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-rw-r--r--include/asm-sh/cpu-sh3/cache.h4
-rw-r--r--include/asm-sh/cpu-sh3/cacheflush.h52
-rw-r--r--include/asm-sh/cpu-sh3/freq.h4
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h8
-rw-r--r--include/asm-sh/cpu-sh3/shmparam.h16
-rw-r--r--include/asm-sh/cpu-sh3/timer.h8
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h15
7 files changed, 46 insertions, 61 deletions
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
index 406aa8d9b947..ffe08d2813f9 100644
--- a/include/asm-sh/cpu-sh3/cache.h
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -26,12 +26,10 @@
26#define CCR_CACHE_ENABLE CCR_CACHE_CE 26#define CCR_CACHE_ENABLE CCR_CACHE_CE
27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF 27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
28 28
29#if defined(CONFIG_CPU_SUBTYPE_SH7705) 29#if defined(CONFIG_CPU_SUBTYPE_SH7705) || defined(CONFIG_CPU_SUBTYPE_SH7710)
30#define CCR3 0xa40000b4 30#define CCR3 0xa40000b4
31#define CCR_CACHE_16KB 0x00010000 31#define CCR_CACHE_16KB 0x00010000
32#define CCR_CACHE_32KB 0x00020000 32#define CCR_CACHE_32KB 0x00020000
33#endif 33#endif
34 34
35
36#endif /* __ASM_CPU_SH3_CACHE_H */ 35#endif /* __ASM_CPU_SH3_CACHE_H */
37
diff --git a/include/asm-sh/cpu-sh3/cacheflush.h b/include/asm-sh/cpu-sh3/cacheflush.h
index f51aed00c68f..03fde97a7fd0 100644
--- a/include/asm-sh/cpu-sh3/cacheflush.h
+++ b/include/asm-sh/cpu-sh3/cacheflush.h
@@ -10,7 +10,7 @@
10#ifndef __ASM_CPU_SH3_CACHEFLUSH_H 10#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
11#define __ASM_CPU_SH3_CACHEFLUSH_H 11#define __ASM_CPU_SH3_CACHEFLUSH_H
12 12
13/* 13/*
14 * Cache flushing: 14 * Cache flushing:
15 * 15 *
16 * - flush_cache_all() flushes entire cache 16 * - flush_cache_all() flushes entire cache
@@ -35,53 +35,33 @@
35 /* 32KB cache, 4kb PAGE sizes need to check bit 12 */ 35 /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
36#define CACHE_ALIAS 0x00001000 36#define CACHE_ALIAS 0x00001000
37 37
38struct page;
39struct mm_struct;
40struct vm_area_struct;
41
42extern void flush_cache_all(void);
43extern void flush_cache_mm(struct mm_struct *mm);
44extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
45 unsigned long end);
46extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
47extern void flush_dcache_page(struct page *pg);
48extern void flush_icache_range(unsigned long start, unsigned long end);
49extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
50
51#define flush_dcache_mmap_lock(mapping) do { } while (0)
52#define flush_dcache_mmap_unlock(mapping) do { } while (0)
53
54/* SH3 has unified cache so no special action needed here */
55#define flush_cache_sigtramp(vaddr) do { } while (0)
56#define flush_page_to_ram(page) do { } while (0)
57#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
58
59#define p3_cache_init() do { } while (0)
60
61#define PG_mapped PG_arch_1 38#define PG_mapped PG_arch_1
62 39
63/* We provide our own get_unmapped_area to avoid cache alias issue */ 40void flush_cache_all(void);
64#define HAVE_ARCH_UNMAPPED_AREA 41void flush_cache_mm(struct mm_struct *mm);
65 42void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
43 unsigned long end);
44void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
45void flush_dcache_page(struct page *pg);
46void flush_icache_range(unsigned long start, unsigned long end);
47void flush_icache_page(struct vm_area_struct *vma, struct page *page);
66#else 48#else
67
68#define flush_cache_all() do { } while (0) 49#define flush_cache_all() do { } while (0)
69#define flush_cache_mm(mm) do { } while (0) 50#define flush_cache_mm(mm) do { } while (0)
70#define flush_cache_range(vma, start, end) do { } while (0) 51#define flush_cache_range(vma, start, end) do { } while (0)
71#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) 52#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
72#define flush_dcache_page(page) do { } while (0) 53#define flush_dcache_page(page) do { } while (0)
73#define flush_dcache_mmap_lock(mapping) do { } while (0)
74#define flush_dcache_mmap_unlock(mapping) do { } while (0)
75#define flush_icache_range(start, end) do { } while (0) 54#define flush_icache_range(start, end) do { } while (0)
76#define flush_icache_page(vma,pg) do { } while (0) 55#define flush_icache_page(vma,pg) do { } while (0)
77#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) 56#endif
78#define flush_cache_sigtramp(vaddr) do { } while (0)
79 57
80#define p3_cache_init() do { } while (0) 58#define flush_dcache_mmap_lock(mapping) do { } while (0)
59#define flush_dcache_mmap_unlock(mapping) do { } while (0)
81 60
82#define HAVE_ARCH_UNMAPPED_AREA 61/* SH3 has unified cache so no special action needed here */
62#define flush_cache_sigtramp(vaddr) do { } while (0)
63#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
83 64
84#endif 65#define p3_cache_init() do { } while (0)
85 66
86#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */ 67#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
87
diff --git a/include/asm-sh/cpu-sh3/freq.h b/include/asm-sh/cpu-sh3/freq.h
index b61b6e331df0..273f3229785c 100644
--- a/include/asm-sh/cpu-sh3/freq.h
+++ b/include/asm-sh/cpu-sh3/freq.h
@@ -18,5 +18,9 @@
18#define MIN_DIVISOR_NR 0 18#define MIN_DIVISOR_NR 0
19#define MAX_DIVISOR_NR 4 19#define MAX_DIVISOR_NR 4
20 20
21#define FRQCR_CKOEN 0x0100
22#define FRQCR_PLLEN 0x0080
23#define FRQCR_PSTBY 0x0040
24
21#endif /* __ASM_CPU_SH3_FREQ_H */ 25#endif /* __ASM_CPU_SH3_FREQ_H */
22 26
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
index a844ea0965b6..bccb7ddb438b 100644
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -27,8 +27,12 @@
27#define TRA 0xffffffd0 27#define TRA 0xffffffd0
28#define EXPEVT 0xffffffd4 28#define EXPEVT 0xffffffd4
29 29
30#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 30#if defined(CONFIG_CPU_SUBTYPE_SH7707) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705) 31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7300) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7705) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7710)
32#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ 36#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
33#else 37#else
34#define INTEVT 0xffffffd8 38#define INTEVT 0xffffffd8
diff --git a/include/asm-sh/cpu-sh3/shmparam.h b/include/asm-sh/cpu-sh3/shmparam.h
deleted file mode 100644
index da5b5eec81ee..000000000000
--- a/include/asm-sh/cpu-sh3/shmparam.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/shmparam.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_SHMPARAM_H
11#define __ASM_CPU_SH3_SHMPARAM_H
12
13#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
14
15#endif /* __ASM_CPU_SH3_SHMPARAM_H */
16
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index 3d8e95e8d10c..b2394cf76f49 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -20,9 +20,14 @@
20 * SH7710 20 * SH7710
21 * SH7720 21 * SH7720
22 * SH7300 22 * SH7300
23 * SH7710
23 * --------------------------------------------------------------------------- 24 * ---------------------------------------------------------------------------
24 */ 25 */
25 26
27#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
28#define TMU_TOCR 0xfffffe90 /* Byte access */
29#endif
30
26#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710) 31#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
27#define TMU_TSTR 0xa412fe92 /* Byte access */ 32#define TMU_TSTR 0xa412fe92 /* Byte access */
28 33
@@ -39,9 +44,6 @@
39#define TMU2_TCR 0xa412feb4 /* Word access */ 44#define TMU2_TCR 0xa412feb4 /* Word access */
40 45
41#else 46#else
42#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
43#define TMU_TOCR 0xfffffe90 /* Byte access */
44#endif
45#define TMU_TSTR 0xfffffe92 /* Byte access */ 47#define TMU_TSTR 0xfffffe92 /* Byte access */
46 48
47#define TMU0_TCOR 0xfffffe94 /* Long access */ 49#define TMU0_TCOR 0xfffffe94 /* Long access */
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
index 0f809dec4e17..9d308cbe9b29 100644
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -11,6 +11,19 @@
11#ifndef __ASM_CPU_SH3_UBC_H 11#ifndef __ASM_CPU_SH3_UBC_H
12#define __ASM_CPU_SH3_UBC_H 12#define __ASM_CPU_SH3_UBC_H
13 13
14#if defined(CONFIG_CPU_SUBTYPE_SH7710)
15#define UBC_BARA 0xa4ffffb0
16#define UBC_BAMRA 0xa4ffffb4
17#define UBC_BBRA 0xa4ffffb8
18#define UBC_BASRA 0xffffffe4
19#define UBC_BARB 0xa4ffffa0
20#define UBC_BAMRB 0xa4ffffa4
21#define UBC_BBRB 0xa4ffffa8
22#define UBC_BASRB 0xffffffe8
23#define UBC_BDRB 0xa4ffff90
24#define UBC_BDMRB 0xa4ffff94
25#define UBC_BRCR 0xa4ffff98
26#else
14#define UBC_BARA 0xffffffb0 27#define UBC_BARA 0xffffffb0
15#define UBC_BAMRA 0xffffffb4 28#define UBC_BAMRA 0xffffffb4
16#define UBC_BBRA 0xffffffb8 29#define UBC_BBRA 0xffffffb8
@@ -22,6 +35,6 @@
22#define UBC_BDRB 0xffffff90 35#define UBC_BDRB 0xffffff90
23#define UBC_BDMRB 0xffffff94 36#define UBC_BDMRB 0xffffff94
24#define UBC_BRCR 0xffffff98 37#define UBC_BRCR 0xffffff98
38#endif
25 39
26#endif /* __ASM_CPU_SH3_UBC_H */ 40#endif /* __ASM_CPU_SH3_UBC_H */
27