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-rw-r--r--include/asm-sh/cpu-sh3/cache.h3
-rw-r--r--include/asm-sh/cpu-sh3/dma.h4
-rw-r--r--include/asm-sh/cpu-sh3/gpio.h3
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h3
-rw-r--r--include/asm-sh/cpu-sh3/timer.h7
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h3
6 files changed, 15 insertions, 8 deletions
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
index 77dd45d82414..56bd838b7db4 100644
--- a/include/asm-sh/cpu-sh3/cache.h
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -33,7 +33,8 @@
33 33
34#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 34#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 35 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
36 defined(CONFIG_CPU_SUBTYPE_SH7720) 36 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7721)
37#define CCR3 0xa40000b4 38#define CCR3 0xa40000b4
38#define CCR_CACHE_16KB 0x00010000 39#define CCR_CACHE_16KB 0x00010000
39#define CCR_CACHE_32KB 0x00020000 40#define CCR_CACHE_32KB 0x00020000
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
index 54bfece328c2..092ff9d872c3 100644
--- a/include/asm-sh/cpu-sh3/dma.h
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -2,7 +2,9 @@
2#define __ASM_CPU_SH3_DMA_H 2#define __ASM_CPU_SH3_DMA_H
3 3
4 4
5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709) 5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7721) || \
7 defined(CONFIG_CPU_SUBTYPE_SH7709)
6#define SH_DMAC_BASE 0xa4010020 8#define SH_DMAC_BASE 0xa4010020
7 9
8#define DMTE0_IRQ 48 10#define DMTE0_IRQ 48
diff --git a/include/asm-sh/cpu-sh3/gpio.h b/include/asm-sh/cpu-sh3/gpio.h
index 48770c1c7bdf..4e53eb314b8f 100644
--- a/include/asm-sh/cpu-sh3/gpio.h
+++ b/include/asm-sh/cpu-sh3/gpio.h
@@ -12,7 +12,8 @@
12#ifndef _CPU_SH3_GPIO_H 12#ifndef _CPU_SH3_GPIO_H
13#define _CPU_SH3_GPIO_H 13#define _CPU_SH3_GPIO_H
14 14
15#if defined(CONFIG_CPU_SUBTYPE_SH7720) 15#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
16 defined(CONFIG_CPU_SUBTYPE_SH7721)
16 17
17/* Control registers */ 18/* Control registers */
18#define PORT_PACR 0xA4050100UL 19#define PORT_PACR 0xA4050100UL
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
index 16c2d63b7e39..ab09da73ce77 100644
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -33,7 +33,8 @@
33 defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 33 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 34 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7712) || \ 35 defined(CONFIG_CPU_SUBTYPE_SH7712) || \
36 defined(CONFIG_CPU_SUBTYPE_SH7720) 36 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7721)
37#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ 38#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
38#else 39#else
39#define INTEVT 0xffffffd8 40#define INTEVT 0xffffffd8
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
index 7b795ac5477c..793acf12aa08 100644
--- a/include/asm-sh/cpu-sh3/timer.h
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -23,12 +23,13 @@
23 * --------------------------------------------------------------------------- 23 * ---------------------------------------------------------------------------
24 */ 24 */
25 25
26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) 26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
27#define TMU_TOCR 0xfffffe90 /* Byte access */ 27#define TMU_TOCR 0xfffffe90 /* Byte access */
28#endif 28#endif
29 29
30#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 30#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7720) 31 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7721)
32#define TMU_012_TSTR 0xa412fe92 /* Byte access */ 33#define TMU_012_TSTR 0xa412fe92 /* Byte access */
33 34
34#define TMU0_TCOR 0xa412fe94 /* Long access */ 35#define TMU0_TCOR 0xa412fe94 /* Long access */
@@ -57,7 +58,7 @@
57#define TMU2_TCOR 0xfffffeac /* Long access */ 58#define TMU2_TCOR 0xfffffeac /* Long access */
58#define TMU2_TCNT 0xfffffeb0 /* Long access */ 59#define TMU2_TCNT 0xfffffeb0 /* Long access */
59#define TMU2_TCR 0xfffffeb4 /* Word access */ 60#define TMU2_TCR 0xfffffeb4 /* Word access */
60#if !defined(CONFIG_CPU_SUBTYPE_SH7720) 61#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
61#define TMU2_TCPR2 0xfffffeb8 /* Long access */ 62#define TMU2_TCPR2 0xfffffeb8 /* Long access */
62#endif 63#endif
63#endif 64#endif
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
index 18467c574534..4e6381d5ff7a 100644
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -12,7 +12,8 @@
12#define __ASM_CPU_SH3_UBC_H 12#define __ASM_CPU_SH3_UBC_H
13 13
14#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 14#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7720) 15 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
16 defined(CONFIG_CPU_SUBTYPE_SH7721)
16#define UBC_BARA 0xa4ffffb0 17#define UBC_BARA 0xa4ffffb0
17#define UBC_BAMRA 0xa4ffffb4 18#define UBC_BAMRA 0xa4ffffb4
18#define UBC_BBRA 0xa4ffffb8 19#define UBC_BBRA 0xa4ffffb8
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-19 03:58:42 -0500