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-rw-r--r--include/asm-sh/cpu-sh3/adc.h28
-rw-r--r--include/asm-sh/cpu-sh3/addrspace.h16
-rw-r--r--include/asm-sh/cpu-sh3/cache.h37
-rw-r--r--include/asm-sh/cpu-sh3/cacheflush.h87
-rw-r--r--include/asm-sh/cpu-sh3/dac.h41
-rw-r--r--include/asm-sh/cpu-sh3/dma.h7
-rw-r--r--include/asm-sh/cpu-sh3/freq.h22
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h28
-rw-r--r--include/asm-sh/cpu-sh3/rtc.h25
-rw-r--r--include/asm-sh/cpu-sh3/shmparam.h16
-rw-r--r--include/asm-sh/cpu-sh3/sigcontext.h17
-rw-r--r--include/asm-sh/cpu-sh3/timer.h64
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h27
-rw-r--r--include/asm-sh/cpu-sh3/watchdog.h25
14 files changed, 440 insertions, 0 deletions
diff --git a/include/asm-sh/cpu-sh3/adc.h b/include/asm-sh/cpu-sh3/adc.h
new file mode 100644
index 000000000000..b289e3ca19a6
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/adc.h
@@ -0,0 +1,28 @@
1#ifndef __ASM_CPU_SH3_ADC_H
2#define __ASM_CPU_SH3_ADC_H
3
4/*
5 * Copyright (C) 2004 Andriy Skulysh
6 */
7
8
9#define ADDRAH 0xa4000080
10#define ADDRAL 0xa4000082
11#define ADDRBH 0xa4000084
12#define ADDRBL 0xa4000086
13#define ADDRCH 0xa4000088
14#define ADDRCL 0xa400008a
15#define ADDRDH 0xa400008c
16#define ADDRDL 0xa400008e
17#define ADCSR 0xa4000090
18
19#define ADCSR_ADF 0x80
20#define ADCSR_ADIE 0x40
21#define ADCSR_ADST 0x20
22#define ADCSR_MULTI 0x10
23#define ADCSR_CKS 0x08
24#define ADCSR_CH_MASK 0x07
25
26#define ADCR 0xa4000092
27
28#endif /* __ASM_CPU_SH3_ADC_H */
diff --git a/include/asm-sh/cpu-sh3/addrspace.h b/include/asm-sh/cpu-sh3/addrspace.h
new file mode 100644
index 000000000000..872e9e1b548c
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/addrspace.h
@@ -0,0 +1,16 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH-3 CPUs.
9 */
10#ifndef __ASM_CPU_SH3_ADDRSPACE_H
11#define __ASM_CPU_SH3_ADDRSPACE_H
12
13/* Should fill here */
14
15#endif /* __ASM_CPU_SH3_ADDRSPACE_H */
16
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
new file mode 100644
index 000000000000..406aa8d9b947
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/cache.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-sh/cpu-sh3/cache.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHE_H
11#define __ASM_CPU_SH3_CACHE_H
12
13#define L1_CACHE_SHIFT 4
14
15#define CCR 0xffffffec /* Address of Cache Control Register */
16
17#define CCR_CACHE_CE 0x01 /* Cache Enable */
18#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
19#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
20#define CCR_CACHE_CF 0x08 /* Cache Flush */
21#define CCR_CACHE_ORA 0x20 /* RAM mode */
22
23#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
24#define CACHE_PHYSADDR_MASK 0x1ffffc00
25
26#define CCR_CACHE_ENABLE CCR_CACHE_CE
27#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
28
29#if defined(CONFIG_CPU_SUBTYPE_SH7705)
30#define CCR3 0xa40000b4
31#define CCR_CACHE_16KB 0x00010000
32#define CCR_CACHE_32KB 0x00020000
33#endif
34
35
36#endif /* __ASM_CPU_SH3_CACHE_H */
37
diff --git a/include/asm-sh/cpu-sh3/cacheflush.h b/include/asm-sh/cpu-sh3/cacheflush.h
new file mode 100644
index 000000000000..f51aed00c68f
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/cacheflush.h
@@ -0,0 +1,87 @@
1/*
2 * include/asm-sh/cpu-sh3/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
11#define __ASM_CPU_SH3_CACHEFLUSH_H
12
13/*
14 * Cache flushing:
15 *
16 * - flush_cache_all() flushes entire cache
17 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
18 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
19 * - flush_cache_range(vma, start, end) flushes a range of pages
20 *
21 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
22 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
23 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
24 *
25 * Caches are indexed (effectively) by physical address on SH-3, so
26 * we don't need them.
27 */
28
29#if defined(CONFIG_SH7705_CACHE_32KB)
30
31/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
32 * SH4. Unlike the SH4 this is a unified cache so we need to do some work
33 * in mmap when 'exec'ing a new binary
34 */
35 /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
36#define CACHE_ALIAS 0x00001000
37
38struct page;
39struct mm_struct;
40struct vm_area_struct;
41
42extern void flush_cache_all(void);
43extern void flush_cache_mm(struct mm_struct *mm);
44extern void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
45 unsigned long end);
46extern void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
47extern void flush_dcache_page(struct page *pg);
48extern void flush_icache_range(unsigned long start, unsigned long end);
49extern void flush_icache_page(struct vm_area_struct *vma, struct page *page);
50
51#define flush_dcache_mmap_lock(mapping) do { } while (0)
52#define flush_dcache_mmap_unlock(mapping) do { } while (0)
53
54/* SH3 has unified cache so no special action needed here */
55#define flush_cache_sigtramp(vaddr) do { } while (0)
56#define flush_page_to_ram(page) do { } while (0)
57#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
58
59#define p3_cache_init() do { } while (0)
60
61#define PG_mapped PG_arch_1
62
63/* We provide our own get_unmapped_area to avoid cache alias issue */
64#define HAVE_ARCH_UNMAPPED_AREA
65
66#else
67
68#define flush_cache_all() do { } while (0)
69#define flush_cache_mm(mm) do { } while (0)
70#define flush_cache_range(vma, start, end) do { } while (0)
71#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
72#define flush_dcache_page(page) do { } while (0)
73#define flush_dcache_mmap_lock(mapping) do { } while (0)
74#define flush_dcache_mmap_unlock(mapping) do { } while (0)
75#define flush_icache_range(start, end) do { } while (0)
76#define flush_icache_page(vma,pg) do { } while (0)
77#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
78#define flush_cache_sigtramp(vaddr) do { } while (0)
79
80#define p3_cache_init() do { } while (0)
81
82#define HAVE_ARCH_UNMAPPED_AREA
83
84#endif
85
86#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
87
diff --git a/include/asm-sh/cpu-sh3/dac.h b/include/asm-sh/cpu-sh3/dac.h
new file mode 100644
index 000000000000..05fda8316ebc
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/dac.h
@@ -0,0 +1,41 @@
1#ifndef __ASM_CPU_SH3_DAC_H
2#define __ASM_CPU_SH3_DAC_H
3
4/*
5 * Copyright (C) 2003 Andriy Skulysh
6 */
7
8
9#define DADR0 0xa40000a0
10#define DADR1 0xa40000a2
11#define DACR 0xa40000a4
12#define DACR_DAOE1 0x80
13#define DACR_DAOE0 0x40
14#define DACR_DAE 0x20
15
16
17static __inline__ void sh_dac_enable(int channel)
18{
19 unsigned char v;
20 v = ctrl_inb(DACR);
21 if(channel) v |= DACR_DAOE1;
22 else v |= DACR_DAOE0;
23 ctrl_outb(v,DACR);
24}
25
26static __inline__ void sh_dac_disable(int channel)
27{
28 unsigned char v;
29 v = ctrl_inb(DACR);
30 if(channel) v &= ~DACR_DAOE1;
31 else v &= ~DACR_DAOE0;
32 ctrl_outb(v,DACR);
33}
34
35static __inline__ void sh_dac_output(u8 value, int channel)
36{
37 if(channel) ctrl_outb(value,DADR1);
38 else ctrl_outb(value,DADR0);
39}
40
41#endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
new file mode 100644
index 000000000000..b972e715f9ee
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/dma.h
@@ -0,0 +1,7 @@
1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H
3
4#define SH_DMAC_BASE 0xa4000020
5
6#endif /* __ASM_CPU_SH3_DMA_H */
7
diff --git a/include/asm-sh/cpu-sh3/freq.h b/include/asm-sh/cpu-sh3/freq.h
new file mode 100644
index 000000000000..b61b6e331df0
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/freq.h
@@ -0,0 +1,22 @@
1/*
2 * include/asm-sh/cpu-sh3/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_FREQ_H
11#define __ASM_CPU_SH3_FREQ_H
12
13#if defined(CONFIG_CPU_SUBTYPE_SH7300)
14#define FRQCR 0xa415ff80
15#else
16#define FRQCR 0xffffff80
17#endif
18#define MIN_DIVISOR_NR 0
19#define MAX_DIVISOR_NR 4
20
21#endif /* __ASM_CPU_SH3_FREQ_H */
22
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
new file mode 100644
index 000000000000..5cfaa6bcf1ed
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -0,0 +1,28 @@
1/*
2 * include/asm-sh/cpu-sh3/mmu_context.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
11#define __ASM_CPU_SH3_MMU_CONTEXT_H
12
13#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
14#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
15#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
16#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
17
18#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
19
20#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
21#define MMU_PAGE_ASSOC_BIT 0x80
22
23#define MMU_NTLB_ENTRIES 128 /* for 7708 */
24#define MMU_NTLB_WAYS 4
25#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
26
27#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */
28
diff --git a/include/asm-sh/cpu-sh3/rtc.h b/include/asm-sh/cpu-sh3/rtc.h
new file mode 100644
index 000000000000..2d926671115a
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/rtc.h
@@ -0,0 +1,25 @@
1#ifndef __ASM_CPU_SH3_RTC_H
2#define __ASM_CPU_SH3_RTC_H
3
4/* SH-3 RTC */
5#define R64CNT 0xfffffec0
6#define RSECCNT 0xfffffec2
7#define RMINCNT 0xfffffec4
8#define RHRCNT 0xfffffec6
9#define RWKCNT 0xfffffec8
10#define RDAYCNT 0xfffffeca
11#define RMONCNT 0xfffffecc
12#define RYRCNT 0xfffffece
13#define RSECAR 0xfffffed0
14#define RMINAR 0xfffffed2
15#define RHRAR 0xfffffed4
16#define RWKAR 0xfffffed6
17#define RDAYAR 0xfffffed8
18#define RMONAR 0xfffffeda
19#define RCR1 0xfffffedc
20#define RCR2 0xfffffede
21
22#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
23
24#endif /* __ASM_CPU_SH3_RTC_H */
25
diff --git a/include/asm-sh/cpu-sh3/shmparam.h b/include/asm-sh/cpu-sh3/shmparam.h
new file mode 100644
index 000000000000..da5b5eec81ee
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/shmparam.h
@@ -0,0 +1,16 @@
1/*
2 * include/asm-sh/cpu-sh3/shmparam.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_SHMPARAM_H
11#define __ASM_CPU_SH3_SHMPARAM_H
12
13#define SHMLBA PAGE_SIZE /* attach addr a multiple of this */
14
15#endif /* __ASM_CPU_SH3_SHMPARAM_H */
16
diff --git a/include/asm-sh/cpu-sh3/sigcontext.h b/include/asm-sh/cpu-sh3/sigcontext.h
new file mode 100644
index 000000000000..17310dc03dcd
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/sigcontext.h
@@ -0,0 +1,17 @@
1#ifndef __ASM_CPU_SH3_SIGCONTEXT_H
2#define __ASM_CPU_SH3_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15};
16
17#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
new file mode 100644
index 000000000000..3d8e95e8d10c
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/timer.h
@@ -0,0 +1,64 @@
1/*
2 * include/asm-sh/cpu-sh3/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_TIMER_H
11#define __ASM_CPU_SH3_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH3 processors
16 * SH7706
17 * SH7709S
18 * SH7727
19 * SH7729R
20 * SH7710
21 * SH7720
22 * SH7300
23 * ---------------------------------------------------------------------------
24 */
25
26#if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7710)
27#define TMU_TSTR 0xa412fe92 /* Byte access */
28
29#define TMU0_TCOR 0xa412fe94 /* Long access */
30#define TMU0_TCNT 0xa412fe98 /* Long access */
31#define TMU0_TCR 0xa412fe9c /* Word access */
32
33#define TMU1_TCOR 0xa412fea0 /* Long access */
34#define TMU1_TCNT 0xa412fea4 /* Long access */
35#define TMU1_TCR 0xa412fea8 /* Word access */
36
37#define TMU2_TCOR 0xa412feac /* Long access */
38#define TMU2_TCNT 0xa412feb0 /* Long access */
39#define TMU2_TCR 0xa412feb4 /* Word access */
40
41#else
42#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
43#define TMU_TOCR 0xfffffe90 /* Byte access */
44#endif
45#define TMU_TSTR 0xfffffe92 /* Byte access */
46
47#define TMU0_TCOR 0xfffffe94 /* Long access */
48#define TMU0_TCNT 0xfffffe98 /* Long access */
49#define TMU0_TCR 0xfffffe9c /* Word access */
50
51#define TMU1_TCOR 0xfffffea0 /* Long access */
52#define TMU1_TCNT 0xfffffea4 /* Long access */
53#define TMU1_TCR 0xfffffea8 /* Word access */
54
55#define TMU2_TCOR 0xfffffeac /* Long access */
56#define TMU2_TCNT 0xfffffeb0 /* Long access */
57#define TMU2_TCR 0xfffffeb4 /* Word access */
58#if !defined(CONFIG_CPU_SUBTYPE_SH7727)
59#define TMU2_TCPR2 0xfffffeb8 /* Long access */
60#endif
61#endif
62
63#endif /* __ASM_CPU_SH3_TIMER_H */
64
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
new file mode 100644
index 000000000000..0f809dec4e17
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/ubc.h
@@ -0,0 +1,27 @@
1/*
2 * include/asm-sh/cpu-sh3/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH3_UBC_H
12#define __ASM_CPU_SH3_UBC_H
13
14#define UBC_BARA 0xffffffb0
15#define UBC_BAMRA 0xffffffb4
16#define UBC_BBRA 0xffffffb8
17#define UBC_BASRA 0xffffffe4
18#define UBC_BARB 0xffffffa0
19#define UBC_BAMRB 0xffffffa4
20#define UBC_BBRB 0xffffffa8
21#define UBC_BASRB 0xffffffe8
22#define UBC_BDRB 0xffffff90
23#define UBC_BDMRB 0xffffff94
24#define UBC_BRCR 0xffffff98
25
26#endif /* __ASM_CPU_SH3_UBC_H */
27
diff --git a/include/asm-sh/cpu-sh3/watchdog.h b/include/asm-sh/cpu-sh3/watchdog.h
new file mode 100644
index 000000000000..4ee0347298d8
--- /dev/null
+++ b/include/asm-sh/cpu-sh3/watchdog.h
@@ -0,0 +1,25 @@
1/*
2 * include/asm-sh/cpu-sh3/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_WATCHDOG_H
11#define __ASM_CPU_SH3_WATCHDOG_H
12
13/* Register definitions */
14#define WTCNT 0xffffff84
15#define WTCSR 0xffffff86
16
17/* Bit definitions */
18#define WTCSR_TME 0x80
19#define WTCSR_WT 0x40
20#define WTCSR_RSTS 0x20
21#define WTCSR_WOVF 0x10
22#define WTCSR_IOVF 0x08
23
24#endif /* __ASM_CPU_SH3_WATCHDOG_H */
25
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