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-rw-r--r--include/asm-sh/cpu-sh3/adc.h28
-rw-r--r--include/asm-sh/cpu-sh3/addrspace.h19
-rw-r--r--include/asm-sh/cpu-sh3/cache.h43
-rw-r--r--include/asm-sh/cpu-sh3/cacheflush.h70
-rw-r--r--include/asm-sh/cpu-sh3/dac.h41
-rw-r--r--include/asm-sh/cpu-sh3/dma.h51
-rw-r--r--include/asm-sh/cpu-sh3/freq.h27
-rw-r--r--include/asm-sh/cpu-sh3/gpio.h67
-rw-r--r--include/asm-sh/cpu-sh3/mmu_context.h44
-rw-r--r--include/asm-sh/cpu-sh3/rtc.h8
-rw-r--r--include/asm-sh/cpu-sh3/sigcontext.h17
-rw-r--r--include/asm-sh/cpu-sh3/timer.h67
-rw-r--r--include/asm-sh/cpu-sh3/ubc.h42
-rw-r--r--include/asm-sh/cpu-sh3/watchdog.h25
14 files changed, 0 insertions, 549 deletions
diff --git a/include/asm-sh/cpu-sh3/adc.h b/include/asm-sh/cpu-sh3/adc.h
deleted file mode 100644
index b289e3ca19a6..000000000000
--- a/include/asm-sh/cpu-sh3/adc.h
+++ /dev/null
@@ -1,28 +0,0 @@
1#ifndef __ASM_CPU_SH3_ADC_H
2#define __ASM_CPU_SH3_ADC_H
3
4/*
5 * Copyright (C) 2004 Andriy Skulysh
6 */
7
8
9#define ADDRAH 0xa4000080
10#define ADDRAL 0xa4000082
11#define ADDRBH 0xa4000084
12#define ADDRBL 0xa4000086
13#define ADDRCH 0xa4000088
14#define ADDRCL 0xa400008a
15#define ADDRDH 0xa400008c
16#define ADDRDL 0xa400008e
17#define ADCSR 0xa4000090
18
19#define ADCSR_ADF 0x80
20#define ADCSR_ADIE 0x40
21#define ADCSR_ADST 0x20
22#define ADCSR_MULTI 0x10
23#define ADCSR_CKS 0x08
24#define ADCSR_CH_MASK 0x07
25
26#define ADCR 0xa4000092
27
28#endif /* __ASM_CPU_SH3_ADC_H */
diff --git a/include/asm-sh/cpu-sh3/addrspace.h b/include/asm-sh/cpu-sh3/addrspace.h
deleted file mode 100644
index 0f94726c7d62..000000000000
--- a/include/asm-sh/cpu-sh3/addrspace.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999 by Kaz Kojima
7 *
8 * Defitions for the address spaces of the SH-3 CPUs.
9 */
10#ifndef __ASM_CPU_SH3_ADDRSPACE_H
11#define __ASM_CPU_SH3_ADDRSPACE_H
12
13#define P0SEG 0x00000000
14#define P1SEG 0x80000000
15#define P2SEG 0xa0000000
16#define P3SEG 0xc0000000
17#define P4SEG 0xe0000000
18
19#endif /* __ASM_CPU_SH3_ADDRSPACE_H */
diff --git a/include/asm-sh/cpu-sh3/cache.h b/include/asm-sh/cpu-sh3/cache.h
deleted file mode 100644
index bee2d81c56bf..000000000000
--- a/include/asm-sh/cpu-sh3/cache.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/cache.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHE_H
11#define __ASM_CPU_SH3_CACHE_H
12
13#define L1_CACHE_SHIFT 4
14
15#define SH_CACHE_VALID 1
16#define SH_CACHE_UPDATED 2
17#define SH_CACHE_COMBINED 4
18#define SH_CACHE_ASSOC 8
19
20#define CCR 0xffffffec /* Address of Cache Control Register */
21
22#define CCR_CACHE_CE 0x01 /* Cache Enable */
23#define CCR_CACHE_WT 0x02 /* Write-Through (for P0,U0,P3) (else writeback) */
24#define CCR_CACHE_CB 0x04 /* Write-Back (for P1) (else writethrough) */
25#define CCR_CACHE_CF 0x08 /* Cache Flush */
26#define CCR_CACHE_ORA 0x20 /* RAM mode */
27
28#define CACHE_OC_ADDRESS_ARRAY 0xf0000000
29#define CACHE_PHYSADDR_MASK 0x1ffffc00
30
31#define CCR_CACHE_ENABLE CCR_CACHE_CE
32#define CCR_CACHE_INVALIDATE CCR_CACHE_CF
33
34#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
36 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7721)
38#define CCR3_REG 0xa40000b4
39#define CCR_CACHE_16KB 0x00010000
40#define CCR_CACHE_32KB 0x00020000
41#endif
42
43#endif /* __ASM_CPU_SH3_CACHE_H */
diff --git a/include/asm-sh/cpu-sh3/cacheflush.h b/include/asm-sh/cpu-sh3/cacheflush.h
deleted file mode 100644
index f70d8ef76a15..000000000000
--- a/include/asm-sh/cpu-sh3/cacheflush.h
+++ /dev/null
@@ -1,70 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/cacheflush.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_CACHEFLUSH_H
11#define __ASM_CPU_SH3_CACHEFLUSH_H
12
13/*
14 * Cache flushing:
15 *
16 * - flush_cache_all() flushes entire cache
17 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
18 * - flush_cache_dup mm(mm) handles cache flushing when forking
19 * - flush_cache_page(mm, vmaddr, pfn) flushes a single page
20 * - flush_cache_range(vma, start, end) flushes a range of pages
21 *
22 * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
23 * - flush_icache_range(start, end) flushes(invalidates) a range for icache
24 * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache
25 *
26 * Caches are indexed (effectively) by physical address on SH-3, so
27 * we don't need them.
28 */
29
30#if defined(CONFIG_SH7705_CACHE_32KB)
31
32/* SH7705 is an SH3 processor with 32KB cache. This has alias issues like the
33 * SH4. Unlike the SH4 this is a unified cache so we need to do some work
34 * in mmap when 'exec'ing a new binary
35 */
36 /* 32KB cache, 4kb PAGE sizes need to check bit 12 */
37#define CACHE_ALIAS 0x00001000
38
39#define PG_mapped PG_arch_1
40
41void flush_cache_all(void);
42void flush_cache_mm(struct mm_struct *mm);
43#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
44void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
45 unsigned long end);
46void flush_cache_page(struct vm_area_struct *vma, unsigned long addr, unsigned long pfn);
47void flush_dcache_page(struct page *pg);
48void flush_icache_range(unsigned long start, unsigned long end);
49void flush_icache_page(struct vm_area_struct *vma, struct page *page);
50#else
51#define flush_cache_all() do { } while (0)
52#define flush_cache_mm(mm) do { } while (0)
53#define flush_cache_dup_mm(mm) do { } while (0)
54#define flush_cache_range(vma, start, end) do { } while (0)
55#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
56#define flush_dcache_page(page) do { } while (0)
57#define flush_icache_range(start, end) do { } while (0)
58#define flush_icache_page(vma,pg) do { } while (0)
59#endif
60
61#define flush_dcache_mmap_lock(mapping) do { } while (0)
62#define flush_dcache_mmap_unlock(mapping) do { } while (0)
63
64/* SH3 has unified cache so no special action needed here */
65#define flush_cache_sigtramp(vaddr) do { } while (0)
66#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
67
68#define p3_cache_init() do { } while (0)
69
70#endif /* __ASM_CPU_SH3_CACHEFLUSH_H */
diff --git a/include/asm-sh/cpu-sh3/dac.h b/include/asm-sh/cpu-sh3/dac.h
deleted file mode 100644
index 05fda8316ebc..000000000000
--- a/include/asm-sh/cpu-sh3/dac.h
+++ /dev/null
@@ -1,41 +0,0 @@
1#ifndef __ASM_CPU_SH3_DAC_H
2#define __ASM_CPU_SH3_DAC_H
3
4/*
5 * Copyright (C) 2003 Andriy Skulysh
6 */
7
8
9#define DADR0 0xa40000a0
10#define DADR1 0xa40000a2
11#define DACR 0xa40000a4
12#define DACR_DAOE1 0x80
13#define DACR_DAOE0 0x40
14#define DACR_DAE 0x20
15
16
17static __inline__ void sh_dac_enable(int channel)
18{
19 unsigned char v;
20 v = ctrl_inb(DACR);
21 if(channel) v |= DACR_DAOE1;
22 else v |= DACR_DAOE0;
23 ctrl_outb(v,DACR);
24}
25
26static __inline__ void sh_dac_disable(int channel)
27{
28 unsigned char v;
29 v = ctrl_inb(DACR);
30 if(channel) v &= ~DACR_DAOE1;
31 else v &= ~DACR_DAOE0;
32 ctrl_outb(v,DACR);
33}
34
35static __inline__ void sh_dac_output(u8 value, int channel)
36{
37 if(channel) ctrl_outb(value,DADR1);
38 else ctrl_outb(value,DADR0);
39}
40
41#endif /* __ASM_CPU_SH3_DAC_H */
diff --git a/include/asm-sh/cpu-sh3/dma.h b/include/asm-sh/cpu-sh3/dma.h
deleted file mode 100644
index 6813c3220a1d..000000000000
--- a/include/asm-sh/cpu-sh3/dma.h
+++ /dev/null
@@ -1,51 +0,0 @@
1#ifndef __ASM_CPU_SH3_DMA_H
2#define __ASM_CPU_SH3_DMA_H
3
4
5#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
6 defined(CONFIG_CPU_SUBTYPE_SH7721)
7#define SH_DMAC_BASE 0xa4010020
8#else
9#define SH_DMAC_BASE 0xa4000020
10#endif
11
12#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
13#define DMTE0_IRQ 48
14#define DMTE1_IRQ 49
15#define DMTE2_IRQ 50
16#define DMTE3_IRQ 51
17#define DMTE4_IRQ 76
18#define DMTE5_IRQ 77
19#endif
20
21/* Definitions for the SuperH DMAC */
22#define TM_BURST 0x00000020
23#define TS_8 0x00000000
24#define TS_16 0x00000008
25#define TS_32 0x00000010
26#define TS_128 0x00000018
27
28#define CHCR_TS_MASK 0x18
29#define CHCR_TS_SHIFT 3
30
31#define DMAOR_INIT DMAOR_DME
32
33/*
34 * The SuperH DMAC supports a number of transmit sizes, we list them here,
35 * with their respective values as they appear in the CHCR registers.
36 */
37enum {
38 XMIT_SZ_8BIT,
39 XMIT_SZ_16BIT,
40 XMIT_SZ_32BIT,
41 XMIT_SZ_128BIT,
42};
43
44static unsigned int ts_shift[] __maybe_unused = {
45 [XMIT_SZ_8BIT] = 0,
46 [XMIT_SZ_16BIT] = 1,
47 [XMIT_SZ_32BIT] = 2,
48 [XMIT_SZ_128BIT] = 4,
49};
50
51#endif /* __ASM_CPU_SH3_DMA_H */
diff --git a/include/asm-sh/cpu-sh3/freq.h b/include/asm-sh/cpu-sh3/freq.h
deleted file mode 100644
index 53c62302b2e3..000000000000
--- a/include/asm-sh/cpu-sh3/freq.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/freq.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_FREQ_H
11#define __ASM_CPU_SH3_FREQ_H
12
13#ifdef CONFIG_CPU_SUBTYPE_SH7712
14#define FRQCR 0xA415FF80
15#else
16#define FRQCR 0xffffff80
17#endif
18
19#define MIN_DIVISOR_NR 0
20#define MAX_DIVISOR_NR 4
21
22#define FRQCR_CKOEN 0x0100
23#define FRQCR_PLLEN 0x0080
24#define FRQCR_PSTBY 0x0040
25
26#endif /* __ASM_CPU_SH3_FREQ_H */
27
diff --git a/include/asm-sh/cpu-sh3/gpio.h b/include/asm-sh/cpu-sh3/gpio.h
deleted file mode 100644
index 4e53eb314b8f..000000000000
--- a/include/asm-sh/cpu-sh3/gpio.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/gpio.h
3 *
4 * Copyright (C) 2007 Markus Brunner, Mark Jonas
5 *
6 * Addresses for the Pin Function Controller
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#ifndef _CPU_SH3_GPIO_H
13#define _CPU_SH3_GPIO_H
14
15#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
16 defined(CONFIG_CPU_SUBTYPE_SH7721)
17
18/* Control registers */
19#define PORT_PACR 0xA4050100UL
20#define PORT_PBCR 0xA4050102UL
21#define PORT_PCCR 0xA4050104UL
22#define PORT_PDCR 0xA4050106UL
23#define PORT_PECR 0xA4050108UL
24#define PORT_PFCR 0xA405010AUL
25#define PORT_PGCR 0xA405010CUL
26#define PORT_PHCR 0xA405010EUL
27#define PORT_PJCR 0xA4050110UL
28#define PORT_PKCR 0xA4050112UL
29#define PORT_PLCR 0xA4050114UL
30#define PORT_PMCR 0xA4050116UL
31#define PORT_PPCR 0xA4050118UL
32#define PORT_PRCR 0xA405011AUL
33#define PORT_PSCR 0xA405011CUL
34#define PORT_PTCR 0xA405011EUL
35#define PORT_PUCR 0xA4050120UL
36#define PORT_PVCR 0xA4050122UL
37
38/* Data registers */
39#define PORT_PADR 0xA4050140UL
40/* Address of PORT_PBDR is wrong in the datasheet, see errata 2005-09-21 */
41#define PORT_PBDR 0xA4050142UL
42#define PORT_PCDR 0xA4050144UL
43#define PORT_PDDR 0xA4050146UL
44#define PORT_PEDR 0xA4050148UL
45#define PORT_PFDR 0xA405014AUL
46#define PORT_PGDR 0xA405014CUL
47#define PORT_PHDR 0xA405014EUL
48#define PORT_PJDR 0xA4050150UL
49#define PORT_PKDR 0xA4050152UL
50#define PORT_PLDR 0xA4050154UL
51#define PORT_PMDR 0xA4050156UL
52#define PORT_PPDR 0xA4050158UL
53#define PORT_PRDR 0xA405015AUL
54#define PORT_PSDR 0xA405015CUL
55#define PORT_PTDR 0xA405015EUL
56#define PORT_PUDR 0xA4050160UL
57#define PORT_PVDR 0xA4050162UL
58
59/* Pin Select Registers */
60#define PORT_PSELA 0xA4050124UL
61#define PORT_PSELB 0xA4050126UL
62#define PORT_PSELC 0xA4050128UL
63#define PORT_PSELD 0xA405012AUL
64
65#endif
66
67#endif
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
deleted file mode 100644
index ab09da73ce77..000000000000
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/mmu_context.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_MMU_CONTEXT_H
11#define __ASM_CPU_SH3_MMU_CONTEXT_H
12
13#define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */
14#define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */
15#define MMU_TTB 0xFFFFFFF8 /* Translation table base register */
16#define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */
17
18#define MMUCR 0xFFFFFFE0 /* MMU Control Register */
19
20#define MMU_TLB_ADDRESS_ARRAY 0xF2000000
21#define MMU_PAGE_ASSOC_BIT 0x80
22
23#define MMU_NTLB_ENTRIES 128 /* for 7708 */
24#define MMU_NTLB_WAYS 4
25#define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */
26
27#define TRA 0xffffffd0
28#define EXPEVT 0xffffffd4
29
30#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7706) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7707) || \
33 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
34 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
35 defined(CONFIG_CPU_SUBTYPE_SH7712) || \
36 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
37 defined(CONFIG_CPU_SUBTYPE_SH7721)
38#define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
39#else
40#define INTEVT 0xffffffd8
41#endif
42
43#endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */
44
diff --git a/include/asm-sh/cpu-sh3/rtc.h b/include/asm-sh/cpu-sh3/rtc.h
deleted file mode 100644
index 319404aaee37..000000000000
--- a/include/asm-sh/cpu-sh3/rtc.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ASM_SH_CPU_SH3_RTC_H
2#define __ASM_SH_CPU_SH3_RTC_H
3
4#define rtc_reg_size sizeof(u16)
5#define RTC_BIT_INVERTED 0 /* No bug on SH7708, SH7709A */
6#define RTC_DEF_CAPABILITIES 0UL
7
8#endif /* __ASM_SH_CPU_SH3_RTC_H */
diff --git a/include/asm-sh/cpu-sh3/sigcontext.h b/include/asm-sh/cpu-sh3/sigcontext.h
deleted file mode 100644
index 17310dc03dcd..000000000000
--- a/include/asm-sh/cpu-sh3/sigcontext.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef __ASM_CPU_SH3_SIGCONTEXT_H
2#define __ASM_CPU_SH3_SIGCONTEXT_H
3
4struct sigcontext {
5 unsigned long oldmask;
6
7 /* CPU registers */
8 unsigned long sc_regs[16];
9 unsigned long sc_pc;
10 unsigned long sc_pr;
11 unsigned long sc_sr;
12 unsigned long sc_gbr;
13 unsigned long sc_mach;
14 unsigned long sc_macl;
15};
16
17#endif /* __ASM_CPU_SH3_SIGCONTEXT_H */
diff --git a/include/asm-sh/cpu-sh3/timer.h b/include/asm-sh/cpu-sh3/timer.h
deleted file mode 100644
index 793acf12aa08..000000000000
--- a/include/asm-sh/cpu-sh3/timer.h
+++ /dev/null
@@ -1,67 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/timer.h
3 *
4 * Copyright (C) 2004 Lineo Solutions, Inc.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_TIMER_H
11#define __ASM_CPU_SH3_TIMER_H
12
13/*
14 * ---------------------------------------------------------------------------
15 * TMU Common definitions for SH3 processors
16 * SH7706
17 * SH7709S
18 * SH7727
19 * SH7729R
20 * SH7710
21 * SH7720
22 * SH7710
23 * ---------------------------------------------------------------------------
24 */
25
26#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
27#define TMU_TOCR 0xfffffe90 /* Byte access */
28#endif
29
30#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7721)
33#define TMU_012_TSTR 0xa412fe92 /* Byte access */
34
35#define TMU0_TCOR 0xa412fe94 /* Long access */
36#define TMU0_TCNT 0xa412fe98 /* Long access */
37#define TMU0_TCR 0xa412fe9c /* Word access */
38
39#define TMU1_TCOR 0xa412fea0 /* Long access */
40#define TMU1_TCNT 0xa412fea4 /* Long access */
41#define TMU1_TCR 0xa412fea8 /* Word access */
42
43#define TMU2_TCOR 0xa412feac /* Long access */
44#define TMU2_TCNT 0xa412feb0 /* Long access */
45#define TMU2_TCR 0xa412feb4 /* Word access */
46
47#else
48#define TMU_012_TSTR 0xfffffe92 /* Byte access */
49
50#define TMU0_TCOR 0xfffffe94 /* Long access */
51#define TMU0_TCNT 0xfffffe98 /* Long access */
52#define TMU0_TCR 0xfffffe9c /* Word access */
53
54#define TMU1_TCOR 0xfffffea0 /* Long access */
55#define TMU1_TCNT 0xfffffea4 /* Long access */
56#define TMU1_TCR 0xfffffea8 /* Word access */
57
58#define TMU2_TCOR 0xfffffeac /* Long access */
59#define TMU2_TCNT 0xfffffeb0 /* Long access */
60#define TMU2_TCR 0xfffffeb4 /* Word access */
61#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
62#define TMU2_TCPR2 0xfffffeb8 /* Long access */
63#endif
64#endif
65
66#endif /* __ASM_CPU_SH3_TIMER_H */
67
diff --git a/include/asm-sh/cpu-sh3/ubc.h b/include/asm-sh/cpu-sh3/ubc.h
deleted file mode 100644
index 4e6381d5ff7a..000000000000
--- a/include/asm-sh/cpu-sh3/ubc.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/ubc.h
3 *
4 * Copyright (C) 1999 Niibe Yutaka
5 * Copyright (C) 2003 Paul Mundt
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11#ifndef __ASM_CPU_SH3_UBC_H
12#define __ASM_CPU_SH3_UBC_H
13
14#if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
15 defined(CONFIG_CPU_SUBTYPE_SH7720) || \
16 defined(CONFIG_CPU_SUBTYPE_SH7721)
17#define UBC_BARA 0xa4ffffb0
18#define UBC_BAMRA 0xa4ffffb4
19#define UBC_BBRA 0xa4ffffb8
20#define UBC_BASRA 0xffffffe4
21#define UBC_BARB 0xa4ffffa0
22#define UBC_BAMRB 0xa4ffffa4
23#define UBC_BBRB 0xa4ffffa8
24#define UBC_BASRB 0xffffffe8
25#define UBC_BDRB 0xa4ffff90
26#define UBC_BDMRB 0xa4ffff94
27#define UBC_BRCR 0xa4ffff98
28#else
29#define UBC_BARA 0xffffffb0
30#define UBC_BAMRA 0xffffffb4
31#define UBC_BBRA 0xffffffb8
32#define UBC_BASRA 0xffffffe4
33#define UBC_BARB 0xffffffa0
34#define UBC_BAMRB 0xffffffa4
35#define UBC_BBRB 0xffffffa8
36#define UBC_BASRB 0xffffffe8
37#define UBC_BDRB 0xffffff90
38#define UBC_BDMRB 0xffffff94
39#define UBC_BRCR 0xffffff98
40#endif
41
42#endif /* __ASM_CPU_SH3_UBC_H */
diff --git a/include/asm-sh/cpu-sh3/watchdog.h b/include/asm-sh/cpu-sh3/watchdog.h
deleted file mode 100644
index 4ee0347298d8..000000000000
--- a/include/asm-sh/cpu-sh3/watchdog.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * include/asm-sh/cpu-sh3/watchdog.h
3 *
4 * Copyright (C) 2002, 2003 Paul Mundt
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10#ifndef __ASM_CPU_SH3_WATCHDOG_H
11#define __ASM_CPU_SH3_WATCHDOG_H
12
13/* Register definitions */
14#define WTCNT 0xffffff84
15#define WTCSR 0xffffff86
16
17/* Bit definitions */
18#define WTCSR_TME 0x80
19#define WTCSR_WT 0x40
20#define WTCSR_RSTS 0x20
21#define WTCSR_WOVF 0x10
22#define WTCSR_IOVF 0x08
23
24#endif /* __ASM_CPU_SH3_WATCHDOG_H */
25
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