aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-sh/bigsur/bigsur.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-sh/bigsur/bigsur.h')
-rw-r--r--include/asm-sh/bigsur/bigsur.h80
1 files changed, 80 insertions, 0 deletions
diff --git a/include/asm-sh/bigsur/bigsur.h b/include/asm-sh/bigsur/bigsur.h
new file mode 100644
index 000000000000..427245f93589
--- /dev/null
+++ b/include/asm-sh/bigsur/bigsur.h
@@ -0,0 +1,80 @@
1/*
2 *
3 * Hitachi Big Sur Eval Board support
4 *
5 * Dustin McIntire (dustin@sensoria.com)
6 *
7 * May be copied or modified under the terms of the GNU General Public
8 * License. See linux/COPYING for more information.
9 *
10 * Derived from Hitachi SH7751 reference manual
11 *
12 */
13
14#ifndef _ASM_BIGSUR_H_
15#define _ASM_BIGSUR_H_
16
17#include <asm/irq.h>
18#include <asm/hd64465/hd64465.h>
19
20/* 7751 Internal IRQ's used by external CPLD controller */
21#define BIGSUR_IRQ_LOW 0
22#define BIGSUR_IRQ_NUM 14 /* External CPLD level 1 IRQs */
23#define BIGSUR_IRQ_HIGH (BIGSUR_IRQ_LOW + BIGSUR_IRQ_NUM)
24#define BIGSUR_2NDLVL_IRQ_LOW (HD64465_IRQ_BASE+HD64465_IRQ_NUM)
25#define BIGSUR_2NDLVL_IRQ_NUM 32 /* Level 2 IRQs = 4 regs * 8 bits */
26#define BIGSUR_2NDLVL_IRQ_HIGH (BIGSUR_2NDLVL_IRQ_LOW + \
27 BIGSUR_2NDLVL_IRQ_NUM)
28
29/* PCI interrupt base number (A_INTA-A_INTD) */
30#define BIGSUR_SH7751_PCI_IRQ_BASE (BIGSUR_2NDLVL_IRQ_LOW+10)
31
32/* CPLD registers and external chip addresses */
33#define BIGSUR_HD64464_ADDR 0xB2000000
34#define BIGSUR_DGDR 0xB1FFFE00
35#define BIGSUR_BIDR 0xB1FFFD00
36#define BIGSUR_CSLR 0xB1FFFC00
37#define BIGSUR_SW1R 0xB1FFFB00
38#define BIGSUR_DBGR 0xB1FFFA00
39#define BIGSUR_BDTR 0xB1FFF900
40#define BIGSUR_BDRR 0xB1FFF800
41#define BIGSUR_PPR1 0xB1FFF700
42#define BIGSUR_PPR2 0xB1FFF600
43#define BIGSUR_IDE2 0xB1FFF500
44#define BIGSUR_IDE3 0xB1FFF400
45#define BIGSUR_SPCR 0xB1FFF300
46#define BIGSUR_ETHR 0xB1FE0000
47#define BIGSUR_PPDR 0xB1FDFF00
48#define BIGSUR_ICTL 0xB1FDFE00
49#define BIGSUR_ICMD 0xB1FDFD00
50#define BIGSUR_DMA0 0xB1FDFC00
51#define BIGSUR_DMA1 0xB1FDFB00
52#define BIGSUR_IRQ0 0xB1FDFA00
53#define BIGSUR_IRQ1 0xB1FDF900
54#define BIGSUR_IRQ2 0xB1FDF800
55#define BIGSUR_IRQ3 0xB1FDF700
56#define BIGSUR_IMR0 0xB1FDF600
57#define BIGSUR_IMR1 0xB1FDF500
58#define BIGSUR_IMR2 0xB1FDF400
59#define BIGSUR_IMR3 0xB1FDF300
60#define BIGSUR_IRLMR0 0xB1FDF200
61#define BIGSUR_IRLMR1 0xB1FDF100
62#define BIGSUR_V320USC_ADDR 0xB1000000
63#define BIGSUR_HD64465_ADDR 0xB0000000
64#define BIGSUR_INTERNAL_BASE 0xB0000000
65
66/* SMC ethernet card parameters */
67#define BIGSUR_ETHER_IOPORT 0x220
68
69/* IDE register paramters */
70#define BIGSUR_IDECMD_IOPORT 0x1f0
71#define BIGSUR_IDECTL_IOPORT 0x1f8
72
73/* LED bit position in BIGSUR_CSLR */
74#define BIGSUR_LED (1<<4)
75
76/* PCI: default LOCAL memory window sizes (seen from PCI bus) */
77#define BIGSUR_LSR0_SIZE (64*(1<<20)) //64MB
78#define BIGSUR_LSR1_SIZE (64*(1<<20)) //64MB
79
80#endif /* _ASM_BIGSUR_H_ */