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Diffstat (limited to 'include/asm-s390/unistd.h')
-rw-r--r--include/asm-s390/unistd.h258
1 files changed, 129 insertions, 129 deletions
diff --git a/include/asm-s390/unistd.h b/include/asm-s390/unistd.h
index d49c54cb5505..0361ac5dcde3 100644
--- a/include/asm-s390/unistd.h
+++ b/include/asm-s390/unistd.h
@@ -355,145 +355,145 @@ do { \
355 355
356#define _svc_clobber "1", "cc", "memory" 356#define _svc_clobber "1", "cc", "memory"
357 357
358#define _syscall0(type,name) \ 358#define _syscall0(type,name) \
359type name(void) { \ 359type name(void) { \
360 register long __svcres asm("2"); \ 360 register long __svcres asm("2"); \
361 long __res; \ 361 long __res; \
362 __asm__ __volatile__ ( \ 362 asm volatile( \
363 " .if %1 < 256\n" \ 363 " .if %1 < 256\n" \
364 " svc %b1\n" \ 364 " svc %b1\n" \
365 " .else\n" \ 365 " .else\n" \
366 " la %%r1,%1\n" \ 366 " la %%r1,%1\n" \
367 " svc 0\n" \ 367 " svc 0\n" \
368 " .endif" \ 368 " .endif" \
369 : "=d" (__svcres) \ 369 : "=d" (__svcres) \
370 : "i" (__NR_##name) \ 370 : "i" (__NR_##name) \
371 : _svc_clobber ); \ 371 : _svc_clobber); \
372 __res = __svcres; \ 372 __res = __svcres; \
373 __syscall_return(type,__res); \ 373 __syscall_return(type,__res); \
374} 374}
375 375
376#define _syscall1(type,name,type1,arg1) \ 376#define _syscall1(type,name,type1,arg1) \
377type name(type1 arg1) { \ 377type name(type1 arg1) { \
378 register type1 __arg1 asm("2") = arg1; \ 378 register type1 __arg1 asm("2") = arg1; \
379 register long __svcres asm("2"); \ 379 register long __svcres asm("2"); \
380 long __res; \ 380 long __res; \
381 __asm__ __volatile__ ( \ 381 asm volatile( \
382 " .if %1 < 256\n" \ 382 " .if %1 < 256\n" \
383 " svc %b1\n" \ 383 " svc %b1\n" \
384 " .else\n" \ 384 " .else\n" \
385 " la %%r1,%1\n" \ 385 " la %%r1,%1\n" \
386 " svc 0\n" \ 386 " svc 0\n" \
387 " .endif" \ 387 " .endif" \
388 : "=d" (__svcres) \ 388 : "=d" (__svcres) \
389 : "i" (__NR_##name), \ 389 : "i" (__NR_##name), \
390 "0" (__arg1) \ 390 "0" (__arg1) \
391 : _svc_clobber ); \ 391 : _svc_clobber); \
392 __res = __svcres; \ 392 __res = __svcres; \
393 __syscall_return(type,__res); \ 393 __syscall_return(type,__res); \
394} 394}
395 395
396#define _syscall2(type,name,type1,arg1,type2,arg2) \ 396#define _syscall2(type,name,type1,arg1,type2,arg2) \
397type name(type1 arg1, type2 arg2) { \ 397type name(type1 arg1, type2 arg2) { \
398 register type1 __arg1 asm("2") = arg1; \ 398 register type1 __arg1 asm("2") = arg1; \
399 register type2 __arg2 asm("3") = arg2; \ 399 register type2 __arg2 asm("3") = arg2; \
400 register long __svcres asm("2"); \ 400 register long __svcres asm("2"); \
401 long __res; \ 401 long __res; \
402 __asm__ __volatile__ ( \ 402 asm volatile( \
403 " .if %1 < 256\n" \ 403 " .if %1 < 256\n" \
404 " svc %b1\n" \ 404 " svc %b1\n" \
405 " .else\n" \ 405 " .else\n" \
406 " la %%r1,%1\n" \ 406 " la %%r1,%1\n" \
407 " svc 0\n" \ 407 " svc 0\n" \
408 " .endif" \ 408 " .endif" \
409 : "=d" (__svcres) \ 409 : "=d" (__svcres) \
410 : "i" (__NR_##name), \ 410 : "i" (__NR_##name), \
411 "0" (__arg1), \ 411 "0" (__arg1), \
412 "d" (__arg2) \ 412 "d" (__arg2) \
413 : _svc_clobber ); \ 413 : _svc_clobber ); \
414 __res = __svcres; \ 414 __res = __svcres; \
415 __syscall_return(type,__res); \ 415 __syscall_return(type,__res); \
416} 416}
417 417
418#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3)\ 418#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
419type name(type1 arg1, type2 arg2, type3 arg3) { \ 419type name(type1 arg1, type2 arg2, type3 arg3) { \
420 register type1 __arg1 asm("2") = arg1; \ 420 register type1 __arg1 asm("2") = arg1; \
421 register type2 __arg2 asm("3") = arg2; \ 421 register type2 __arg2 asm("3") = arg2; \
422 register type3 __arg3 asm("4") = arg3; \ 422 register type3 __arg3 asm("4") = arg3; \
423 register long __svcres asm("2"); \ 423 register long __svcres asm("2"); \
424 long __res; \ 424 long __res; \
425 __asm__ __volatile__ ( \ 425 asm volatile( \
426 " .if %1 < 256\n" \ 426 " .if %1 < 256\n" \
427 " svc %b1\n" \ 427 " svc %b1\n" \
428 " .else\n" \ 428 " .else\n" \
429 " la %%r1,%1\n" \ 429 " la %%r1,%1\n" \
430 " svc 0\n" \ 430 " svc 0\n" \
431 " .endif" \ 431 " .endif" \
432 : "=d" (__svcres) \ 432 : "=d" (__svcres) \
433 : "i" (__NR_##name), \ 433 : "i" (__NR_##name), \
434 "0" (__arg1), \ 434 "0" (__arg1), \
435 "d" (__arg2), \ 435 "d" (__arg2), \
436 "d" (__arg3) \ 436 "d" (__arg3) \
437 : _svc_clobber ); \ 437 : _svc_clobber); \
438 __res = __svcres; \ 438 __res = __svcres; \
439 __syscall_return(type,__res); \ 439 __syscall_return(type,__res); \
440} 440}
441 441
442#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,\ 442#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3, \
443 type4,name4) \ 443 type4,name4) \
444type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \ 444type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \
445 register type1 __arg1 asm("2") = arg1; \ 445 register type1 __arg1 asm("2") = arg1; \
446 register type2 __arg2 asm("3") = arg2; \ 446 register type2 __arg2 asm("3") = arg2; \
447 register type3 __arg3 asm("4") = arg3; \ 447 register type3 __arg3 asm("4") = arg3; \
448 register type4 __arg4 asm("5") = arg4; \ 448 register type4 __arg4 asm("5") = arg4; \
449 register long __svcres asm("2"); \ 449 register long __svcres asm("2"); \
450 long __res; \ 450 long __res; \
451 __asm__ __volatile__ ( \ 451 asm volatile( \
452 " .if %1 < 256\n" \ 452 " .if %1 < 256\n" \
453 " svc %b1\n" \ 453 " svc %b1\n" \
454 " .else\n" \ 454 " .else\n" \
455 " la %%r1,%1\n" \ 455 " la %%r1,%1\n" \
456 " svc 0\n" \ 456 " svc 0\n" \
457 " .endif" \ 457 " .endif" \
458 : "=d" (__svcres) \ 458 : "=d" (__svcres) \
459 : "i" (__NR_##name), \ 459 : "i" (__NR_##name), \
460 "0" (__arg1), \ 460 "0" (__arg1), \
461 "d" (__arg2), \ 461 "d" (__arg2), \
462 "d" (__arg3), \ 462 "d" (__arg3), \
463 "d" (__arg4) \ 463 "d" (__arg4) \
464 : _svc_clobber ); \ 464 : _svc_clobber); \
465 __res = __svcres; \ 465 __res = __svcres; \
466 __syscall_return(type,__res); \ 466 __syscall_return(type,__res); \
467} 467}
468 468
469#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,\ 469#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3, \
470 type4,name4,type5,name5) \ 470 type4,name4,type5,name5) \
471type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \ 471type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, \
472 type5 arg5) { \ 472 type5 arg5) { \
473 register type1 __arg1 asm("2") = arg1; \ 473 register type1 __arg1 asm("2") = arg1; \
474 register type2 __arg2 asm("3") = arg2; \ 474 register type2 __arg2 asm("3") = arg2; \
475 register type3 __arg3 asm("4") = arg3; \ 475 register type3 __arg3 asm("4") = arg3; \
476 register type4 __arg4 asm("5") = arg4; \ 476 register type4 __arg4 asm("5") = arg4; \
477 register type5 __arg5 asm("6") = arg5; \ 477 register type5 __arg5 asm("6") = arg5; \
478 register long __svcres asm("2"); \ 478 register long __svcres asm("2"); \
479 long __res; \ 479 long __res; \
480 __asm__ __volatile__ ( \ 480 asm volatile( \
481 " .if %1 < 256\n" \ 481 " .if %1 < 256\n" \
482 " svc %b1\n" \ 482 " svc %b1\n" \
483 " .else\n" \ 483 " .else\n" \
484 " la %%r1,%1\n" \ 484 " la %%r1,%1\n" \
485 " svc 0\n" \ 485 " svc 0\n" \
486 " .endif" \ 486 " .endif" \
487 : "=d" (__svcres) \ 487 : "=d" (__svcres) \
488 : "i" (__NR_##name), \ 488 : "i" (__NR_##name), \
489 "0" (__arg1), \ 489 "0" (__arg1), \
490 "d" (__arg2), \ 490 "d" (__arg2), \
491 "d" (__arg3), \ 491 "d" (__arg3), \
492 "d" (__arg4), \ 492 "d" (__arg4), \
493 "d" (__arg5) \ 493 "d" (__arg5) \
494 : _svc_clobber ); \ 494 : _svc_clobber); \
495 __res = __svcres; \ 495 __res = __svcres; \
496 __syscall_return(type,__res); \ 496 __syscall_return(type,__res); \
497} 497}
498 498
499#define __ARCH_WANT_IPC_PARSE_VERSION 499#define __ARCH_WANT_IPC_PARSE_VERSION
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-01 21:43:10 -0500