diff options
Diffstat (limited to 'include/asm-s390/sigp.h')
| -rw-r--r-- | include/asm-s390/sigp.h | 65 |
1 files changed, 30 insertions, 35 deletions
diff --git a/include/asm-s390/sigp.h b/include/asm-s390/sigp.h index fc56458aff66..e16d56f8dfe1 100644 --- a/include/asm-s390/sigp.h +++ b/include/asm-s390/sigp.h | |||
| @@ -70,16 +70,16 @@ typedef enum | |||
| 70 | static inline sigp_ccode | 70 | static inline sigp_ccode |
| 71 | signal_processor(__u16 cpu_addr, sigp_order_code order_code) | 71 | signal_processor(__u16 cpu_addr, sigp_order_code order_code) |
| 72 | { | 72 | { |
| 73 | register unsigned long reg1 asm ("1") = 0; | ||
| 73 | sigp_ccode ccode; | 74 | sigp_ccode ccode; |
| 74 | 75 | ||
| 75 | __asm__ __volatile__( | 76 | asm volatile( |
| 76 | " sr 1,1\n" /* parameter=0 in gpr 1 */ | 77 | " sigp %1,%2,0(%3)\n" |
| 77 | " sigp 1,%1,0(%2)\n" | 78 | " ipm %0\n" |
| 78 | " ipm %0\n" | 79 | " srl %0,28\n" |
| 79 | " srl %0,28\n" | 80 | : "=d" (ccode) |
| 80 | : "=d" (ccode) | 81 | : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]), |
| 81 | : "d" (__cpu_logical_map[cpu_addr]), "a" (order_code) | 82 | "a" (order_code) : "cc" , "memory"); |
| 82 | : "cc" , "memory", "1" ); | ||
| 83 | return ccode; | 83 | return ccode; |
| 84 | } | 84 | } |
| 85 | 85 | ||
| @@ -87,20 +87,18 @@ signal_processor(__u16 cpu_addr, sigp_order_code order_code) | |||
| 87 | * Signal processor with parameter | 87 | * Signal processor with parameter |
| 88 | */ | 88 | */ |
| 89 | static inline sigp_ccode | 89 | static inline sigp_ccode |
| 90 | signal_processor_p(__u32 parameter, __u16 cpu_addr, | 90 | signal_processor_p(__u32 parameter, __u16 cpu_addr, sigp_order_code order_code) |
| 91 | sigp_order_code order_code) | ||
| 92 | { | 91 | { |
| 92 | register unsigned int reg1 asm ("1") = parameter; | ||
| 93 | sigp_ccode ccode; | 93 | sigp_ccode ccode; |
| 94 | 94 | ||
| 95 | __asm__ __volatile__( | 95 | asm volatile( |
| 96 | " lr 1,%1\n" /* parameter in gpr 1 */ | 96 | " sigp %1,%2,0(%3)\n" |
| 97 | " sigp 1,%2,0(%3)\n" | 97 | " ipm %0\n" |
| 98 | " ipm %0\n" | 98 | " srl %0,28\n" |
| 99 | " srl %0,28\n" | ||
| 100 | : "=d" (ccode) | 99 | : "=d" (ccode) |
| 101 | : "d" (parameter), "d" (__cpu_logical_map[cpu_addr]), | 100 | : "d" (reg1), "d" (__cpu_logical_map[cpu_addr]), |
| 102 | "a" (order_code) | 101 | "a" (order_code) : "cc" , "memory"); |
| 103 | : "cc" , "memory", "1" ); | ||
| 104 | return ccode; | 102 | return ccode; |
| 105 | } | 103 | } |
| 106 | 104 | ||
| @@ -108,24 +106,21 @@ signal_processor_p(__u32 parameter, __u16 cpu_addr, | |||
| 108 | * Signal processor with parameter and return status | 106 | * Signal processor with parameter and return status |
| 109 | */ | 107 | */ |
| 110 | static inline sigp_ccode | 108 | static inline sigp_ccode |
| 111 | signal_processor_ps(__u32 *statusptr, __u32 parameter, | 109 | signal_processor_ps(__u32 *statusptr, __u32 parameter, __u16 cpu_addr, |
| 112 | __u16 cpu_addr, sigp_order_code order_code) | 110 | sigp_order_code order_code) |
| 113 | { | 111 | { |
| 112 | register unsigned int reg1 asm ("1") = parameter; | ||
| 114 | sigp_ccode ccode; | 113 | sigp_ccode ccode; |
| 115 | 114 | ||
| 116 | __asm__ __volatile__( | 115 | asm volatile( |
| 117 | " sr 2,2\n" /* clear status */ | 116 | " sigp %1,%2,0(%3)\n" |
| 118 | " lr 3,%2\n" /* parameter in gpr 3 */ | 117 | " ipm %0\n" |
| 119 | " sigp 2,%3,0(%4)\n" | 118 | " srl %0,28\n" |
| 120 | " st 2,%1\n" | 119 | : "=d" (ccode), "+d" (reg1) |
| 121 | " ipm %0\n" | 120 | : "d" (__cpu_logical_map[cpu_addr]), "a" (order_code) |
| 122 | " srl %0,28\n" | 121 | : "cc" , "memory"); |
| 123 | : "=d" (ccode), "=m" (*statusptr) | 122 | *statusptr = reg1; |
| 124 | : "d" (parameter), "d" (__cpu_logical_map[cpu_addr]), | 123 | return ccode; |
| 125 | "a" (order_code) | ||
| 126 | : "cc" , "memory", "2" , "3" | ||
| 127 | ); | ||
| 128 | return ccode; | ||
| 129 | } | 124 | } |
| 130 | 125 | ||
| 131 | #endif /* __SIGP__ */ | 126 | #endif /* __SIGP__ */ |