aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-ppc
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/fsl_ocp.h54
-rw-r--r--include/asm-ppc/kexec.h38
-rw-r--r--include/asm-ppc/machdep.h31
-rw-r--r--include/asm-ppc/mmu.h2
-rw-r--r--include/asm-ppc/mmu_context.h2
-rw-r--r--include/asm-ppc/ocp.h4
-rw-r--r--include/asm-ppc/ppc_asm.h2
-rw-r--r--include/asm-ppc/reg.h1
-rw-r--r--include/asm-ppc/reg_booke.h18
9 files changed, 91 insertions, 61 deletions
diff --git a/include/asm-ppc/fsl_ocp.h b/include/asm-ppc/fsl_ocp.h
deleted file mode 100644
index 050fbba8d049..000000000000
--- a/include/asm-ppc/fsl_ocp.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * include/asm-ppc/fsl_ocp.h
3 *
4 * Definitions for the on-chip peripherals on Freescale PPC processors
5 *
6 * Maintainer: Kumar Gala (kumar.gala@freescale.com)
7 *
8 * Copyright 2004 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_FS_OCP_H__
18#define __ASM_FS_OCP_H__
19
20/* A table of information for supporting the Gianfar Ethernet Controller
21 * This helps identify which enet controller we are dealing with,
22 * and what type of enet controller it is
23 */
24struct ocp_gfar_data {
25 uint interruptTransmit;
26 uint interruptError;
27 uint interruptReceive;
28 uint interruptPHY;
29 uint flags;
30 uint phyid;
31 uint phyregidx;
32 unsigned char mac_addr[6];
33};
34
35/* Flags in the flags field */
36#define GFAR_HAS_COALESCE 0x20
37#define GFAR_HAS_RMON 0x10
38#define GFAR_HAS_MULTI_INTR 0x08
39#define GFAR_FIRM_SET_MACADDR 0x04
40#define GFAR_HAS_PHY_INTR 0x02 /* if not set use a timer */
41#define GFAR_HAS_GIGABIT 0x01
42
43/* Data structure for I2C support. Just contains a couple flags
44 * to distinguish various I2C implementations*/
45struct ocp_fs_i2c_data {
46 uint flags;
47};
48
49/* Flags for I2C */
50#define FS_I2C_SEPARATE_DFSRR 0x02
51#define FS_I2C_CLOCK_5200 0x01
52
53#endif /* __ASM_FS_OCP_H__ */
54#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/kexec.h b/include/asm-ppc/kexec.h
new file mode 100644
index 000000000000..73191310d8db
--- /dev/null
+++ b/include/asm-ppc/kexec.h
@@ -0,0 +1,38 @@
1#ifndef _PPC_KEXEC_H
2#define _PPC_KEXEC_H
3
4#ifdef CONFIG_KEXEC
5
6/*
7 * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
8 * I.e. Maximum page that is mapped directly into kernel memory,
9 * and kmap is not required.
10 *
11 * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
12 * calculation for the amount of memory directly mappable into the
13 * kernel memory space.
14 */
15
16/* Maximum physical address we can use pages from */
17#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
18/* Maximum address we can reach in physical address mode */
19#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
20/* Maximum address we can use for the control code buffer */
21#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
22
23#define KEXEC_CONTROL_CODE_SIZE 4096
24
25/* The native architecture */
26#define KEXEC_ARCH KEXEC_ARCH_PPC
27
28#ifndef __ASSEMBLY__
29
30struct kimage;
31
32extern void machine_kexec_simple(struct kimage *image);
33
34#endif /* __ASSEMBLY__ */
35
36#endif /* CONFIG_KEXEC */
37
38#endif /* _PPC_KEXEC_H */
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
index b78d40870c95..1d4ab70a56f3 100644
--- a/include/asm-ppc/machdep.h
+++ b/include/asm-ppc/machdep.h
@@ -4,6 +4,7 @@
4 4
5#include <linux/config.h> 5#include <linux/config.h>
6#include <linux/init.h> 6#include <linux/init.h>
7#include <linux/kexec.h>
7 8
8#include <asm/setup.h> 9#include <asm/setup.h>
9#include <asm/page.h> 10#include <asm/page.h>
@@ -114,6 +115,36 @@ struct machdep_calls {
114 /* functions for dealing with other cpus */ 115 /* functions for dealing with other cpus */
115 struct smp_ops_t *smp_ops; 116 struct smp_ops_t *smp_ops;
116#endif /* CONFIG_SMP */ 117#endif /* CONFIG_SMP */
118
119#ifdef CONFIG_KEXEC
120 /* Called to shutdown machine specific hardware not already controlled
121 * by other drivers.
122 * XXX Should we move this one out of kexec scope?
123 */
124 void (*machine_shutdown)(void);
125
126 /* Called to do the minimal shutdown needed to run a kexec'd kernel
127 * to run successfully.
128 * XXX Should we move this one out of kexec scope?
129 */
130 void (*machine_crash_shutdown)(void);
131
132 /* Called to do what every setup is needed on image and the
133 * reboot code buffer. Returns 0 on success.
134 * Provide your own (maybe dummy) implementation if your platform
135 * claims to support kexec.
136 */
137 int (*machine_kexec_prepare)(struct kimage *image);
138
139 /* Called to handle any machine specific cleanup on image */
140 void (*machine_kexec_cleanup)(struct kimage *image);
141
142 /* Called to perform the _real_ kexec.
143 * Do NOT allocate memory or fail here. We are past the point of
144 * no return.
145 */
146 void (*machine_kexec)(struct kimage *image);
147#endif /* CONFIG_KEXEC */
117}; 148};
118 149
119extern struct machdep_calls ppc_md; 150extern struct machdep_calls ppc_md;
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index d465aee1c82e..9205db404c7a 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -405,7 +405,7 @@ typedef struct _P601_BAT {
405 405
406#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) 406#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
407#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) 407#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
408#define MAS0_NV 0x00000FFF 408#define MAS0_NV(x) ((x) & 0x00000FFF)
409 409
410#define MAS1_VALID 0x80000000 410#define MAS1_VALID 0x80000000
411#define MAS1_IPROT 0x40000000 411#define MAS1_IPROT 0x40000000
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index 9222fa6ca172..ccabbce39d85 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -63,7 +63,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
63#define LAST_CONTEXT 255 63#define LAST_CONTEXT 255
64#define FIRST_CONTEXT 1 64#define FIRST_CONTEXT 1
65 65
66#elif defined(CONFIG_E500) 66#elif defined(CONFIG_E200) || defined(CONFIG_E500)
67#define NO_CONTEXT 256 67#define NO_CONTEXT 256
68#define LAST_CONTEXT 255 68#define LAST_CONTEXT 255
69#define FIRST_CONTEXT 1 69#define FIRST_CONTEXT 1
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
index c726f1845190..983116f59d90 100644
--- a/include/asm-ppc/ocp.h
+++ b/include/asm-ppc/ocp.h
@@ -202,10 +202,6 @@ static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
202#include <asm/ibm_ocp.h> 202#include <asm/ibm_ocp.h>
203#endif 203#endif
204 204
205#ifdef CONFIG_FSL_OCP
206#include <asm/fsl_ocp.h>
207#endif
208
209#endif /* CONFIG_PPC_OCP */ 205#endif /* CONFIG_PPC_OCP */
210#endif /* __OCP_H__ */ 206#endif /* __OCP_H__ */
211#endif /* __KERNEL__ */ 207#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
index 13fa8e7483c1..f76221def484 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-ppc/ppc_asm.h
@@ -174,6 +174,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
174#define CLR_TOP32(r) 174#define CLR_TOP32(r)
175#endif /* CONFIG_PPC64BRIDGE */ 175#endif /* CONFIG_PPC64BRIDGE */
176 176
177#define RFCI .long 0x4c000066 /* rfci instruction */
178#define RFDI .long 0x4c00004e /* rfdi instruction */
177#define RFMCI .long 0x4c00004c /* rfmci instruction */ 179#define RFMCI .long 0x4c00004c /* rfmci instruction */
178 180
179#ifdef CONFIG_IBM405_ERR77 181#ifdef CONFIG_IBM405_ERR77
diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
index c418aab7cd34..88b4222154d4 100644
--- a/include/asm-ppc/reg.h
+++ b/include/asm-ppc/reg.h
@@ -160,6 +160,7 @@
160#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 160#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
161#define HID0_DCI (1<<10) /* Data Cache Invalidate */ 161#define HID0_DCI (1<<10) /* Data Cache Invalidate */
162#define HID0_SPD (1<<9) /* Speculative disable */ 162#define HID0_SPD (1<<9) /* Speculative disable */
163#define HID0_DAPUEN (1<<8) /* Debug APU enable */
163#define HID0_SGE (1<<7) /* Store Gathering Enable */ 164#define HID0_SGE (1<<7) /* Store Gathering Enable */
164#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 165#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
165#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ 166#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 45c5e6f2b7ab..00ad9c754c78 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -165,6 +165,8 @@ do { \
165#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 165#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
166#define SPRN_MCSR 0x23C /* Machine Check Status Register */ 166#define SPRN_MCSR 0x23C /* Machine Check Status Register */
167#define SPRN_MCAR 0x23D /* Machine Check Address Register */ 167#define SPRN_MCAR 0x23D /* Machine Check Address Register */
168#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
169#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
168#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 170#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
169#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 171#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
170#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 172#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
@@ -264,6 +266,17 @@ do { \
264#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ 266#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
265#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ 267#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
266#endif 268#endif
269#ifdef CONFIG_E200
270#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
271#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
272#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
273#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
274 fetch for an exception handler */
275#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
276#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
277#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
278 store or cache line push */
279#endif
267 280
268/* Bit definitions for the DBSR. */ 281/* Bit definitions for the DBSR. */
269/* 282/*
@@ -311,6 +324,7 @@ do { \
311#define ESR_ST 0x00800000 /* Store Operation */ 324#define ESR_ST 0x00800000 /* Store Operation */
312#define ESR_DLK 0x00200000 /* Data Cache Locking */ 325#define ESR_DLK 0x00200000 /* Data Cache Locking */
313#define ESR_ILK 0x00100000 /* Instr. Cache Locking */ 326#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
327#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
314#define ESR_BO 0x00020000 /* Byte Ordering */ 328#define ESR_BO 0x00020000 /* Byte Ordering */
315 329
316/* Bit definitions related to the DBCR0. */ 330/* Bit definitions related to the DBCR0. */
@@ -387,10 +401,12 @@ do { \
387#define ICCR_CACHE 1 /* Cacheable */ 401#define ICCR_CACHE 1 /* Cacheable */
388 402
389/* Bit definitions for L1CSR0. */ 403/* Bit definitions for L1CSR0. */
404#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
390#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 405#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
406#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
391#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 407#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
392 408
393/* Bit definitions for L1CSR0. */ 409/* Bit definitions for L1CSR1. */
394#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ 410#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
395#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ 411#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
396#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ 412#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-10 19:06:13 -0500