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-rw-r--r--include/asm-ppc/a.out.h26
-rw-r--r--include/asm-ppc/atomic.h214
-rw-r--r--include/asm-ppc/auxvec.h14
-rw-r--r--include/asm-ppc/backlight.h30
-rw-r--r--include/asm-ppc/bug.h58
-rw-r--r--include/asm-ppc/byteorder.h76
-rw-r--r--include/asm-ppc/cache.h13
-rw-r--r--include/asm-ppc/checksum.h107
-rw-r--r--include/asm-ppc/cpm2.h3
-rw-r--r--include/asm-ppc/cputable.h129
-rw-r--r--include/asm-ppc/dbdma.h102
-rw-r--r--include/asm-ppc/dma.h371
-rw-r--r--include/asm-ppc/elf.h151
-rw-r--r--include/asm-ppc/hardirq.h31
-rw-r--r--include/asm-ppc/heathrow.h62
-rw-r--r--include/asm-ppc/hw_irq.h74
-rw-r--r--include/asm-ppc/i8259.h11
-rw-r--r--include/asm-ppc/io.h11
-rw-r--r--include/asm-ppc/irq.h418
-rw-r--r--include/asm-ppc/keylargo.h248
-rw-r--r--include/asm-ppc/kmap_types.h25
-rw-r--r--include/asm-ppc/machdep.h4
-rw-r--r--include/asm-ppc/macio.h140
-rw-r--r--include/asm-ppc/mediabay.h31
-rw-r--r--include/asm-ppc/mmu_context.h6
-rw-r--r--include/asm-ppc/mpc8260.h4
-rw-r--r--include/asm-ppc/mpc85xx.h3
-rw-r--r--include/asm-ppc/mpc8xx.h4
-rw-r--r--include/asm-ppc/of_device.h65
-rw-r--r--include/asm-ppc/ohare.h48
-rw-r--r--include/asm-ppc/open_pic.h3
-rw-r--r--include/asm-ppc/page.h18
-rw-r--r--include/asm-ppc/parport.h18
-rw-r--r--include/asm-ppc/pci-bridge.h5
-rw-r--r--include/asm-ppc/pci.h6
-rw-r--r--include/asm-ppc/perfmon.h22
-rw-r--r--include/asm-ppc/pgtable.h2
-rw-r--r--include/asm-ppc/pmac_feature.h380
-rw-r--r--include/asm-ppc/pmac_low_i2c.h43
-rw-r--r--include/asm-ppc/posix_types.h111
-rw-r--r--include/asm-ppc/ppc_asm.h350
-rw-r--r--include/asm-ppc/processor.h201
-rw-r--r--include/asm-ppc/ptrace.h2
-rw-r--r--include/asm-ppc/reg.h440
-rw-r--r--include/asm-ppc/rwsem.h177
-rw-r--r--include/asm-ppc/scatterlist.h25
-rw-r--r--include/asm-ppc/seccomp.h10
-rw-r--r--include/asm-ppc/sections.h33
-rw-r--r--include/asm-ppc/semaphore.h111
-rw-r--r--include/asm-ppc/smp.h28
-rw-r--r--include/asm-ppc/spinlock.h8
-rw-r--r--include/asm-ppc/spinlock_types.h20
-rw-r--r--include/asm-ppc/statfs.h8
-rw-r--r--include/asm-ppc/system.h28
-rw-r--r--include/asm-ppc/thread_info.h107
-rw-r--r--include/asm-ppc/types.h69
-rw-r--r--include/asm-ppc/uninorth.h229
-rw-r--r--include/asm-ppc/unistd.h493
-rw-r--r--include/asm-ppc/vga.h46
-rw-r--r--include/asm-ppc/xmon.h17
60 files changed, 89 insertions, 5400 deletions
diff --git a/include/asm-ppc/a.out.h b/include/asm-ppc/a.out.h
deleted file mode 100644
index 8979a94c4a81..000000000000
--- a/include/asm-ppc/a.out.h
+++ /dev/null
@@ -1,26 +0,0 @@
1#ifndef __PPC_A_OUT_H__
2#define __PPC_A_OUT_H__
3
4/* grabbed from the intel stuff */
5#define STACK_TOP TASK_SIZE
6
7
8struct exec
9{
10 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
11 unsigned a_text; /* length of text, in bytes */
12 unsigned a_data; /* length of data, in bytes */
13 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
14 unsigned a_syms; /* length of symbol table data in file, in bytes */
15 unsigned a_entry; /* start address */
16 unsigned a_trsize; /* length of relocation info for text, in bytes */
17 unsigned a_drsize; /* length of relocation info for data, in bytes */
18};
19
20
21#define N_TRSIZE(a) ((a).a_trsize)
22#define N_DRSIZE(a) ((a).a_drsize)
23#define N_SYMSIZE(a) ((a).a_syms)
24
25
26#endif
diff --git a/include/asm-ppc/atomic.h b/include/asm-ppc/atomic.h
deleted file mode 100644
index eeafd505836e..000000000000
--- a/include/asm-ppc/atomic.h
+++ /dev/null
@@ -1,214 +0,0 @@
1/*
2 * PowerPC atomic operations
3 */
4
5#ifndef _ASM_PPC_ATOMIC_H_
6#define _ASM_PPC_ATOMIC_H_
7
8typedef struct { volatile int counter; } atomic_t;
9
10#ifdef __KERNEL__
11
12#define ATOMIC_INIT(i) { (i) }
13
14#define atomic_read(v) ((v)->counter)
15#define atomic_set(v,i) (((v)->counter) = (i))
16
17extern void atomic_clear_mask(unsigned long mask, unsigned long *addr);
18
19#ifdef CONFIG_SMP
20#define SMP_SYNC "sync"
21#define SMP_ISYNC "\n\tisync"
22#else
23#define SMP_SYNC ""
24#define SMP_ISYNC
25#endif
26
27/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
28 * The old ATOMIC_SYNC_FIX covered some but not all of this.
29 */
30#ifdef CONFIG_IBM405_ERR77
31#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";"
32#else
33#define PPC405_ERR77(ra,rb)
34#endif
35
36static __inline__ void atomic_add(int a, atomic_t *v)
37{
38 int t;
39
40 __asm__ __volatile__(
41"1: lwarx %0,0,%3 # atomic_add\n\
42 add %0,%2,%0\n"
43 PPC405_ERR77(0,%3)
44" stwcx. %0,0,%3 \n\
45 bne- 1b"
46 : "=&r" (t), "=m" (v->counter)
47 : "r" (a), "r" (&v->counter), "m" (v->counter)
48 : "cc");
49}
50
51static __inline__ int atomic_add_return(int a, atomic_t *v)
52{
53 int t;
54
55 __asm__ __volatile__(
56"1: lwarx %0,0,%2 # atomic_add_return\n\
57 add %0,%1,%0\n"
58 PPC405_ERR77(0,%2)
59" stwcx. %0,0,%2 \n\
60 bne- 1b"
61 SMP_ISYNC
62 : "=&r" (t)
63 : "r" (a), "r" (&v->counter)
64 : "cc", "memory");
65
66 return t;
67}
68
69#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
70
71static __inline__ void atomic_sub(int a, atomic_t *v)
72{
73 int t;
74
75 __asm__ __volatile__(
76"1: lwarx %0,0,%3 # atomic_sub\n\
77 subf %0,%2,%0\n"
78 PPC405_ERR77(0,%3)
79" stwcx. %0,0,%3 \n\
80 bne- 1b"
81 : "=&r" (t), "=m" (v->counter)
82 : "r" (a), "r" (&v->counter), "m" (v->counter)
83 : "cc");
84}
85
86static __inline__ int atomic_sub_return(int a, atomic_t *v)
87{
88 int t;
89
90 __asm__ __volatile__(
91"1: lwarx %0,0,%2 # atomic_sub_return\n\
92 subf %0,%1,%0\n"
93 PPC405_ERR77(0,%2)
94" stwcx. %0,0,%2 \n\
95 bne- 1b"
96 SMP_ISYNC
97 : "=&r" (t)
98 : "r" (a), "r" (&v->counter)
99 : "cc", "memory");
100
101 return t;
102}
103
104static __inline__ void atomic_inc(atomic_t *v)
105{
106 int t;
107
108 __asm__ __volatile__(
109"1: lwarx %0,0,%2 # atomic_inc\n\
110 addic %0,%0,1\n"
111 PPC405_ERR77(0,%2)
112" stwcx. %0,0,%2 \n\
113 bne- 1b"
114 : "=&r" (t), "=m" (v->counter)
115 : "r" (&v->counter), "m" (v->counter)
116 : "cc");
117}
118
119static __inline__ int atomic_inc_return(atomic_t *v)
120{
121 int t;
122
123 __asm__ __volatile__(
124"1: lwarx %0,0,%1 # atomic_inc_return\n\
125 addic %0,%0,1\n"
126 PPC405_ERR77(0,%1)
127" stwcx. %0,0,%1 \n\
128 bne- 1b"
129 SMP_ISYNC
130 : "=&r" (t)
131 : "r" (&v->counter)
132 : "cc", "memory");
133
134 return t;
135}
136
137/*
138 * atomic_inc_and_test - increment and test
139 * @v: pointer of type atomic_t
140 *
141 * Atomically increments @v by 1
142 * and returns true if the result is zero, or false for all
143 * other cases.
144 */
145#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
146
147static __inline__ void atomic_dec(atomic_t *v)
148{
149 int t;
150
151 __asm__ __volatile__(
152"1: lwarx %0,0,%2 # atomic_dec\n\
153 addic %0,%0,-1\n"
154 PPC405_ERR77(0,%2)\
155" stwcx. %0,0,%2\n\
156 bne- 1b"
157 : "=&r" (t), "=m" (v->counter)
158 : "r" (&v->counter), "m" (v->counter)
159 : "cc");
160}
161
162static __inline__ int atomic_dec_return(atomic_t *v)
163{
164 int t;
165
166 __asm__ __volatile__(
167"1: lwarx %0,0,%1 # atomic_dec_return\n\
168 addic %0,%0,-1\n"
169 PPC405_ERR77(0,%1)
170" stwcx. %0,0,%1\n\
171 bne- 1b"
172 SMP_ISYNC
173 : "=&r" (t)
174 : "r" (&v->counter)
175 : "cc", "memory");
176
177 return t;
178}
179
180#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
181#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
182
183/*
184 * Atomically test *v and decrement if it is greater than 0.
185 * The function returns the old value of *v minus 1.
186 */
187static __inline__ int atomic_dec_if_positive(atomic_t *v)
188{
189 int t;
190
191 __asm__ __volatile__(
192"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
193 addic. %0,%0,-1\n\
194 blt- 2f\n"
195 PPC405_ERR77(0,%1)
196" stwcx. %0,0,%1\n\
197 bne- 1b"
198 SMP_ISYNC
199 "\n\
2002:" : "=&r" (t)
201 : "r" (&v->counter)
202 : "cc", "memory");
203
204 return t;
205}
206
207#define __MB __asm__ __volatile__ (SMP_SYNC : : : "memory")
208#define smp_mb__before_atomic_dec() __MB
209#define smp_mb__after_atomic_dec() __MB
210#define smp_mb__before_atomic_inc() __MB
211#define smp_mb__after_atomic_inc() __MB
212
213#endif /* __KERNEL__ */
214#endif /* _ASM_PPC_ATOMIC_H_ */
diff --git a/include/asm-ppc/auxvec.h b/include/asm-ppc/auxvec.h
deleted file mode 100644
index 172358df29c8..000000000000
--- a/include/asm-ppc/auxvec.h
+++ /dev/null
@@ -1,14 +0,0 @@
1#ifndef __PPC_AUXVEC_H
2#define __PPC_AUXVEC_H
3
4/*
5 * We need to put in some extra aux table entries to tell glibc what
6 * the cache block size is, so it can use the dcbz instruction safely.
7 */
8#define AT_DCACHEBSIZE 19
9#define AT_ICACHEBSIZE 20
10#define AT_UCACHEBSIZE 21
11/* A special ignored type value for PPC, for glibc compatibility. */
12#define AT_IGNOREPPC 22
13
14#endif
diff --git a/include/asm-ppc/backlight.h b/include/asm-ppc/backlight.h
deleted file mode 100644
index 3a1c3dede2a0..000000000000
--- a/include/asm-ppc/backlight.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Routines for handling backlight control on PowerBooks
3 *
4 * For now, implementation resides in arch/ppc/kernel/pmac_support.c
5 *
6 */
7#ifdef __KERNEL__
8#ifndef __ASM_PPC_BACKLIGHT_H
9#define __ASM_PPC_BACKLIGHT_H
10
11/* Abstract values */
12#define BACKLIGHT_OFF 0
13#define BACKLIGHT_MIN 1
14#define BACKLIGHT_MAX 0xf
15
16struct backlight_controller {
17 int (*set_enable)(int enable, int level, void *data);
18 int (*set_level)(int level, void *data);
19};
20
21extern void register_backlight_controller(struct backlight_controller *ctrler, void *data, char *type);
22extern void unregister_backlight_controller(struct backlight_controller *ctrler, void *data);
23
24extern int set_backlight_enable(int enable);
25extern int get_backlight_enable(void);
26extern int set_backlight_level(int level);
27extern int get_backlight_level(void);
28
29#endif
30#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/bug.h b/include/asm-ppc/bug.h
deleted file mode 100644
index 8b34fd682b0d..000000000000
--- a/include/asm-ppc/bug.h
+++ /dev/null
@@ -1,58 +0,0 @@
1#ifndef _PPC_BUG_H
2#define _PPC_BUG_H
3
4struct bug_entry {
5 unsigned long bug_addr;
6 int line;
7 const char *file;
8 const char *function;
9};
10
11/*
12 * If this bit is set in the line number it means that the trap
13 * is for WARN_ON rather than BUG or BUG_ON.
14 */
15#define BUG_WARNING_TRAP 0x1000000
16
17#ifdef CONFIG_BUG
18#define BUG() do { \
19 __asm__ __volatile__( \
20 "1: twi 31,0,0\n" \
21 ".section __bug_table,\"a\"\n\t" \
22 " .long 1b,%0,%1,%2\n" \
23 ".previous" \
24 : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
25} while (0)
26
27#define BUG_ON(x) do { \
28 if (!__builtin_constant_p(x) || (x)) { \
29 __asm__ __volatile__( \
30 "1: twnei %0,0\n" \
31 ".section __bug_table,\"a\"\n\t" \
32 " .long 1b,%1,%2,%3\n" \
33 ".previous" \
34 : : "r" (x), "i" (__LINE__), "i" (__FILE__), \
35 "i" (__FUNCTION__)); \
36 } \
37} while (0)
38
39#define WARN_ON(x) do { \
40 if (!__builtin_constant_p(x) || (x)) { \
41 __asm__ __volatile__( \
42 "1: twnei %0,0\n" \
43 ".section __bug_table,\"a\"\n\t" \
44 " .long 1b,%1,%2,%3\n" \
45 ".previous" \
46 : : "r" (x), "i" (__LINE__ + BUG_WARNING_TRAP), \
47 "i" (__FILE__), "i" (__FUNCTION__)); \
48 } \
49} while (0)
50
51#define HAVE_ARCH_BUG
52#define HAVE_ARCH_BUG_ON
53#define HAVE_ARCH_WARN_ON
54#endif
55
56#include <asm-generic/bug.h>
57
58#endif
diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h
deleted file mode 100644
index c63c81ec7968..000000000000
--- a/include/asm-ppc/byteorder.h
+++ /dev/null
@@ -1,76 +0,0 @@
1#ifndef _PPC_BYTEORDER_H
2#define _PPC_BYTEORDER_H
3
4#include <asm/types.h>
5#include <linux/compiler.h>
6
7#ifdef __GNUC__
8#ifdef __KERNEL__
9
10extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
11{
12 unsigned val;
13
14 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
15 return val;
16}
17
18extern __inline__ void st_le16(volatile unsigned short *addr, const unsigned val)
19{
20 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
21}
22
23extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
24{
25 unsigned val;
26
27 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
28 return val;
29}
30
31extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
32{
33 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
34}
35
36static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
37{
38 __u16 result;
39
40 __asm__("rlwimi %0,%2,8,16,23" : "=&r" (result) : "0" (value >> 8), "r" (value));
41 return result;
42}
43
44static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
45{
46 __u32 result;
47
48 __asm__("rlwimi %0,%2,24,16,23" : "=&r" (result) : "0" (value>>24), "r" (value));
49 __asm__("rlwimi %0,%2,8,8,15" : "=&r" (result) : "0" (result), "r" (value));
50 __asm__("rlwimi %0,%2,24,0,7" : "=&r" (result) : "0" (result), "r" (value));
51
52 return result;
53}
54#define __arch__swab32(x) ___arch__swab32(x)
55#define __arch__swab16(x) ___arch__swab16(x)
56
57/* The same, but returns converted value from the location pointer by addr. */
58#define __arch__swab16p(addr) ld_le16(addr)
59#define __arch__swab32p(addr) ld_le32(addr)
60
61/* The same, but do the conversion in situ, ie. put the value back to addr. */
62#define __arch__swab16s(addr) st_le16(addr,*addr)
63#define __arch__swab32s(addr) st_le32(addr,*addr)
64
65#endif /* __KERNEL__ */
66
67#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
68# define __BYTEORDER_HAS_U64__
69# define __SWAB_64_THRU_32__
70#endif
71
72#endif /* __GNUC__ */
73
74#include <linux/byteorder/big_endian.h>
75
76#endif /* _PPC_BYTEORDER_H */
diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h
index 38f2f1be4a87..7a157d0f4b5f 100644
--- a/include/asm-ppc/cache.h
+++ b/include/asm-ppc/cache.h
@@ -9,21 +9,18 @@
9 9
10/* bytes per L1 cache line */ 10/* bytes per L1 cache line */
11#if defined(CONFIG_8xx) || defined(CONFIG_403GCX) 11#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
12#define L1_CACHE_LINE_SIZE 16 12#define L1_CACHE_SHIFT 4
13#define LG_L1_CACHE_LINE_SIZE 4
14#define MAX_COPY_PREFETCH 1 13#define MAX_COPY_PREFETCH 1
15#elif defined(CONFIG_PPC64BRIDGE) 14#elif defined(CONFIG_PPC64BRIDGE)
16#define L1_CACHE_LINE_SIZE 128 15#define L1_CACHE_SHIFT 7
17#define LG_L1_CACHE_LINE_SIZE 7
18#define MAX_COPY_PREFETCH 1 16#define MAX_COPY_PREFETCH 1
19#else 17#else
20#define L1_CACHE_LINE_SIZE 32 18#define L1_CACHE_SHIFT 5
21#define LG_L1_CACHE_LINE_SIZE 5
22#define MAX_COPY_PREFETCH 4 19#define MAX_COPY_PREFETCH 4
23#endif 20#endif
24 21
25#define L1_CACHE_BYTES L1_CACHE_LINE_SIZE 22#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
26#define L1_CACHE_SHIFT LG_L1_CACHE_LINE_SIZE 23
27#define SMP_CACHE_BYTES L1_CACHE_BYTES 24#define SMP_CACHE_BYTES L1_CACHE_BYTES
28#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */ 25#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
29 26
diff --git a/include/asm-ppc/checksum.h b/include/asm-ppc/checksum.h
deleted file mode 100644
index cf953a92c7ab..000000000000
--- a/include/asm-ppc/checksum.h
+++ /dev/null
@@ -1,107 +0,0 @@
1#ifdef __KERNEL__
2#ifndef _PPC_CHECKSUM_H
3#define _PPC_CHECKSUM_H
4
5
6/*
7 * computes the checksum of a memory block at buff, length len,
8 * and adds in "sum" (32-bit)
9 *
10 * returns a 32-bit number suitable for feeding into itself
11 * or csum_tcpudp_magic
12 *
13 * this function must be called with even lengths, except
14 * for the last fragment, which may be odd
15 *
16 * it's best to have buff aligned on a 32-bit boundary
17 */
18extern unsigned int csum_partial(const unsigned char * buff, int len,
19 unsigned int sum);
20
21/*
22 * Computes the checksum of a memory block at src, length len,
23 * and adds in "sum" (32-bit), while copying the block to dst.
24 * If an access exception occurs on src or dst, it stores -EFAULT
25 * to *src_err or *dst_err respectively (if that pointer is not
26 * NULL), and, for an error on src, zeroes the rest of dst.
27 *
28 * Like csum_partial, this must be called with even lengths,
29 * except for the last fragment.
30 */
31extern unsigned int csum_partial_copy_generic(const char *src, char *dst,
32 int len, unsigned int sum,
33 int *src_err, int *dst_err);
34
35#define csum_partial_copy_from_user(src, dst, len, sum, errp) \
36 csum_partial_copy_generic((__force void *)(src), (dst), (len), (sum), (errp), NULL)
37
38/* FIXME: this needs to be written to really do no check -- Cort */
39#define csum_partial_copy_nocheck(src, dst, len, sum) \
40 csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
41
42/*
43 * turns a 32-bit partial checksum (e.g. from csum_partial) into a
44 * 1's complement 16-bit checksum.
45 */
46static inline unsigned int csum_fold(unsigned int sum)
47{
48 unsigned int tmp;
49
50 /* swap the two 16-bit halves of sum */
51 __asm__("rlwinm %0,%1,16,0,31" : "=r" (tmp) : "r" (sum));
52 /* if there is a carry from adding the two 16-bit halves,
53 it will carry from the lower half into the upper half,
54 giving us the correct sum in the upper half. */
55 sum = ~(sum + tmp) >> 16;
56 return sum;
57}
58
59/*
60 * this routine is used for miscellaneous IP-like checksums, mainly
61 * in icmp.c
62 */
63static inline unsigned short ip_compute_csum(unsigned char * buff, int len)
64{
65 return csum_fold(csum_partial(buff, len, 0));
66}
67
68/*
69 * FIXME: I swiped this one from the sparc and made minor modifications.
70 * It may not be correct. -- Cort
71 */
72static inline unsigned long csum_tcpudp_nofold(unsigned long saddr,
73 unsigned long daddr,
74 unsigned short len,
75 unsigned short proto,
76 unsigned int sum)
77{
78 __asm__("\n\
79 addc %0,%0,%1 \n\
80 adde %0,%0,%2 \n\
81 adde %0,%0,%3 \n\
82 addze %0,%0 \n\
83 "
84 : "=r" (sum)
85 : "r" (daddr), "r"(saddr), "r"((proto<<16)+len), "0"(sum));
86 return sum;
87}
88
89/*
90 * This is a version of ip_compute_csum() optimized for IP headers,
91 * which always checksum on 4 octet boundaries. ihl is the number
92 * of 32-bit words and is always >= 5.
93 */
94extern unsigned short ip_fast_csum(unsigned char * iph, unsigned int ihl);
95
96/*
97 * computes the checksum of the TCP/UDP pseudo-header
98 * returns a 16-bit checksum, already complemented
99 */
100extern unsigned short csum_tcpudp_magic(unsigned long saddr,
101 unsigned long daddr,
102 unsigned short len,
103 unsigned short proto,
104 unsigned int sum);
105
106#endif
107#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index 9483d4bfacf7..43d2ebbc7748 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -1087,6 +1087,9 @@ typedef struct im_idma {
1087#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */ 1087#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1088#define SCCR_PCIDF_SHIFT 3 1088#define SCCR_PCIDF_SHIFT 3
1089 1089
1090#ifndef CPM_IMMR_OFFSET
1091#define CPM_IMMR_OFFSET 0x101a8
1092#endif
1090 1093
1091#endif /* __CPM2__ */ 1094#endif /* __CPM2__ */
1092#endif /* __KERNEL__ */ 1095#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/cputable.h b/include/asm-ppc/cputable.h
deleted file mode 100644
index e17c492c870b..000000000000
--- a/include/asm-ppc/cputable.h
+++ /dev/null
@@ -1,129 +0,0 @@
1/*
2 * include/asm-ppc/cputable.h
3 *
4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef __ASM_PPC_CPUTABLE_H
13#define __ASM_PPC_CPUTABLE_H
14
15/* Exposed to userland CPU features */
16#define PPC_FEATURE_32 0x80000000
17#define PPC_FEATURE_64 0x40000000
18#define PPC_FEATURE_601_INSTR 0x20000000
19#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
20#define PPC_FEATURE_HAS_FPU 0x08000000
21#define PPC_FEATURE_HAS_MMU 0x04000000
22#define PPC_FEATURE_HAS_4xxMAC 0x02000000
23#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
24#define PPC_FEATURE_HAS_SPE 0x00800000
25#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
26#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
27#define PPC_FEATURE_NO_TB 0x00100000
28
29#ifdef __KERNEL__
30
31#ifndef __ASSEMBLY__
32
33/* This structure can grow, it's real size is used by head.S code
34 * via the mkdefs mecanism.
35 */
36struct cpu_spec;
37
38typedef void (*cpu_setup_t)(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
39
40struct cpu_spec {
41 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
42 unsigned int pvr_mask;
43 unsigned int pvr_value;
44
45 char *cpu_name;
46 unsigned int cpu_features; /* Kernel features */
47 unsigned int cpu_user_features; /* Userland features */
48
49 /* cache line sizes */
50 unsigned int icache_bsize;
51 unsigned int dcache_bsize;
52
53 /* number of performance monitor counters */
54 unsigned int num_pmcs;
55
56 /* this is called to initialize various CPU bits like L1 cache,
57 * BHT, SPD, etc... from head.S before branching to identify_machine
58 */
59 cpu_setup_t cpu_setup;
60};
61
62extern struct cpu_spec cpu_specs[];
63extern struct cpu_spec *cur_cpu_spec[];
64
65static inline unsigned int cpu_has_feature(unsigned int feature)
66{
67 return cur_cpu_spec[0]->cpu_features & feature;
68}
69
70#endif /* __ASSEMBLY__ */
71
72/* CPU kernel features */
73#define CPU_FTR_SPLIT_ID_CACHE 0x00000001
74#define CPU_FTR_L2CR 0x00000002
75#define CPU_FTR_SPEC7450 0x00000004
76#define CPU_FTR_ALTIVEC 0x00000008
77#define CPU_FTR_TAU 0x00000010
78#define CPU_FTR_CAN_DOZE 0x00000020
79#define CPU_FTR_USE_TB 0x00000040
80#define CPU_FTR_604_PERF_MON 0x00000080
81#define CPU_FTR_601 0x00000100
82#define CPU_FTR_HPTE_TABLE 0x00000200
83#define CPU_FTR_CAN_NAP 0x00000400
84#define CPU_FTR_L3CR 0x00000800
85#define CPU_FTR_L3_DISABLE_NAP 0x00001000
86#define CPU_FTR_NAP_DISABLE_L2_PR 0x00002000
87#define CPU_FTR_DUAL_PLL_750FX 0x00004000
88#define CPU_FTR_NO_DPM 0x00008000
89#define CPU_FTR_HAS_HIGH_BATS 0x00010000
90#define CPU_FTR_NEED_COHERENT 0x00020000
91#define CPU_FTR_NO_BTIC 0x00040000
92#define CPU_FTR_BIG_PHYS 0x00080000
93
94#ifdef __ASSEMBLY__
95
96#define BEGIN_FTR_SECTION 98:
97
98#define END_FTR_SECTION(msk, val) \
9999: \
100 .section __ftr_fixup,"a"; \
101 .align 2; \
102 .long msk; \
103 .long val; \
104 .long 98b; \
105 .long 99b; \
106 .previous
107
108#else
109
110#define BEGIN_FTR_SECTION "98:\n"
111#define END_FTR_SECTION(msk, val) \
112"99:\n" \
113" .section __ftr_fixup,\"a\";\n" \
114" .align 2;\n" \
115" .long "#msk";\n" \
116" .long "#val";\n" \
117" .long 98b;\n" \
118" .long 99b;\n" \
119" .previous\n"
120
121
122#endif /* __ASSEMBLY__ */
123
124#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
125#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
126
127#endif /* __ASM_PPC_CPUTABLE_H */
128#endif /* __KERNEL__ */
129
diff --git a/include/asm-ppc/dbdma.h b/include/asm-ppc/dbdma.h
deleted file mode 100644
index 8973565f95d3..000000000000
--- a/include/asm-ppc/dbdma.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * Definitions for using the Apple Descriptor-Based DMA controller
3 * in Power Macintosh computers.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
8#ifdef __KERNEL__
9#ifndef _ASM_DBDMA_H_
10#define _ASM_DBDMA_H_
11/*
12 * DBDMA control/status registers. All little-endian.
13 */
14struct dbdma_regs {
15 unsigned int control; /* lets you change bits in status */
16 unsigned int status; /* DMA and device status bits (see below) */
17 unsigned int cmdptr_hi; /* upper 32 bits of command address */
18 unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
19 unsigned int intr_sel; /* select interrupt condition bit */
20 unsigned int br_sel; /* select branch condition bit */
21 unsigned int wait_sel; /* select wait condition bit */
22 unsigned int xfer_mode;
23 unsigned int data2ptr_hi;
24 unsigned int data2ptr;
25 unsigned int res1;
26 unsigned int address_hi;
27 unsigned int br_addr_hi;
28 unsigned int res2[3];
29};
30
31/* Bits in control and status registers */
32#define RUN 0x8000
33#define PAUSE 0x4000
34#define FLUSH 0x2000
35#define WAKE 0x1000
36#define DEAD 0x0800
37#define ACTIVE 0x0400
38#define BT 0x0100
39#define DEVSTAT 0x00ff
40
41/*
42 * DBDMA command structure. These fields are all little-endian!
43 */
44struct dbdma_cmd {
45 unsigned short req_count; /* requested byte transfer count */
46 unsigned short command; /* command word (has bit-fields) */
47 unsigned int phy_addr; /* physical data address */
48 unsigned int cmd_dep; /* command-dependent field */
49 unsigned short res_count; /* residual count after completion */
50 unsigned short xfer_status; /* transfer status */
51};
52
53/* DBDMA command values in command field */
54#define OUTPUT_MORE 0 /* transfer memory data to stream */
55#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
56#define INPUT_MORE 0x2000 /* transfer stream data to memory */
57#define INPUT_LAST 0x3000 /* ditto, expect end marker */
58#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
59#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
60#define DBDMA_NOP 0x6000 /* do nothing */
61#define DBDMA_STOP 0x7000 /* suspend processing */
62
63/* Key values in command field */
64#define KEY_STREAM0 0 /* usual data stream */
65#define KEY_STREAM1 0x100 /* control/status stream */
66#define KEY_STREAM2 0x200 /* device-dependent stream */
67#define KEY_STREAM3 0x300 /* device-dependent stream */
68#define KEY_REGS 0x500 /* device register space */
69#define KEY_SYSTEM 0x600 /* system memory-mapped space */
70#define KEY_DEVICE 0x700 /* device memory-mapped space */
71
72/* Interrupt control values in command field */
73#define INTR_NEVER 0 /* don't interrupt */
74#define INTR_IFSET 0x10 /* intr if condition bit is 1 */
75#define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
76#define INTR_ALWAYS 0x30 /* always interrupt */
77
78/* Branch control values in command field */
79#define BR_NEVER 0 /* don't branch */
80#define BR_IFSET 0x4 /* branch if condition bit is 1 */
81#define BR_IFCLR 0x8 /* branch if condition bit is 0 */
82#define BR_ALWAYS 0xc /* always branch */
83
84/* Wait control values in command field */
85#define WAIT_NEVER 0 /* don't wait */
86#define WAIT_IFSET 1 /* wait if condition bit is 1 */
87#define WAIT_IFCLR 2 /* wait if condition bit is 0 */
88#define WAIT_ALWAYS 3 /* always wait */
89
90/* Align an address for a DBDMA command structure */
91#define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
92 & -sizeof(struct dbdma_cmd))
93
94/* Useful macros */
95#define DBDMA_DO_STOP(regs) do { \
96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
97 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
98 ; \
99} while(0)
100
101#endif /* _ASM_DBDMA_H_ */
102#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/dma.h b/include/asm-ppc/dma.h
deleted file mode 100644
index cc8e5cd8c9d2..000000000000
--- a/include/asm-ppc/dma.h
+++ /dev/null
@@ -1,371 +0,0 @@
1/*
2 * include/asm-ppc/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 * Changes for ppc sound by Christoph Nadig
7 */
8
9#ifdef __KERNEL__
10
11#include <linux/config.h>
12#include <asm/io.h>
13#include <linux/spinlock.h>
14#include <asm/system.h>
15
16/*
17 * Note: Adapted for PowerPC by Gary Thomas
18 * Modified by Cort Dougan <cort@cs.nmt.edu>
19 *
20 * None of this really applies for Power Macintoshes. There is
21 * basically just enough here to get kernel/dma.c to compile.
22 *
23 * There may be some comments or restrictions made here which are
24 * not valid for the PReP platform. Take what you read
25 * with a grain of salt.
26 */
27
28#ifndef _ASM_DMA_H
29#define _ASM_DMA_H
30
31#ifndef MAX_DMA_CHANNELS
32#define MAX_DMA_CHANNELS 8
33#endif
34
35/* The maximum address that we can perform a DMA transfer to on this platform */
36/* Doesn't really apply... */
37#define MAX_DMA_ADDRESS 0xFFFFFFFF
38
39/* in arch/ppc/kernel/setup.c -- Cort */
40extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
41extern unsigned long ISA_DMA_THRESHOLD;
42
43#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
44#define dma_outb outb_p
45#else
46#define dma_outb outb
47#endif
48
49#define dma_inb inb
50
51/*
52 * NOTES about DMA transfers:
53 *
54 * controller 1: channels 0-3, byte operations, ports 00-1F
55 * controller 2: channels 4-7, word operations, ports C0-DF
56 *
57 * - ALL registers are 8 bits only, regardless of transfer size
58 * - channel 4 is not used - cascades 1 into 2.
59 * - channels 0-3 are byte - addresses/counts are for physical bytes
60 * - channels 5-7 are word - addresses/counts are for physical words
61 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
62 * - transfer count loaded to registers is 1 less than actual count
63 * - controller 2 offsets are all even (2x offsets for controller 1)
64 * - page registers for 5-7 don't use data bit 0, represent 128K pages
65 * - page registers for 0-3 use bit 0, represent 64K pages
66 *
67 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
68 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
69 * Note that addresses loaded into registers must be _physical_ addresses,
70 * not logical addresses (which may differ if paging is active).
71 *
72 * Address mapping for channels 0-3:
73 *
74 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
75 * | ... | | ... | | ... |
76 * | ... | | ... | | ... |
77 * | ... | | ... | | ... |
78 * P7 ... P0 A7 ... A0 A7 ... A0
79 * | Page | Addr MSB | Addr LSB | (DMA registers)
80 *
81 * Address mapping for channels 5-7:
82 *
83 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
84 * | ... | \ \ ... \ \ \ ... \ \
85 * | ... | \ \ ... \ \ \ ... \ (not used)
86 * | ... | \ \ ... \ \ \ ... \
87 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
88 * | Page | Addr MSB | Addr LSB | (DMA registers)
89 *
90 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
91 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
92 * the hardware level, so odd-byte transfers aren't possible).
93 *
94 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
95 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
96 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
97 *
98 */
99
100/* see prep_setup_arch() for detailed informations */
101#if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_PPC_PREP)
102extern long ppc_cs4232_dma, ppc_cs4232_dma2;
103#define SND_DMA1 ppc_cs4232_dma
104#define SND_DMA2 ppc_cs4232_dma2
105#else
106#define SND_DMA1 -1
107#define SND_DMA2 -1
108#endif
109
110/* 8237 DMA controllers */
111#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
112#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
113
114/* DMA controller registers */
115#define DMA1_CMD_REG 0x08 /* command register (w) */
116#define DMA1_STAT_REG 0x08 /* status register (r) */
117#define DMA1_REQ_REG 0x09 /* request register (w) */
118#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
119#define DMA1_MODE_REG 0x0B /* mode register (w) */
120#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
121#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
122#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
123#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
124#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
125
126#define DMA2_CMD_REG 0xD0 /* command register (w) */
127#define DMA2_STAT_REG 0xD0 /* status register (r) */
128#define DMA2_REQ_REG 0xD2 /* request register (w) */
129#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
130#define DMA2_MODE_REG 0xD6 /* mode register (w) */
131#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
132#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
133#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
134#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
135#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
136
137#define DMA_ADDR_0 0x00 /* DMA address registers */
138#define DMA_ADDR_1 0x02
139#define DMA_ADDR_2 0x04
140#define DMA_ADDR_3 0x06
141#define DMA_ADDR_4 0xC0
142#define DMA_ADDR_5 0xC4
143#define DMA_ADDR_6 0xC8
144#define DMA_ADDR_7 0xCC
145
146#define DMA_CNT_0 0x01 /* DMA count registers */
147#define DMA_CNT_1 0x03
148#define DMA_CNT_2 0x05
149#define DMA_CNT_3 0x07
150#define DMA_CNT_4 0xC2
151#define DMA_CNT_5 0xC6
152#define DMA_CNT_6 0xCA
153#define DMA_CNT_7 0xCE
154
155#define DMA_LO_PAGE_0 0x87 /* DMA page registers */
156#define DMA_LO_PAGE_1 0x83
157#define DMA_LO_PAGE_2 0x81
158#define DMA_LO_PAGE_3 0x82
159#define DMA_LO_PAGE_5 0x8B
160#define DMA_LO_PAGE_6 0x89
161#define DMA_LO_PAGE_7 0x8A
162
163#define DMA_HI_PAGE_0 0x487 /* DMA page registers */
164#define DMA_HI_PAGE_1 0x483
165#define DMA_HI_PAGE_2 0x481
166#define DMA_HI_PAGE_3 0x482
167#define DMA_HI_PAGE_5 0x48B
168#define DMA_HI_PAGE_6 0x489
169#define DMA_HI_PAGE_7 0x48A
170
171#define DMA1_EXT_REG 0x40B
172#define DMA2_EXT_REG 0x4D6
173
174#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
175#define DMA_AUTOINIT 0x10
176
177extern spinlock_t dma_spin_lock;
178
179static __inline__ unsigned long claim_dma_lock(void)
180{
181 unsigned long flags;
182 spin_lock_irqsave(&dma_spin_lock, flags);
183 return flags;
184}
185
186static __inline__ void release_dma_lock(unsigned long flags)
187{
188 spin_unlock_irqrestore(&dma_spin_lock, flags);
189}
190
191/* enable/disable a specific DMA channel */
192static __inline__ void enable_dma(unsigned int dmanr)
193{
194 unsigned char ucDmaCmd = 0x00;
195
196 if (dmanr != 4) {
197 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
198 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
199 }
200 if (dmanr <= 3) {
201 dma_outb(dmanr, DMA1_MASK_REG);
202 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
203 } else
204 dma_outb(dmanr & 3, DMA2_MASK_REG);
205}
206
207static __inline__ void disable_dma(unsigned int dmanr)
208{
209 if (dmanr <= 3)
210 dma_outb(dmanr | 4, DMA1_MASK_REG);
211 else
212 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
213}
214
215/* Clear the 'DMA Pointer Flip Flop'.
216 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
217 * Use this once to initialize the FF to a known state.
218 * After that, keep track of it. :-)
219 * --- In order to do that, the DMA routines below should ---
220 * --- only be used while interrupts are disabled! ---
221 */
222static __inline__ void clear_dma_ff(unsigned int dmanr)
223{
224 if (dmanr <= 3)
225 dma_outb(0, DMA1_CLEAR_FF_REG);
226 else
227 dma_outb(0, DMA2_CLEAR_FF_REG);
228}
229
230/* set mode (above) for a specific DMA channel */
231static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
232{
233 if (dmanr <= 3)
234 dma_outb(mode | dmanr, DMA1_MODE_REG);
235 else
236 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
237}
238
239/* Set only the page register bits of the transfer address.
240 * This is used for successive transfers when we know the contents of
241 * the lower 16 bits of the DMA current address register, but a 64k boundary
242 * may have been crossed.
243 */
244static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
245{
246 switch (dmanr) {
247 case 0:
248 dma_outb(pagenr, DMA_LO_PAGE_0);
249 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
250 break;
251 case 1:
252 dma_outb(pagenr, DMA_LO_PAGE_1);
253 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
254 break;
255 case 2:
256 dma_outb(pagenr, DMA_LO_PAGE_2);
257 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
258 break;
259 case 3:
260 dma_outb(pagenr, DMA_LO_PAGE_3);
261 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
262 break;
263 case 5:
264 if (SND_DMA1 == 5 || SND_DMA2 == 5)
265 dma_outb(pagenr, DMA_LO_PAGE_5);
266 else
267 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
268 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
269 break;
270 case 6:
271 if (SND_DMA1 == 6 || SND_DMA2 == 6)
272 dma_outb(pagenr, DMA_LO_PAGE_6);
273 else
274 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
275 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
276 break;
277 case 7:
278 if (SND_DMA1 == 7 || SND_DMA2 == 7)
279 dma_outb(pagenr, DMA_LO_PAGE_7);
280 else
281 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
282 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
283 break;
284 }
285}
286
287/* Set transfer address & page bits for specific DMA channel.
288 * Assumes dma flipflop is clear.
289 */
290static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
291{
292 if (dmanr <= 3) {
293 dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
294 dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
295 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
296 dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
297 dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
298 dma_outb((dmanr & 3), DMA2_EXT_REG);
299 } else {
300 dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
301 dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
302 }
303 set_dma_page(dmanr, phys >> 16);
304}
305
306/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
307 * a specific DMA channel.
308 * You must ensure the parameters are valid.
309 * NOTE: from a manual: "the number of transfers is one more
310 * than the initial word count"! This is taken into account.
311 * Assumes dma flip-flop is clear.
312 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
313 */
314static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
315{
316 count--;
317 if (dmanr <= 3) {
318 dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
319 dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 +
320 IO_DMA1_BASE);
321 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
322 dma_outb(count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
323 dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 +
324 IO_DMA2_BASE);
325 } else {
326 dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 +
327 IO_DMA2_BASE);
328 dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 +
329 IO_DMA2_BASE);
330 }
331}
332
333/* Get DMA residue count. After a DMA transfer, this
334 * should return zero. Reading this while a DMA transfer is
335 * still in progress will return unpredictable results.
336 * If called before the channel has been used, it may return 1.
337 * Otherwise, it returns the number of _bytes_ left to transfer.
338 *
339 * Assumes DMA flip-flop is clear.
340 */
341static __inline__ int get_dma_residue(unsigned int dmanr)
342{
343 unsigned int io_port = (dmanr <= 3) ?
344 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
345 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
346
347 /* using short to get 16-bit wrap around */
348 unsigned short count;
349
350 count = 1 + dma_inb(io_port);
351 count += dma_inb(io_port) << 8;
352
353 return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
354 ? count : (count << 1);
355
356}
357
358/* These are in kernel/dma.c: */
359
360/* reserve a DMA channel */
361extern int request_dma(unsigned int dmanr, const char *device_id);
362/* release it again */
363extern void free_dma(unsigned int dmanr);
364
365#ifdef CONFIG_PCI
366extern int isa_dma_bridge_buggy;
367#else
368#define isa_dma_bridge_buggy (0)
369#endif
370#endif /* _ASM_DMA_H */
371#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/elf.h b/include/asm-ppc/elf.h
deleted file mode 100644
index c25cc35e6ab5..000000000000
--- a/include/asm-ppc/elf.h
+++ /dev/null
@@ -1,151 +0,0 @@
1#ifndef __PPC_ELF_H
2#define __PPC_ELF_H
3
4/*
5 * ELF register definitions..
6 */
7#include <asm/types.h>
8#include <asm/ptrace.h>
9#include <asm/cputable.h>
10#include <asm/auxvec.h>
11
12/* PowerPC relocations defined by the ABIs */
13#define R_PPC_NONE 0
14#define R_PPC_ADDR32 1 /* 32bit absolute address */
15#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
16#define R_PPC_ADDR16 3 /* 16bit absolute address */
17#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
18#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
19#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
20#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
21#define R_PPC_ADDR14_BRTAKEN 8
22#define R_PPC_ADDR14_BRNTAKEN 9
23#define R_PPC_REL24 10 /* PC relative 26 bit */
24#define R_PPC_REL14 11 /* PC relative 16 bit */
25#define R_PPC_REL14_BRTAKEN 12
26#define R_PPC_REL14_BRNTAKEN 13
27#define R_PPC_GOT16 14
28#define R_PPC_GOT16_LO 15
29#define R_PPC_GOT16_HI 16
30#define R_PPC_GOT16_HA 17
31#define R_PPC_PLTREL24 18
32#define R_PPC_COPY 19
33#define R_PPC_GLOB_DAT 20
34#define R_PPC_JMP_SLOT 21
35#define R_PPC_RELATIVE 22
36#define R_PPC_LOCAL24PC 23
37#define R_PPC_UADDR32 24
38#define R_PPC_UADDR16 25
39#define R_PPC_REL32 26
40#define R_PPC_PLT32 27
41#define R_PPC_PLTREL32 28
42#define R_PPC_PLT16_LO 29
43#define R_PPC_PLT16_HI 30
44#define R_PPC_PLT16_HA 31
45#define R_PPC_SDAREL16 32
46#define R_PPC_SECTOFF 33
47#define R_PPC_SECTOFF_LO 34
48#define R_PPC_SECTOFF_HI 35
49#define R_PPC_SECTOFF_HA 36
50/* Keep this the last entry. */
51#define R_PPC_NUM 37
52
53#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
54#define ELF_NFPREG 33 /* includes fpscr */
55#define ELF_NVRREG 33 /* includes vscr */
56#define ELF_NEVRREG 34 /* includes acc (as 2) */
57
58/*
59 * These are used to set parameters in the core dumps.
60 */
61#define ELF_ARCH EM_PPC
62#define ELF_CLASS ELFCLASS32
63#define ELF_DATA ELFDATA2MSB
64
65/* General registers */
66typedef unsigned long elf_greg_t;
67typedef elf_greg_t elf_gregset_t[ELF_NGREG];
68
69/* Floating point registers */
70typedef double elf_fpreg_t;
71typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
72
73/* Altivec registers */
74typedef __vector128 elf_vrreg_t;
75typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
76
77#ifdef __KERNEL__
78
79struct task_struct;
80
81/*
82 * This is used to ensure we don't load something for the wrong architecture.
83 */
84
85#define elf_check_arch(x) ((x)->e_machine == EM_PPC)
86
87/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
88 use of this is to invoke "./ld.so someprog" to test out a new version of
89 the loader. We need to make sure that it is out of the way of the program
90 that it will "exec", and that there is sufficient room for the brk. */
91
92#define ELF_ET_DYN_BASE (0x08000000)
93
94#define USE_ELF_CORE_DUMP
95#define ELF_EXEC_PAGESIZE 4096
96
97#define ELF_CORE_COPY_REGS(gregs, regs) \
98 memcpy((gregs), (regs), sizeof(struct pt_regs)); \
99 memset((char *)(gregs) + sizeof(struct pt_regs), 0, \
100 sizeof(elf_gregset_t) - sizeof(struct pt_regs));
101
102#define ELF_CORE_COPY_TASK_REGS(t, elfregs) \
103 ((t)->thread.regs? \
104 ({ ELF_CORE_COPY_REGS((elfregs), (t)->thread.regs); 1; }): 0)
105
106extern int dump_task_fpu(struct task_struct *t, elf_fpregset_t *fpu);
107#define ELF_CORE_COPY_FPREGS(t, fpu) dump_task_fpu((t), (fpu))
108
109/* This yields a mask that user programs can use to figure out what
110 instruction set this cpu supports. This could be done in userspace,
111 but it's not easy, and we've already done it here. */
112
113#define ELF_HWCAP (cur_cpu_spec[0]->cpu_user_features)
114
115/* This yields a string that ld.so will use to load implementation
116 specific libraries for optimization. This is more specific in
117 intent than poking at uname or /proc/cpuinfo.
118
119 For the moment, we have only optimizations for the Intel generations,
120 but that could change... */
121
122#define ELF_PLATFORM (NULL)
123
124#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
125
126extern int dcache_bsize;
127extern int icache_bsize;
128extern int ucache_bsize;
129
130/*
131 * The requirements here are:
132 * - keep the final alignment of sp (sp & 0xf)
133 * - make sure the 32-bit value at the first 16 byte aligned position of
134 * AUXV is greater than 16 for glibc compatibility.
135 * AT_IGNOREPPC is used for that.
136 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
137 * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
138 */
139#define ARCH_DLINFO \
140do { \
141 /* Handle glibc compatibility. */ \
142 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
143 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
144 /* Cache size items */ \
145 NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
146 NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
147 NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
148 } while (0)
149
150#endif /* __KERNEL__ */
151#endif
diff --git a/include/asm-ppc/hardirq.h b/include/asm-ppc/hardirq.h
deleted file mode 100644
index 94f1411b1a93..000000000000
--- a/include/asm-ppc/hardirq.h
+++ /dev/null
@@ -1,31 +0,0 @@
1#ifdef __KERNEL__
2#ifndef __ASM_HARDIRQ_H
3#define __ASM_HARDIRQ_H
4
5#include <linux/config.h>
6#include <linux/cache.h>
7#include <linux/smp_lock.h>
8#include <asm/irq.h>
9
10/* The __last_jiffy_stamp field is needed to ensure that no decrementer
11 * interrupt is lost on SMP machines. Since on most CPUs it is in the same
12 * cache line as local_irq_count, it is cheap to access and is also used on UP
13 * for uniformity.
14 */
15typedef struct {
16 unsigned long __softirq_pending; /* set_bit is used on this */
17 unsigned int __last_jiffy_stamp;
18} ____cacheline_aligned irq_cpustat_t;
19
20#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
21
22#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
23
24static inline void ack_bad_irq(int irq)
25{
26 printk(KERN_CRIT "illegal vector %d received!\n", irq);
27 BUG();
28}
29
30#endif /* __ASM_HARDIRQ_H */
31#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/heathrow.h b/include/asm-ppc/heathrow.h
deleted file mode 100644
index 22ac179856b9..000000000000
--- a/include/asm-ppc/heathrow.h
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
3 *
4 * Grabbed from Open Firmware definitions on a PowerBook G3 Series
5 *
6 * Copyright (C) 1997 Paul Mackerras.
7 */
8
9/* Front light color on Yikes/B&W G3. 32 bits */
10#define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */
11
12/* Brightness/contrast (gossamer iMac ?). 8 bits */
13#define HEATHROW_BRIGHTNESS_CNTL 0x32
14#define HEATHROW_CONTRAST_CNTL 0x33
15
16/* offset from ohare base for feature control register */
17#define HEATHROW_MBCR 0x34 /* Media bay control */
18#define HEATHROW_FCR 0x38 /* Feature control */
19#define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */
20
21/*
22 * Bits in feature control register.
23 * Bits postfixed with a _N are in inverse logic
24 */
25#define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */
26#define HRW_BAY_POWER_N 0x00000002
27#define HRW_BAY_PCI_ENABLE 0x00000004
28#define HRW_BAY_IDE_ENABLE 0x00000008
29#define HRW_BAY_FLOPPY_ENABLE 0x00000010
30#define HRW_IDE0_ENABLE 0x00000020
31#define HRW_IDE0_RESET_N 0x00000040
32#define HRW_BAY_DEV_MASK 0x0000001c
33#define HRW_BAY_RESET_N 0x00000080
34#define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */
35#define HRW_SCC_ENABLE 0x00000200
36#define HRW_MESH_ENABLE 0x00000400
37#define HRW_SWIM_ENABLE 0x00000800
38#define HRW_SOUND_POWER_N 0x00001000
39#define HRW_SOUND_CLK_ENABLE 0x00002000
40#define HRW_SCCA_IO 0x00004000
41#define HRW_SCCB_IO 0x00008000
42#define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */
43#define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */
44#define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */
45#define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */
46#define HRW_AUD_RUN22 0x00100000 /* ??? (1) */
47#define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */
48#define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */
49#define HRW_IDE1_RESET_N 0x00800000 /* Media bay */
50#define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */
51#define HRW_RESET_SCC 0x02000000
52#define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */
53#define HRW_USE_MFDC 0x08000000 /* ??? (0) */
54#define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */
55#define HRW_BMAC_RESET 0x80000000 /* not documented in OF */
56
57/* We OR those features at boot on desktop G3s */
58#define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
59
60/* Looks like Heathrow has some sort of GPIOs as well... */
61#define HRW_GPIO_MODEM_RESET 0x6d
62
diff --git a/include/asm-ppc/hw_irq.h b/include/asm-ppc/hw_irq.h
deleted file mode 100644
index 47dc7990fb26..000000000000
--- a/include/asm-ppc/hw_irq.h
+++ /dev/null
@@ -1,74 +0,0 @@
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifdef __KERNEL__
5#ifndef _PPC_HW_IRQ_H
6#define _PPC_HW_IRQ_H
7
8#include <asm/ptrace.h>
9#include <asm/reg.h>
10
11extern void timer_interrupt(struct pt_regs *);
12
13#define INLINE_IRQS
14
15#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
16
17#ifdef INLINE_IRQS
18
19static inline void local_irq_disable(void)
20{
21 unsigned long msr;
22 msr = mfmsr();
23 mtmsr(msr & ~MSR_EE);
24 __asm__ __volatile__("": : :"memory");
25}
26
27static inline void local_irq_enable(void)
28{
29 unsigned long msr;
30 __asm__ __volatile__("": : :"memory");
31 msr = mfmsr();
32 mtmsr(msr | MSR_EE);
33}
34
35static inline void local_irq_save_ptr(unsigned long *flags)
36{
37 unsigned long msr;
38 msr = mfmsr();
39 *flags = msr;
40 mtmsr(msr & ~MSR_EE);
41 __asm__ __volatile__("": : :"memory");
42}
43
44#define local_save_flags(flags) ((flags) = mfmsr())
45#define local_irq_save(flags) local_irq_save_ptr(&flags)
46#define local_irq_restore(flags) mtmsr(flags)
47
48#else
49
50extern void local_irq_enable(void);
51extern void local_irq_disable(void);
52extern void local_irq_restore(unsigned long);
53extern void local_save_flags_ptr(unsigned long *);
54
55#define local_save_flags(flags) local_save_flags_ptr(&flags)
56#define local_irq_save(flags) ({local_save_flags(flags);local_irq_disable();})
57
58#endif
59
60extern void do_lost_interrupts(unsigned long);
61
62#define mask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->disable) irq_desc[irq].handler->disable(irq);})
63#define unmask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->enable) irq_desc[irq].handler->enable(irq);})
64#define ack_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->ack) irq_desc[irq].handler->ack(irq);})
65
66/* Should we handle this via lost interrupts and IPIs or should we don't care like
67 * we do now ? --BenH.
68 */
69struct hw_interrupt_type;
70static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
71
72
73#endif /* _PPC_HW_IRQ_H */
74#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/i8259.h b/include/asm-ppc/i8259.h
deleted file mode 100644
index 091b71295de4..000000000000
--- a/include/asm-ppc/i8259.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef _PPC_KERNEL_i8259_H
2#define _PPC_KERNEL_i8259_H
3
4#include <linux/irq.h>
5
6extern struct hw_interrupt_type i8259_pic;
7
8extern void i8259_init(long intack_addr);
9extern int i8259_irq(struct pt_regs *regs);
10
11#endif /* _PPC_KERNEL_i8259_H */
diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h
index 94d83998a759..f7f614dfc648 100644
--- a/include/asm-ppc/io.h
+++ b/include/asm-ppc/io.h
@@ -8,6 +8,7 @@
8 8
9#include <asm/page.h> 9#include <asm/page.h>
10#include <asm/byteorder.h> 10#include <asm/byteorder.h>
11#include <asm/synch.h>
11#include <asm/mmu.h> 12#include <asm/mmu.h>
12 13
13#define SIO_CONFIG_RA 0x398 14#define SIO_CONFIG_RA 0x398
@@ -440,16 +441,6 @@ extern inline void * phys_to_virt(unsigned long address)
440#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) 441#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
441#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET) 442#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
442 443
443/*
444 * Enforce In-order Execution of I/O:
445 * Acts as a barrier to ensure all previous I/O accesses have
446 * completed before any further ones are issued.
447 */
448extern inline void eieio(void)
449{
450 __asm__ __volatile__ ("eieio" : : : "memory");
451}
452
453/* Enforce in-order execution of data I/O. 444/* Enforce in-order execution of data I/O.
454 * No distinction between read/write on PPC; use eieio for all three. 445 * No distinction between read/write on PPC; use eieio for all three.
455 */ 446 */
diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h
deleted file mode 100644
index bd9674807f05..000000000000
--- a/include/asm-ppc/irq.h
+++ /dev/null
@@ -1,418 +0,0 @@
1#ifdef __KERNEL__
2#ifndef _ASM_IRQ_H
3#define _ASM_IRQ_H
4
5#include <linux/config.h>
6#include <asm/machdep.h> /* ppc_md */
7#include <asm/atomic.h>
8
9/*
10 * These constants are used for passing information about interrupt
11 * signal polarity and level/edge sensing to the low-level PIC chip
12 * drivers.
13 */
14#define IRQ_SENSE_MASK 0x1
15#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
16#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
17
18#define IRQ_POLARITY_MASK 0x2
19#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
20#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
21
22/*
23 * IRQ line status macro IRQ_PER_CPU is used
24 */
25#define ARCH_HAS_IRQ_PER_CPU
26
27#if defined(CONFIG_40x)
28#include <asm/ibm4xx.h>
29
30#ifndef NR_BOARD_IRQS
31#define NR_BOARD_IRQS 0
32#endif
33
34#ifndef UIC_WIDTH /* Number of interrupts per device */
35#define UIC_WIDTH 32
36#endif
37
38#ifndef NR_UICS /* number of UIC devices */
39#define NR_UICS 1
40#endif
41
42#if defined (CONFIG_403)
43/*
44 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
45 * 32 possible interrupts, a majority of which are not implemented on
46 * all cores. There are six configurable, external interrupt pins and
47 * there are eight internal interrupts for the on-chip serial port
48 * (SPU), DMA controller, and JTAG controller.
49 *
50 */
51
52#define NR_AIC_IRQS 32
53#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
54
55#elif !defined (CONFIG_403)
56
57/*
58 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
59 * possible interrupts as well. There are seven, configurable external
60 * interrupt pins and there are 17 internal interrupts for the on-chip
61 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
62 *
63 */
64
65
66#define NR_UIC_IRQS UIC_WIDTH
67#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
68#endif
69static __inline__ int
70irq_canonicalize(int irq)
71{
72 return (irq);
73}
74
75#elif defined(CONFIG_44x)
76#include <asm/ibm44x.h>
77
78#define NR_UIC_IRQS 32
79#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
80
81static __inline__ int
82irq_canonicalize(int irq)
83{
84 return (irq);
85}
86
87#elif defined(CONFIG_8xx)
88
89/* Now include the board configuration specific associations.
90*/
91#include <asm/mpc8xx.h>
92
93/* The MPC8xx cores have 16 possible interrupts. There are eight
94 * possible level sensitive interrupts assigned and generated internally
95 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
96 * There are eight external interrupts (IRQs) that can be configured
97 * as either level or edge sensitive.
98 *
99 * On some implementations, there is also the possibility of an 8259
100 * through the PCI and PCI-ISA bridges.
101 *
102 * We are "flattening" the interrupt vectors of the cascaded CPM
103 * and 8259 interrupt controllers so that we can uniquely identify
104 * any interrupt source with a single integer.
105 */
106#define NR_SIU_INTS 16
107#define NR_CPM_INTS 32
108#ifndef NR_8259_INTS
109#define NR_8259_INTS 0
110#endif
111
112#define SIU_IRQ_OFFSET 0
113#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
114#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
115
116#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
117
118/* These values must be zero-based and map 1:1 with the SIU configuration.
119 * They are used throughout the 8xx I/O subsystem to generate
120 * interrupt masks, flags, and other control patterns. This is why the
121 * current kernel assumption of the 8259 as the base controller is such
122 * a pain in the butt.
123 */
124#define SIU_IRQ0 (0) /* Highest priority */
125#define SIU_LEVEL0 (1)
126#define SIU_IRQ1 (2)
127#define SIU_LEVEL1 (3)
128#define SIU_IRQ2 (4)
129#define SIU_LEVEL2 (5)
130#define SIU_IRQ3 (6)
131#define SIU_LEVEL3 (7)
132#define SIU_IRQ4 (8)
133#define SIU_LEVEL4 (9)
134#define SIU_IRQ5 (10)
135#define SIU_LEVEL5 (11)
136#define SIU_IRQ6 (12)
137#define SIU_LEVEL6 (13)
138#define SIU_IRQ7 (14)
139#define SIU_LEVEL7 (15)
140
141#define MPC8xx_INT_FEC1 SIU_LEVEL1
142#define MPC8xx_INT_FEC2 SIU_LEVEL3
143
144#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
145#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
146#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
147#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
148#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
149#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
150
151/* The internal interrupts we can configure as we see fit.
152 * My personal preference is CPM at level 2, which puts it above the
153 * MBX PCI/ISA/IDE interrupts.
154 */
155#ifndef PIT_INTERRUPT
156#define PIT_INTERRUPT SIU_LEVEL0
157#endif
158#ifndef CPM_INTERRUPT
159#define CPM_INTERRUPT SIU_LEVEL2
160#endif
161#ifndef PCMCIA_INTERRUPT
162#define PCMCIA_INTERRUPT SIU_LEVEL6
163#endif
164#ifndef DEC_INTERRUPT
165#define DEC_INTERRUPT SIU_LEVEL7
166#endif
167
168/* Some internal interrupt registers use an 8-bit mask for the interrupt
169 * level instead of a number.
170 */
171#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
172
173/* always the same on 8xx -- Cort */
174static __inline__ int irq_canonicalize(int irq)
175{
176 return irq;
177}
178
179#elif defined(CONFIG_83xx)
180#include <asm/mpc83xx.h>
181
182static __inline__ int irq_canonicalize(int irq)
183{
184 return irq;
185}
186
187#define NR_IRQS (NR_IPIC_INTS)
188
189#elif defined(CONFIG_85xx)
190/* Now include the board configuration specific associations.
191*/
192#include <asm/mpc85xx.h>
193
194/* The MPC8548 openpic has 48 internal interrupts and 12 external
195 * interrupts.
196 *
197 * We are "flattening" the interrupt vectors of the cascaded CPM
198 * so that we can uniquely identify any interrupt source with a
199 * single integer.
200 */
201#define NR_CPM_INTS 64
202#define NR_EPIC_INTS 60
203#ifndef NR_8259_INTS
204#define NR_8259_INTS 0
205#endif
206#define NUM_8259_INTERRUPTS NR_8259_INTS
207
208#ifndef CPM_IRQ_OFFSET
209#define CPM_IRQ_OFFSET 0
210#endif
211
212#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
213
214/* Internal IRQs on MPC85xx OpenPIC */
215
216#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
217#ifdef CONFIG_CPM2
218#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
219#else
220#define MPC85xx_OPENPIC_IRQ_OFFSET 0
221#endif
222#endif
223
224/* Not all of these exist on all MPC85xx implementations */
225#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
226#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
227#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
228#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
229#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
230#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
231#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
232#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
233#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
234#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
235#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
236#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
237#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
238#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
239#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
240#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
241#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
242#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
243#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
244#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
245#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
246#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
247#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
248#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
249#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
250#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
251#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
252#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
253#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
254#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
255#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
256#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
257
258/* The 12 external interrupt lines */
259#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
260#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
261#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
262#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
263#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
264#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
265#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
266#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
267#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
268#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
269#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
270#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
271
272/* CPM related interrupts */
273#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
274#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
275#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
276#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
277#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
278#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
279#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
280#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
281#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
282#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
283#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
284#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
285#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
286#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
287#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
288#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
289#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
290#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
291#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
292#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
293#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
294#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
295#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
296#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
297#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
298#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
299#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
300#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
301#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
302#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
303#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
304#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
305#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
306#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
307#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
308#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
309
310static __inline__ int irq_canonicalize(int irq)
311{
312 return irq;
313}
314
315#else /* CONFIG_40x + CONFIG_8xx */
316/*
317 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
318 * so it is the max of them all
319 */
320#define NR_IRQS 256
321
322#ifndef CONFIG_8260
323
324#define NUM_8259_INTERRUPTS 16
325
326#else /* CONFIG_8260 */
327
328/* The 8260 has an internal interrupt controller with a maximum of
329 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
330 * Don't be confused by the 8260 documentation where they list an
331 * "interrupt number" and "interrupt vector". We are only interested
332 * in the interrupt vector. There are "reserved" holes where the
333 * vector number increases, but the interrupt number in the table does not.
334 * (Document errata updates have fixed this...make sure you have up to
335 * date processor documentation -- Dan).
336 */
337
338#ifndef CPM_IRQ_OFFSET
339#define CPM_IRQ_OFFSET 0
340#endif
341
342#define NR_CPM_INTS 64
343
344#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
345#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
346#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
347#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
348#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
349#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
350#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
351#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
352#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
353#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
354#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
355#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
356#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
357#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
358#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
359#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
360#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
361#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
362#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
363#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
364#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
365#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
366#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
367#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
368#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
369#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
370#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
371#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
372#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
373#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
374#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
375#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
376#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
377#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
378#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
379#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
380#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
381#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
382#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
383#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
384#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
385#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
386#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
387#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
388#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
389#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
390#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
391#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
392#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
393#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
394
395#endif /* CONFIG_8260 */
396
397/*
398 * This gets called from serial.c, which is now used on
399 * powermacs as well as prep/chrp boxes.
400 * Prep and chrp both have cascaded 8259 PICs.
401 */
402static __inline__ int irq_canonicalize(int irq)
403{
404 if (ppc_md.irq_canonicalize)
405 return ppc_md.irq_canonicalize(irq);
406 return irq;
407}
408
409#endif
410
411#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
412/* pedantic: these are long because they are used with set_bit --RR */
413extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
414extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
415extern atomic_t ppc_n_lost_interrupts;
416
417#endif /* _ASM_IRQ_H */
418#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/keylargo.h b/include/asm-ppc/keylargo.h
deleted file mode 100644
index a669a3f0f5a2..000000000000
--- a/include/asm-ppc/keylargo.h
+++ /dev/null
@@ -1,248 +0,0 @@
1/*
2 * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
3 *
4 */
5
6/* "Pangea" chipset has keylargo device-id 0x25 while core99
7 * has device-id 0x22. The rev. of the pangea one is 0, so we
8 * fake an artificial rev. in keylargo_rev by oring 0x100
9 */
10#define KL_PANGEA_REV 0x100
11
12/* offset from base for feature control registers */
13#define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
14#define KEYLARGO_FCR0 0x38
15#define KEYLARGO_FCR1 0x3c
16#define KEYLARGO_FCR2 0x40
17#define KEYLARGO_FCR3 0x44
18#define KEYLARGO_FCR4 0x48
19#define KEYLARGO_FCR5 0x4c /* Pangea only */
20
21/* K2 aditional FCRs */
22#define K2_FCR6 0x34
23#define K2_FCR7 0x30
24#define K2_FCR8 0x2c
25#define K2_FCR9 0x28
26#define K2_FCR10 0x24
27
28/* GPIO registers */
29#define KEYLARGO_GPIO_LEVELS0 0x50
30#define KEYLARGO_GPIO_LEVELS1 0x54
31#define KEYLARGO_GPIO_EXTINT_0 0x58
32#define KEYLARGO_GPIO_EXTINT_CNT 18
33#define KEYLARGO_GPIO_0 0x6A
34#define KEYLARGO_GPIO_CNT 17
35#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80
36#define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04
37#define KEYLARGO_GPIO_OUTOUT_DATA 0x01
38#define KEYLARGO_GPIO_INPUT_DATA 0x02
39
40/* K2 does only extint GPIOs and does 51 of them */
41#define K2_GPIO_EXTINT_0 0x58
42#define K2_GPIO_EXTINT_CNT 51
43
44/* Specific GPIO regs */
45
46#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03)
47#define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */
48
49#define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05)
50
51/* Hrm... this one is only to be used on Pismo. It seeem to also
52 * control the timebase enable on other machines. Still to be
53 * experimented... --BenH.
54 */
55#define KL_GPIO_FW_CABLE_POWER (KEYLARGO_GPIO_0+0x09)
56#define KL_GPIO_TB_ENABLE (KEYLARGO_GPIO_0+0x09)
57
58#define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10)
59
60#define KL_GPIO_EXTINT_CPU1 (KEYLARGO_GPIO_0+0x0a)
61#define KL_GPIO_EXTINT_CPU1_ASSERT 0x04
62#define KL_GPIO_EXTINT_CPU1_RELEASE 0x38
63
64#define KL_GPIO_RESET_CPU0 (KEYLARGO_GPIO_EXTINT_0+0x03)
65#define KL_GPIO_RESET_CPU1 (KEYLARGO_GPIO_EXTINT_0+0x04)
66#define KL_GPIO_RESET_CPU2 (KEYLARGO_GPIO_EXTINT_0+0x0f)
67#define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10)
68
69#define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09)
70#define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA
71
72#define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e)
73
74#define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a)
75#define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d)
76#define KL_GPIO_AIRPORT_2 (KEYLARGO_GPIO_0+0x0d)
77#define KL_GPIO_AIRPORT_3 (KEYLARGO_GPIO_0+0x0e)
78#define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f)
79
80/*
81 * Bits in feature control register. Those bits different for K2 are
82 * listed separately
83 */
84#define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */
85#define KL_MBCR_MB0_IDE_ENABLE 0x00001000
86#define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */
87#define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */
88#define KL_MBCR_MB0_DEV_MASK 0x00007800
89#define KL_MBCR_MB0_DEV_POWER 0x00000400
90#define KL_MBCR_MB0_DEV_RESET 0x00000200
91#define KL_MBCR_MB0_ENABLE 0x00000100
92#define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */
93#define KL_MBCR_MB1_IDE_ENABLE 0x10000000
94#define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */
95#define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */
96#define KL_MBCR_MB1_DEV_MASK 0x78000000
97#define KL_MBCR_MB1_DEV_POWER 0x04000000
98#define KL_MBCR_MB1_DEV_RESET 0x02000000
99#define KL_MBCR_MB1_ENABLE 0x01000000
100
101#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */
102#define KL0_SCC_A_INTF_ENABLE 0x00000002
103#define KL0_SCC_SLOWPCLK 0x00000004
104#define KL0_SCC_RESET 0x00000008
105#define KL0_SCCA_ENABLE 0x00000010
106#define KL0_SCCB_ENABLE 0x00000020
107#define KL0_SCC_CELL_ENABLE 0x00000040
108#define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */
109#define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */
110#define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */
111#define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */
112#define KL0_IRDA_RESET 0x00000800 /* (KL Only) */
113#define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */
114#define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */
115#define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */
116#define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */
117#define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */
118#define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */
119#define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */
120#define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */
121#define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */
122#define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */
123#define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */
124#define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */
125#define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */
126#define KL0_USB0_PAD_SUSPEND0 0x00040000
127#define KL0_USB0_PAD_SUSPEND1 0x00080000
128#define KL0_USB0_CELL_ENABLE 0x00100000
129#define KL0_USB1_PAD_SUSPEND0 0x00400000
130#define KL0_USB1_PAD_SUSPEND1 0x00800000
131#define KL0_USB1_CELL_ENABLE 0x01000000
132#define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */
133
134#define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \
135 KL0_SCC_SLOWPCLK | \
136 KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
137
138#define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */
139#define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */
140#define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */
141#define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */
142#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */
143#define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */
144#define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */
145#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */
146#define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */
147#define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */
148#define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */
149#define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */
150#define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */
151#define KL1_I2S0_CELL_ENABLE 0x00000400
152#define KL1_I2S0_CLK_ENABLE_BIT 0x00001000
153#define KL1_I2S0_ENABLE 0x00002000
154#define KL1_I2S1_CELL_ENABLE 0x00020000
155#define KL1_I2S1_CLK_ENABLE_BIT 0x00080000
156#define KL1_I2S1_ENABLE 0x00100000
157#define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */
158#define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */
159#define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */
160#define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */
161#define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */
162#define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */
163
164#define KL2_IOBUS_ENABLE 0x00000002
165#define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */
166#define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */
167#define KL2_MPIC_ENABLE 0x00020000
168#define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */
169#define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */
170#define KL2_MEM_IS_BIG 0x04000000
171#define KL2_CARDSEL_16 0x08000000
172
173#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */
174#define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */
175#define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */
176#define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */
177#define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */
178#define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */
179#define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */
180#define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */
181#define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */
182#define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */
183#define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */
184#define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */
185#define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */
186#define KL3_CLK66_ENABLE 0x00000100 /* KL Only */
187#define KL3_CLK49_ENABLE 0x00000200
188#define KL3_CLK45_ENABLE 0x00000400
189#define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */
190#define KL3_TIMER_CLK18_ENABLE 0x00001000
191#define KL3_I2S1_CLK18_ENABLE 0x00002000
192#define KL3_I2S0_CLK18_ENABLE 0x00004000
193#define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */
194#define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */
195#define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */
196#define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */
197
198/* Intrepid USB bus 2, port 0,1 */
199#define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3))
200#define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3))
201#define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3))
202#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3))
203#define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3))
204#define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3))
205#define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3))
206
207/* Port 0,1 : bus 0, port 2,3 : bus 1 */
208#define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3))
209#define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3))
210#define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3))
211#define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3))
212#define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3))
213#define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3))
214#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
215
216/* Pangea and Intrepid only */
217#define KL5_VIA_USE_CLK31 0000000001 /* Pangea Only */
218#define KL5_SCC_USE_CLK31 0x00000002 /* Pangea Only */
219#define KL5_PWM_CLK32_EN 0x00000004
220#define KL5_CLK3_68_EN 0x00000010
221#define KL5_CLK32_EN 0x00000020
222
223
224/* K2 definitions */
225#define K2_FCR0_USB0_SWRESET 0x00200000
226#define K2_FCR0_USB1_SWRESET 0x02000000
227#define K2_FCR0_RING_PME_DISABLE 0x08000000
228
229#define K2_FCR1_PCI1_BUS_RESET_N 0x00000010
230#define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020
231#define K2_FCR1_I2S0_CELL_ENABLE 0x00000400
232#define K2_FCR1_I2S0_RESET 0x00000800
233#define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000
234#define K2_FCR1_I2S0_ENABLE 0x00002000
235
236#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
237#define K2_FCR1_FW_CLK_ENABLE 0x00008000
238#define K2_FCR1_FW_RESET_N 0x00010000
239#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
240#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
241#define K2_FCR1_GMAC_RESET_N 0x01000000
242#define K2_FCR1_SATA_CLK_ENABLE 0x02000000
243#define K2_FCR1_SATA_POWER_DOWN 0x04000000
244#define K2_FCR1_SATA_RESET_N 0x08000000
245#define K2_FCR1_UATA_CLK_ENABLE 0x10000000
246#define K2_FCR1_UATA_RESET_N 0x40000000
247#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000
248
diff --git a/include/asm-ppc/kmap_types.h b/include/asm-ppc/kmap_types.h
deleted file mode 100644
index 6d6fc78731e5..000000000000
--- a/include/asm-ppc/kmap_types.h
+++ /dev/null
@@ -1,25 +0,0 @@
1#ifdef __KERNEL__
2#ifndef _ASM_KMAP_TYPES_H
3#define _ASM_KMAP_TYPES_H
4
5enum km_type {
6 KM_BOUNCE_READ,
7 KM_SKB_SUNRPC_DATA,
8 KM_SKB_DATA_SOFTIRQ,
9 KM_USER0,
10 KM_USER1,
11 KM_BIO_SRC_IRQ,
12 KM_BIO_DST_IRQ,
13 KM_PTE0,
14 KM_PTE1,
15 KM_IRQ0,
16 KM_IRQ1,
17 KM_SOFTIRQ0,
18 KM_SOFTIRQ1,
19 KM_PPC_SYNC_PAGE,
20 KM_PPC_SYNC_ICACHE,
21 KM_TYPE_NR
22};
23
24#endif
25#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
index 1d4ab70a56f3..f01255bd1dc3 100644
--- a/include/asm-ppc/machdep.h
+++ b/include/asm-ppc/machdep.h
@@ -98,7 +98,7 @@ struct machdep_calls {
98 98
99 /* Get access protection for /dev/mem */ 99 /* Get access protection for /dev/mem */
100 pgprot_t (*phys_mem_access_prot)(struct file *file, 100 pgprot_t (*phys_mem_access_prot)(struct file *file,
101 unsigned long offset, 101 unsigned long pfn,
102 unsigned long size, 102 unsigned long size,
103 pgprot_t vma_prot); 103 pgprot_t vma_prot);
104 104
@@ -167,7 +167,7 @@ extern sys_ctrler_t sys_ctrler;
167 167
168#ifdef CONFIG_SMP 168#ifdef CONFIG_SMP
169struct smp_ops_t { 169struct smp_ops_t {
170 void (*message_pass)(int target, int msg, unsigned long data, int wait); 170 void (*message_pass)(int target, int msg);
171 int (*probe)(void); 171 int (*probe)(void);
172 void (*kick_cpu)(int nr); 172 void (*kick_cpu)(int nr);
173 void (*setup_cpu)(int nr); 173 void (*setup_cpu)(int nr);
diff --git a/include/asm-ppc/macio.h b/include/asm-ppc/macio.h
deleted file mode 100644
index b553dd4b139e..000000000000
--- a/include/asm-ppc/macio.h
+++ /dev/null
@@ -1,140 +0,0 @@
1#ifndef __MACIO_ASIC_H__
2#define __MACIO_ASIC_H__
3
4#include <asm/of_device.h>
5
6extern struct bus_type macio_bus_type;
7
8/* MacIO device driver is defined later */
9struct macio_driver;
10struct macio_chip;
11
12#define MACIO_DEV_COUNT_RESOURCES 8
13#define MACIO_DEV_COUNT_IRQS 8
14
15/*
16 * the macio_bus structure is used to describe a "virtual" bus
17 * within a MacIO ASIC. It's typically provided by a macio_pci_asic
18 * PCI device, but could be provided differently as well (nubus
19 * machines using a fake OF tree).
20 *
21 * The pdev field can be NULL on non-PCI machines
22 */
23struct macio_bus
24{
25 struct macio_chip *chip; /* macio_chip (private use) */
26 int index; /* macio chip index in system */
27#ifdef CONFIG_PCI
28 struct pci_dev *pdev; /* PCI device hosting this bus */
29#endif
30};
31
32/*
33 * the macio_dev structure is used to describe a device
34 * within an Apple MacIO ASIC.
35 */
36struct macio_dev
37{
38 struct macio_bus *bus; /* macio bus this device is on */
39 struct macio_dev *media_bay; /* Device is part of a media bay */
40 struct of_device ofdev;
41 int n_resources;
42 struct resource resource[MACIO_DEV_COUNT_RESOURCES];
43 int n_interrupts;
44 struct resource interrupt[MACIO_DEV_COUNT_IRQS];
45};
46#define to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev)
47#define of_to_macio_device(d) container_of(d, struct macio_dev, ofdev)
48
49extern struct macio_dev *macio_dev_get(struct macio_dev *dev);
50extern void macio_dev_put(struct macio_dev *dev);
51
52/*
53 * Accessors to resources & interrupts and other device
54 * fields
55 */
56
57static inline int macio_resource_count(struct macio_dev *dev)
58{
59 return dev->n_resources;
60}
61
62static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no)
63{
64 return dev->resource[resource_no].start;
65}
66
67static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no)
68{
69 return dev->resource[resource_no].end;
70}
71
72static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no)
73{
74 struct resource *res = &dev->resource[resource_no];
75 if (res->start == 0 || res->end == 0 || res->end < res->start)
76 return 0;
77 return res->end - res->start + 1;
78}
79
80extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
81extern void macio_release_resource(struct macio_dev *dev, int resource_no);
82extern int macio_request_resources(struct macio_dev *dev, const char *name);
83extern void macio_release_resources(struct macio_dev *dev);
84
85static inline int macio_irq_count(struct macio_dev *dev)
86{
87 return dev->n_interrupts;
88}
89
90static inline int macio_irq(struct macio_dev *dev, int irq_no)
91{
92 return dev->interrupt[irq_no].start;
93}
94
95static inline void macio_set_drvdata(struct macio_dev *dev, void *data)
96{
97 dev_set_drvdata(&dev->ofdev.dev, data);
98}
99
100static inline void* macio_get_drvdata(struct macio_dev *dev)
101{
102 return dev_get_drvdata(&dev->ofdev.dev);
103}
104
105static inline struct device_node *macio_get_of_node(struct macio_dev *mdev)
106{
107 return mdev->ofdev.node;
108}
109
110#ifdef CONFIG_PCI
111static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
112{
113 return mdev->bus->pdev;
114}
115#endif
116
117/*
118 * A driver for a mac-io chip based device
119 */
120struct macio_driver
121{
122 char *name;
123 struct of_device_id *match_table;
124 struct module *owner;
125
126 int (*probe)(struct macio_dev* dev, const struct of_device_id *match);
127 int (*remove)(struct macio_dev* dev);
128
129 int (*suspend)(struct macio_dev* dev, pm_message_t state);
130 int (*resume)(struct macio_dev* dev);
131 int (*shutdown)(struct macio_dev* dev);
132
133 struct device_driver driver;
134};
135#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
136
137extern int macio_register_driver(struct macio_driver *);
138extern void macio_unregister_driver(struct macio_driver *);
139
140#endif /* __MACIO_ASIC_H__ */
diff --git a/include/asm-ppc/mediabay.h b/include/asm-ppc/mediabay.h
deleted file mode 100644
index 9daa3252d7b6..000000000000
--- a/include/asm-ppc/mediabay.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * mediabay.h: definitions for using the media bay
3 * on PowerBook 3400 and similar computers.
4 *
5 * Copyright (C) 1997 Paul Mackerras.
6 */
7#ifndef _PPC_MEDIABAY_H
8#define _PPC_MEDIABAY_H
9
10#ifdef __KERNEL__
11
12#define MB_FD 0 /* media bay contains floppy drive (automatic eject ?) */
13#define MB_FD1 1 /* media bay contains floppy drive (manual eject ?) */
14#define MB_SOUND 2 /* sound device ? */
15#define MB_CD 3 /* media bay contains ATA drive such as CD or ZIP */
16#define MB_PCI 5 /* media bay contains a PCI device */
17#define MB_POWER 6 /* media bay contains a Power device (???) */
18#define MB_NO 7 /* media bay contains nothing */
19
20int check_media_bay(struct device_node *which_bay, int what);
21int check_media_bay_by_base(unsigned long base, int what);
22
23/* Number of bays in the machine or 0 */
24extern int media_bay_count;
25
26/* called by pmac-ide.c to register IDE controller for media bay */
27extern int media_bay_set_ide_infos(struct device_node* which_bay,
28 unsigned long base, int irq, int index);
29
30#endif /* __KERNEL__ */
31#endif /* _PPC_MEDIABAY_H */
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index afe26ffc2e2d..4f152cca13c1 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -164,13 +164,11 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
164 struct task_struct *tsk) 164 struct task_struct *tsk)
165{ 165{
166#ifdef CONFIG_ALTIVEC 166#ifdef CONFIG_ALTIVEC
167 asm volatile ( 167 if (cpu_has_feature(CPU_FTR_ALTIVEC))
168 BEGIN_FTR_SECTION 168 asm volatile ("dssall;\n"
169 "dssall;\n"
170#ifndef CONFIG_POWER4 169#ifndef CONFIG_POWER4
171 "sync;\n" /* G4 needs a sync here, G5 apparently not */ 170 "sync;\n" /* G4 needs a sync here, G5 apparently not */
172#endif 171#endif
173 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
174 : : ); 172 : : );
175#endif /* CONFIG_ALTIVEC */ 173#endif /* CONFIG_ALTIVEC */
176 174
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
index 9694eca16e92..321452695039 100644
--- a/include/asm-ppc/mpc8260.h
+++ b/include/asm-ppc/mpc8260.h
@@ -92,6 +92,10 @@ enum ppc_sys_devices {
92extern unsigned char __res[]; 92extern unsigned char __res[];
93#endif 93#endif
94 94
95#ifndef BOARD_CHIP_NAME
96#define BOARD_CHIP_NAME ""
97#endif
98
95#endif /* CONFIG_8260 */ 99#endif /* CONFIG_8260 */
96#endif /* !__ASM_PPC_MPC8260_H__ */ 100#endif /* !__ASM_PPC_MPC8260_H__ */
97#endif /* __KERNEL__ */ 101#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 516984ee14b5..d98db980cd49 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -67,6 +67,8 @@ extern unsigned char __res[];
67#define MPC85xx_DMA3_SIZE (0x00080) 67#define MPC85xx_DMA3_SIZE (0x00080)
68#define MPC85xx_ENET1_OFFSET (0x24000) 68#define MPC85xx_ENET1_OFFSET (0x24000)
69#define MPC85xx_ENET1_SIZE (0x01000) 69#define MPC85xx_ENET1_SIZE (0x01000)
70#define MPC85xx_MIIM_OFFSET (0x24520)
71#define MPC85xx_MIIM_SIZE (0x00018)
70#define MPC85xx_ENET2_OFFSET (0x25000) 72#define MPC85xx_ENET2_OFFSET (0x25000)
71#define MPC85xx_ENET2_SIZE (0x01000) 73#define MPC85xx_ENET2_SIZE (0x01000)
72#define MPC85xx_ENET3_OFFSET (0x26000) 74#define MPC85xx_ENET3_OFFSET (0x26000)
@@ -132,6 +134,7 @@ enum ppc_sys_devices {
132 MPC85xx_eTSEC3, 134 MPC85xx_eTSEC3,
133 MPC85xx_eTSEC4, 135 MPC85xx_eTSEC4,
134 MPC85xx_IIC2, 136 MPC85xx_IIC2,
137 MPC85xx_MDIO,
135}; 138};
136 139
137/* Internal interrupts are all Level Sensitive, and Positive Polarity */ 140/* Internal interrupts are all Level Sensitive, and Positive Polarity */
diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h
index 208a2e11daee..46f159cf589e 100644
--- a/include/asm-ppc/mpc8xx.h
+++ b/include/asm-ppc/mpc8xx.h
@@ -113,6 +113,10 @@ enum ppc_sys_devices {
113 MPC8xx_CPM_USB, 113 MPC8xx_CPM_USB,
114}; 114};
115 115
116#ifndef BOARD_CHIP_NAME
117#define BOARD_CHIP_NAME ""
118#endif
119
116#endif /* !__ASSEMBLY__ */ 120#endif /* !__ASSEMBLY__ */
117#endif /* CONFIG_8xx */ 121#endif /* CONFIG_8xx */
118#endif /* __CONFIG_8xx_DEFS */ 122#endif /* __CONFIG_8xx_DEFS */
diff --git a/include/asm-ppc/of_device.h b/include/asm-ppc/of_device.h
deleted file mode 100644
index 575bce418f80..000000000000
--- a/include/asm-ppc/of_device.h
+++ /dev/null
@@ -1,65 +0,0 @@
1#ifndef __OF_DEVICE_H__
2#define __OF_DEVICE_H__
3
4#include <linux/device.h>
5#include <linux/mod_devicetable.h>
6#include <asm/prom.h>
7
8/*
9 * The of_platform_bus_type is a bus type used by drivers that do not
10 * attach to a macio or similar bus but still use OF probing
11 * mecanism
12 */
13extern struct bus_type of_platform_bus_type;
14
15/*
16 * The of_device is a kind of "base class" that is a superset of
17 * struct device for use by devices attached to an OF node and
18 * probed using OF properties
19 */
20struct of_device
21{
22 struct device_node *node; /* OF device node */
23 u64 dma_mask; /* DMA mask */
24 struct device dev; /* Generic device interface */
25};
26#define to_of_device(d) container_of(d, struct of_device, dev)
27
28extern const struct of_device_id *of_match_device(
29 const struct of_device_id *matches, const struct of_device *dev);
30
31extern struct of_device *of_dev_get(struct of_device *dev);
32extern void of_dev_put(struct of_device *dev);
33
34/*
35 * An of_platform_driver driver is attached to a basic of_device on
36 * the "platform bus" (of_platform_bus_type)
37 */
38struct of_platform_driver
39{
40 char *name;
41 struct of_device_id *match_table;
42 struct module *owner;
43
44 int (*probe)(struct of_device* dev, const struct of_device_id *match);
45 int (*remove)(struct of_device* dev);
46
47 int (*suspend)(struct of_device* dev, pm_message_t state);
48 int (*resume)(struct of_device* dev);
49 int (*shutdown)(struct of_device* dev);
50
51 struct device_driver driver;
52};
53#define to_of_platform_driver(drv) container_of(drv,struct of_platform_driver, driver)
54
55extern int of_register_driver(struct of_platform_driver *drv);
56extern void of_unregister_driver(struct of_platform_driver *drv);
57extern int of_device_register(struct of_device *ofdev);
58extern void of_device_unregister(struct of_device *ofdev);
59extern struct of_device *of_platform_device_create(struct device_node *np,
60 const char *bus_id,
61 struct device *parent);
62extern void of_release_dev(struct device *dev);
63
64#endif /* __OF_DEVICE_H__ */
65
diff --git a/include/asm-ppc/ohare.h b/include/asm-ppc/ohare.h
deleted file mode 100644
index 023b59772231..000000000000
--- a/include/asm-ppc/ohare.h
+++ /dev/null
@@ -1,48 +0,0 @@
1/*
2 * ohare.h: definitions for using the "O'Hare" I/O controller chip.
3 *
4 * Copyright (C) 1997 Paul Mackerras.
5 *
6 * BenH: Changed to match those of heathrow (but not all of them). Please
7 * check if I didn't break anything (especially the media bay).
8 */
9
10/* offset from ohare base for feature control register */
11#define OHARE_MBCR 0x34
12#define OHARE_FCR 0x38
13
14/*
15 * Bits in feature control register.
16 * These were mostly derived by experiment on a powerbook 3400
17 * and may differ for other machines.
18 */
19#define OH_SCC_RESET 1
20#define OH_BAY_POWER_N 2 /* a guess */
21#define OH_BAY_PCI_ENABLE 4 /* a guess */
22#define OH_BAY_IDE_ENABLE 8
23#define OH_BAY_FLOPPY_ENABLE 0x10
24#define OH_IDE0_ENABLE 0x20
25#define OH_IDE0_RESET_N 0x40 /* a guess */
26#define OH_BAY_DEV_MASK 0x1c
27#define OH_BAY_RESET_N 0x80
28#define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */
29#define OH_SCC_ENABLE 0x200
30#define OH_MESH_ENABLE 0x400
31#define OH_FLOPPY_ENABLE 0x800
32#define OH_SCCA_IO 0x4000
33#define OH_SCCB_IO 0x8000
34#define OH_VIA_ENABLE 0x10000 /* Is apparently wrong, to be verified */
35#define OH_IDE1_RESET_N 0x800000
36
37/*
38 * Bits to set in the feature control register on PowerBooks.
39 */
40#define PBOOK_FEATURES (OH_IDE_ENABLE | OH_SCC_ENABLE | \
41 OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
42
43/*
44 * A magic value to put into the feature control register of the
45 * "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
46 * Contributed by Harry Eaton.
47 */
48#define STARMAX_FEATURES 0xbeff7a
diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h
index 7848aa610c05..ec2f46629ca2 100644
--- a/include/asm-ppc/open_pic.h
+++ b/include/asm-ppc/open_pic.h
@@ -58,8 +58,7 @@ extern int openpic_get_irq(struct pt_regs *regs);
58extern void openpic_reset_processor_phys(u_int cpumask); 58extern void openpic_reset_processor_phys(u_int cpumask);
59extern void openpic_setup_ISU(int isu_num, unsigned long addr); 59extern void openpic_setup_ISU(int isu_num, unsigned long addr);
60extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask); 60extern void openpic_cause_IPI(u_int ipi, cpumask_t cpumask);
61extern void smp_openpic_message_pass(int target, int msg, unsigned long data, 61extern void smp_openpic_message_pass(int target, int msg);
62 int wait);
63extern void openpic_set_k2_cascade(int irq); 62extern void openpic_set_k2_cascade(int irq);
64extern void openpic_set_priority(u_int pri); 63extern void openpic_set_priority(u_int pri);
65extern u_int openpic_get_priority(void); 64extern u_int openpic_get_priority(void);
diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h
index 4789dc024240..fc44f7ca62d7 100644
--- a/include/asm-ppc/page.h
+++ b/include/asm-ppc/page.h
@@ -34,6 +34,17 @@ typedef unsigned long pte_basic_t;
34#define PTE_FMT "%.8lx" 34#define PTE_FMT "%.8lx"
35#endif 35#endif
36 36
37/* align addr on a size boundary - adjust address up/down if needed */
38#define _ALIGN_UP(addr,size) (((addr)+((size)-1))&(~((size)-1)))
39#define _ALIGN_DOWN(addr,size) ((addr)&(~((size)-1)))
40
41/* align addr on a size boundary - adjust address up if needed */
42#define _ALIGN(addr,size) _ALIGN_UP(addr,size)
43
44/* to align the pointer to the (next) page boundary */
45#define PAGE_ALIGN(addr) _ALIGN(addr, PAGE_SIZE)
46
47
37#undef STRICT_MM_TYPECHECKS 48#undef STRICT_MM_TYPECHECKS
38 49
39#ifdef STRICT_MM_TYPECHECKS 50#ifdef STRICT_MM_TYPECHECKS
@@ -76,13 +87,6 @@ typedef unsigned long pgprot_t;
76 87
77#endif 88#endif
78 89
79
80/* align addr on a size boundary - adjust address up if needed -- Cort */
81#define _ALIGN(addr,size) (((addr)+(size)-1)&(~((size)-1)))
82
83/* to align the pointer to the (next) page boundary */
84#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK)
85
86struct page; 90struct page;
87extern void clear_pages(void *page, int order); 91extern void clear_pages(void *page, int order);
88static inline void clear_page(void *page) { clear_pages(page, 0); } 92static inline void clear_page(void *page) { clear_pages(page, 0); }
diff --git a/include/asm-ppc/parport.h b/include/asm-ppc/parport.h
deleted file mode 100644
index 11f96d3de5b6..000000000000
--- a/include/asm-ppc/parport.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * parport.h: platform-specific PC-style parport initialisation
3 *
4 * Copyright (C) 1999, 2000 Tim Waugh <tim@cyberelk.demon.co.uk>
5 *
6 * This file should only be included by drivers/parport/parport_pc.c.
7 */
8
9#ifndef _ASM_PPC_PARPORT_H
10#define _ASM_PPC_PARPORT_H
11
12static int __devinit parport_pc_find_isa_ports (int autoirq, int autodma);
13static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
14{
15 return parport_pc_find_isa_ports (autoirq, autodma);
16}
17
18#endif /* !(_ASM_PPC_PARPORT_H) */
diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h
index ffa423456c2b..e58c78f90a5a 100644
--- a/include/asm-ppc/pci-bridge.h
+++ b/include/asm-ppc/pci-bridge.h
@@ -79,6 +79,11 @@ struct pci_controller {
79 struct resource mem_space; 79 struct resource mem_space;
80}; 80};
81 81
82static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
83{
84 return bus->sysdata;
85}
86
82/* These are used for config access before all the PCI probing 87/* These are used for config access before all the PCI probing
83 has been done. */ 88 has been done. */
84int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, 89int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index 9dd06cd40096..61434edbad7b 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -24,9 +24,9 @@ struct pci_dev;
24 * Set this to 1 if you want the kernel to re-assign all PCI 24 * Set this to 1 if you want the kernel to re-assign all PCI
25 * bus numbers 25 * bus numbers
26 */ 26 */
27extern int pci_assign_all_busses; 27extern int pci_assign_all_buses;
28 28
29#define pcibios_assign_all_busses() (pci_assign_all_busses) 29#define pcibios_assign_all_busses() (pci_assign_all_buses)
30#define pcibios_scan_all_fns(a, b) 0 30#define pcibios_scan_all_fns(a, b) 0
31 31
32#define PCIBIOS_MIN_IO 0x1000 32#define PCIBIOS_MIN_IO 0x1000
@@ -126,7 +126,7 @@ extern void pcibios_add_platform_entries(struct pci_dev *dev);
126 126
127struct file; 127struct file;
128extern pgprot_t pci_phys_mem_access_prot(struct file *file, 128extern pgprot_t pci_phys_mem_access_prot(struct file *file,
129 unsigned long offset, 129 unsigned long pfn,
130 unsigned long size, 130 unsigned long size,
131 pgprot_t prot); 131 pgprot_t prot);
132 132
diff --git a/include/asm-ppc/perfmon.h b/include/asm-ppc/perfmon.h
deleted file mode 100644
index 5e7a89c47b5b..000000000000
--- a/include/asm-ppc/perfmon.h
+++ /dev/null
@@ -1,22 +0,0 @@
1#ifndef __PERFMON_H
2#define __PERFMON_H
3
4extern void (*perf_irq)(struct pt_regs *);
5
6int request_perfmon_irq(void (*handler)(struct pt_regs *));
7void free_perfmon_irq(void);
8
9#ifdef CONFIG_FSL_BOOKE
10void init_pmc_stop(int ctr);
11void set_pmc_event(int ctr, int event);
12void set_pmc_user_kernel(int ctr, int user, int kernel);
13void set_pmc_marked(int ctr, int mark0, int mark1);
14void pmc_start_ctr(int ctr, int enable);
15void pmc_start_ctrs(int enable);
16void pmc_stop_ctrs(void);
17void dump_pmcs(void);
18
19extern struct op_ppc32_model op_model_fsl_booke;
20#endif
21
22#endif /* __PERFMON_H */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index eee601bb9ada..b28a713ba862 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -705,7 +705,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
705#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED)) 705#define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
706 706
707struct file; 707struct file;
708extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long addr, 708extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
709 unsigned long size, pgprot_t vma_prot); 709 unsigned long size, pgprot_t vma_prot);
710#define __HAVE_PHYS_MEM_ACCESS_PROT 710#define __HAVE_PHYS_MEM_ACCESS_PROT
711 711
diff --git a/include/asm-ppc/pmac_feature.h b/include/asm-ppc/pmac_feature.h
deleted file mode 100644
index e9683bcff19b..000000000000
--- a/include/asm-ppc/pmac_feature.h
+++ /dev/null
@@ -1,380 +0,0 @@
1/*
2 * Definition of platform feature hooks for PowerMacs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Paul Mackerras &
9 * Ben. Herrenschmidt.
10 *
11 *
12 * Note: I removed media-bay details from the feature stuff, I believe it's
13 * not worth it, the media-bay driver can directly use the mac-io
14 * ASIC registers.
15 *
16 * Implementation note: Currently, none of these functions will block.
17 * However, they may internally protect themselves with a spinlock
18 * for way too long. Be prepared for at least some of these to block
19 * in the future.
20 *
21 * Unless specifically defined, the result code is assumed to be an
22 * error when negative, 0 is the default success result. Some functions
23 * may return additional positive result values.
24 *
25 * To keep implementation simple, all feature calls are assumed to have
26 * the prototype parameters (struct device_node* node, int value).
27 * When either is not used, pass 0.
28 */
29
30#ifdef __KERNEL__
31#ifndef __PPC_ASM_PMAC_FEATURE_H
32#define __PPC_ASM_PMAC_FEATURE_H
33
34#include <asm/macio.h>
35#include <asm/machdep.h>
36
37/*
38 * Known Mac motherboard models
39 *
40 * Please, report any error here to benh@kernel.crashing.org, thanks !
41 *
42 * Note that I don't fully maintain this list for Core99 & MacRISC2
43 * and I'm considering removing all NewWorld entries from it and
44 * entirely rely on the model string.
45 */
46
47/* PowerSurge are the first generation of PCI Pmacs. This include
48 * all of the Grand-Central based machines. We currently don't
49 * differenciate most of them.
50 */
51#define PMAC_TYPE_PSURGE 0x10 /* PowerSurge */
52#define PMAC_TYPE_ANS 0x11 /* Apple Network Server */
53
54/* Here is the infamous serie of OHare based machines
55 */
56#define PMAC_TYPE_COMET 0x20 /* Beleived to be PowerBook 2400 */
57#define PMAC_TYPE_HOOPER 0x21 /* Beleived to be PowerBook 3400 */
58#define PMAC_TYPE_KANGA 0x22 /* PowerBook 3500 (first G3) */
59#define PMAC_TYPE_ALCHEMY 0x23 /* Alchemy motherboard base */
60#define PMAC_TYPE_GAZELLE 0x24 /* Spartacus, some 5xxx/6xxx */
61#define PMAC_TYPE_UNKNOWN_OHARE 0x2f /* Unknown, but OHare based */
62
63/* Here are the Heathrow based machines
64 * FIXME: Differenciate wallstreet,mainstreet,wallstreetII
65 */
66#define PMAC_TYPE_GOSSAMER 0x30 /* Gossamer motherboard */
67#define PMAC_TYPE_SILK 0x31 /* Desktop PowerMac G3 */
68#define PMAC_TYPE_WALLSTREET 0x32 /* Wallstreet/Mainstreet PowerBook*/
69#define PMAC_TYPE_UNKNOWN_HEATHROW 0x3f /* Unknown but heathrow based */
70
71/* Here are newworld machines based on Paddington (heathrow derivative)
72 */
73#define PMAC_TYPE_101_PBOOK 0x40 /* 101 PowerBook (aka Lombard) */
74#define PMAC_TYPE_ORIG_IMAC 0x41 /* First generation iMac */
75#define PMAC_TYPE_YOSEMITE 0x42 /* B&W G3 */
76#define PMAC_TYPE_YIKES 0x43 /* Yikes G4 (PCI graphics) */
77#define PMAC_TYPE_UNKNOWN_PADDINGTON 0x4f /* Unknown but paddington based */
78
79/* Core99 machines based on UniNorth 1.0 and 1.5
80 *
81 * Note: A single entry here may cover several actual models according
82 * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most
83 * FireWire based iMacs, etc...). Those machines are too similar to be
84 * distinguished here, when they need to be differencied, use the
85 * device-tree "model" or "compatible" property.
86 */
87#define PMAC_TYPE_ORIG_IBOOK 0x40 /* First iBook model (no firewire) */
88#define PMAC_TYPE_SAWTOOTH 0x41 /* Desktop G4s */
89#define PMAC_TYPE_FW_IMAC 0x42 /* FireWire iMacs (except Pangea based) */
90#define PMAC_TYPE_FW_IBOOK 0x43 /* FireWire iBooks (except iBook2) */
91#define PMAC_TYPE_CUBE 0x44 /* Cube PowerMac */
92#define PMAC_TYPE_QUICKSILVER 0x45 /* QuickSilver G4s */
93#define PMAC_TYPE_PISMO 0x46 /* Pismo PowerBook */
94#define PMAC_TYPE_TITANIUM 0x47 /* Titanium PowerBook */
95#define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook (no L3, M6) */
96#define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3 & M7) */
97#define PMAC_TYPE_TITANIUM4 0x50 /* Titanium IV PowerBook (with L3 & M9) */
98#define PMAC_TYPE_EMAC 0x50 /* eMac */
99#define PMAC_TYPE_UNKNOWN_CORE99 0x5f
100
101/* MacRisc2 with UniNorth 2.0 */
102#define PMAC_TYPE_RACKMAC 0x80 /* XServe */
103#define PMAC_TYPE_WINDTUNNEL 0x81
104
105/* MacRISC2 machines based on the Pangea chipset
106 */
107#define PMAC_TYPE_PANGEA_IMAC 0x100 /* Flower Power iMac */
108#define PMAC_TYPE_IBOOK2 0x101 /* iBook2 (polycarbonate) */
109#define PMAC_TYPE_FLAT_PANEL_IMAC 0x102 /* Flat panel iMac */
110#define PMAC_TYPE_UNKNOWN_PANGEA 0x10f
111
112/* MacRISC2 machines based on the Intrepid chipset
113 */
114#define PMAC_TYPE_UNKNOWN_INTREPID 0x11f /* Generic */
115
116/* MacRISC4 / G5 machines. We don't have per-machine selection here anymore,
117 * but rather machine families
118 */
119#define PMAC_TYPE_POWERMAC_G5 0x150 /* U3 & U3H based */
120#define PMAC_TYPE_POWERMAC_G5_U3L 0x151 /* U3L based desktop */
121#define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */
122#define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */
123#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */
124
125/*
126 * Motherboard flags
127 */
128
129#define PMAC_MB_CAN_SLEEP 0x00000001
130#define PMAC_MB_HAS_FW_POWER 0x00000002
131#define PMAC_MB_OLD_CORE99 0x00000004
132#define PMAC_MB_MOBILE 0x00000008
133#define PMAC_MB_MAY_SLEEP 0x00000010
134
135/*
136 * Feature calls supported on pmac
137 *
138 */
139
140/*
141 * Use this inline wrapper
142 */
143struct device_node;
144
145static inline long pmac_call_feature(int selector, struct device_node* node,
146 long param, long value)
147{
148 if (!ppc_md.feature_call)
149 return -ENODEV;
150 return ppc_md.feature_call(selector, node, param, value);
151}
152
153/* PMAC_FTR_SERIAL_ENABLE (struct device_node* node, int param, int value)
154 * enable/disable an SCC side. Pass the node corresponding to the
155 * channel side as a parameter.
156 * param is the type of port
157 * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled
158 * for use by xmon.
159 */
160#define PMAC_FTR_SCC_ENABLE PMAC_FTR_DEF(0)
161 #define PMAC_SCC_ASYNC 0
162 #define PMAC_SCC_IRDA 1
163 #define PMAC_SCC_I2S1 2
164 #define PMAC_SCC_FLAG_XMON 0x00001000
165
166/* PMAC_FTR_MODEM_ENABLE (struct device_node* node, 0, int value)
167 * enable/disable the internal modem.
168 */
169#define PMAC_FTR_MODEM_ENABLE PMAC_FTR_DEF(1)
170
171/* PMAC_FTR_SWIM3_ENABLE (struct device_node* node, 0,int value)
172 * enable/disable the swim3 (floppy) cell of a mac-io ASIC
173 */
174#define PMAC_FTR_SWIM3_ENABLE PMAC_FTR_DEF(2)
175
176/* PMAC_FTR_MESH_ENABLE (struct device_node* node, 0, int value)
177 * enable/disable the mesh (scsi) cell of a mac-io ASIC
178 */
179#define PMAC_FTR_MESH_ENABLE PMAC_FTR_DEF(3)
180
181/* PMAC_FTR_IDE_ENABLE (struct device_node* node, int busID, int value)
182 * enable/disable an IDE port of a mac-io ASIC
183 * pass the busID parameter
184 */
185#define PMAC_FTR_IDE_ENABLE PMAC_FTR_DEF(4)
186
187/* PMAC_FTR_IDE_RESET (struct device_node* node, int busID, int value)
188 * assert(1)/release(0) an IDE reset line (mac-io IDE only)
189 */
190#define PMAC_FTR_IDE_RESET PMAC_FTR_DEF(5)
191
192/* PMAC_FTR_BMAC_ENABLE (struct device_node* node, 0, int value)
193 * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
194 * it's reset line
195 */
196#define PMAC_FTR_BMAC_ENABLE PMAC_FTR_DEF(6)
197
198/* PMAC_FTR_GMAC_ENABLE (struct device_node* node, 0, int value)
199 * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This
200 * control the cell's clock.
201 */
202#define PMAC_FTR_GMAC_ENABLE PMAC_FTR_DEF(7)
203
204/* PMAC_FTR_GMAC_PHY_RESET (struct device_node* node, 0, 0)
205 * Perform a HW reset of the PHY connected to a gmac controller.
206 * Pass the gmac device node, not the PHY node.
207 */
208#define PMAC_FTR_GMAC_PHY_RESET PMAC_FTR_DEF(8)
209
210/* PMAC_FTR_SOUND_CHIP_ENABLE (struct device_node* node, 0, int value)
211 * enable/disable the sound chip, whatever it is and provided it can
212 * acually be controlled
213 */
214#define PMAC_FTR_SOUND_CHIP_ENABLE PMAC_FTR_DEF(9)
215
216/* -- add various tweaks related to sound routing -- */
217
218/* PMAC_FTR_AIRPORT_ENABLE (struct device_node* node, 0, int value)
219 * enable/disable the airport card
220 */
221#define PMAC_FTR_AIRPORT_ENABLE PMAC_FTR_DEF(10)
222
223/* PMAC_FTR_RESET_CPU (NULL, int cpu_nr, 0)
224 * toggle the reset line of a CPU on an uninorth-based SMP machine
225 */
226#define PMAC_FTR_RESET_CPU PMAC_FTR_DEF(11)
227
228/* PMAC_FTR_USB_ENABLE (struct device_node* node, 0, int value)
229 * enable/disable an USB cell, along with the power of the USB "pad"
230 * on keylargo based machines
231 */
232#define PMAC_FTR_USB_ENABLE PMAC_FTR_DEF(12)
233
234/* PMAC_FTR_1394_ENABLE (struct device_node* node, 0, int value)
235 * enable/disable the firewire cell of an uninorth ASIC.
236 */
237#define PMAC_FTR_1394_ENABLE PMAC_FTR_DEF(13)
238
239/* PMAC_FTR_1394_CABLE_POWER (struct device_node* node, 0, int value)
240 * enable/disable the firewire cable power supply of the uninorth
241 * firewire cell
242 */
243#define PMAC_FTR_1394_CABLE_POWER PMAC_FTR_DEF(14)
244
245/* PMAC_FTR_SLEEP_STATE (struct device_node* node, 0, int value)
246 * set the sleep state of the motherboard.
247 *
248 * Pass -1 as value to query for sleep capability
249 * Pass 1 to set IOs to sleep
250 * Pass 0 to set IOs to wake
251 */
252#define PMAC_FTR_SLEEP_STATE PMAC_FTR_DEF(15)
253
254/* PMAC_FTR_GET_MB_INFO (NULL, selector, 0)
255 *
256 * returns some motherboard infos.
257 * selector: 0 - model id
258 * 1 - model flags (capabilities)
259 * 2 - model name (cast to const char *)
260 */
261#define PMAC_FTR_GET_MB_INFO PMAC_FTR_DEF(16)
262#define PMAC_MB_INFO_MODEL 0
263#define PMAC_MB_INFO_FLAGS 1
264#define PMAC_MB_INFO_NAME 2
265
266/* PMAC_FTR_READ_GPIO (NULL, int index, 0)
267 *
268 * read a GPIO from a mac-io controller of type KeyLargo or Pangea.
269 * the value returned is a byte (positive), or a negative error code
270 */
271#define PMAC_FTR_READ_GPIO PMAC_FTR_DEF(17)
272
273/* PMAC_FTR_WRITE_GPIO (NULL, int index, int value)
274 *
275 * write a GPIO of a mac-io controller of type KeyLargo or Pangea.
276 */
277#define PMAC_FTR_WRITE_GPIO PMAC_FTR_DEF(18)
278
279/* PMAC_FTR_ENABLE_MPIC
280 *
281 * Enable the MPIC cell
282 */
283#define PMAC_FTR_ENABLE_MPIC PMAC_FTR_DEF(19)
284
285/* PMAC_FTR_AACK_DELAY_ENABLE (NULL, int enable, 0)
286 *
287 * Enable/disable the AACK delay on the northbridge for systems using DFS
288 */
289#define PMAC_FTR_AACK_DELAY_ENABLE PMAC_FTR_DEF(20)
290
291/* PMAC_FTR_DEVICE_CAN_WAKE
292 *
293 * Used by video drivers to inform system that they can actually perform
294 * wakeup from sleep
295 */
296#define PMAC_FTR_DEVICE_CAN_WAKE PMAC_FTR_DEF(22)
297
298
299/* Don't use those directly, they are for the sake of pmac_setup.c */
300extern long pmac_do_feature_call(unsigned int selector, ...);
301extern void pmac_feature_init(void);
302
303/* Video suspend tweak */
304extern void pmac_set_early_video_resume(void (*proc)(void *data), void *data);
305extern void pmac_call_early_video_resume(void);
306
307#define PMAC_FTR_DEF(x) ((_MACH_Pmac << 16) | (x))
308
309/* The AGP driver registers itself here */
310extern void pmac_register_agp_pm(struct pci_dev *bridge,
311 int (*suspend)(struct pci_dev *bridge),
312 int (*resume)(struct pci_dev *bridge));
313
314/* Those are meant to be used by video drivers to deal with AGP
315 * suspend resume properly
316 */
317extern void pmac_suspend_agp_for_card(struct pci_dev *dev);
318extern void pmac_resume_agp_for_card(struct pci_dev *dev);
319
320/* Used by the via-pmu driver for suspend/resume
321 */
322extern void pmac_tweak_clock_spreading(int enable);
323
324/*
325 * The part below is for use by macio_asic.c only, do not rely
326 * on the data structures or constants below in a normal driver
327 *
328 */
329
330#define MAX_MACIO_CHIPS 2
331
332enum {
333 macio_unknown = 0,
334 macio_grand_central,
335 macio_ohare,
336 macio_ohareII,
337 macio_heathrow,
338 macio_gatwick,
339 macio_paddington,
340 macio_keylargo,
341 macio_pangea,
342 macio_intrepid,
343 macio_keylargo2,
344};
345
346struct macio_chip
347{
348 struct device_node *of_node;
349 int type;
350 const char *name;
351 int rev;
352 volatile u32 __iomem *base;
353 unsigned long flags;
354
355 /* For use by macio_asic PCI driver */
356 struct macio_bus lbus;
357};
358
359extern struct macio_chip macio_chips[MAX_MACIO_CHIPS];
360
361#define MACIO_FLAG_SCCA_ON 0x00000001
362#define MACIO_FLAG_SCCB_ON 0x00000002
363#define MACIO_FLAG_SCC_LOCKED 0x00000004
364#define MACIO_FLAG_AIRPORT_ON 0x00000010
365#define MACIO_FLAG_FW_SUPPORTED 0x00000020
366
367extern struct macio_chip* macio_find(struct device_node* child, int type);
368
369#define MACIO_FCR32(macio, r) ((macio)->base + ((r) >> 2))
370#define MACIO_FCR8(macio, r) (((volatile u8 __iomem *)((macio)->base)) + (r))
371
372#define MACIO_IN32(r) (in_le32(MACIO_FCR32(macio,r)))
373#define MACIO_OUT32(r,v) (out_le32(MACIO_FCR32(macio,r), (v)))
374#define MACIO_BIS(r,v) (MACIO_OUT32((r), MACIO_IN32(r) | (v)))
375#define MACIO_BIC(r,v) (MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
376#define MACIO_IN8(r) (in_8(MACIO_FCR8(macio,r)))
377#define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v)))
378
379#endif /* __PPC_ASM_PMAC_FEATURE_H */
380#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pmac_low_i2c.h b/include/asm-ppc/pmac_low_i2c.h
deleted file mode 100644
index 809a5963d5e7..000000000000
--- a/include/asm-ppc/pmac_low_i2c.h
+++ /dev/null
@@ -1,43 +0,0 @@
1/*
2 * include/asm-ppc/pmac_low_i2c.h
3 *
4 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12#ifndef __PMAC_LOW_I2C_H__
13#define __PMAC_LOW_I2C_H__
14
15/* i2c mode (based on the platform functions format) */
16enum {
17 pmac_low_i2c_mode_dumb = 1,
18 pmac_low_i2c_mode_std = 2,
19 pmac_low_i2c_mode_stdsub = 3,
20 pmac_low_i2c_mode_combined = 4,
21};
22
23/* RW bit in address */
24enum {
25 pmac_low_i2c_read = 0x01,
26 pmac_low_i2c_write = 0x00
27};
28
29/* Init, called early during boot */
30extern void pmac_init_low_i2c(void);
31
32/* Locking functions exposed to i2c-keywest */
33int pmac_low_i2c_lock(struct device_node *np);
34int pmac_low_i2c_unlock(struct device_node *np);
35
36/* Access functions for platform code */
37int pmac_low_i2c_open(struct device_node *np, int channel);
38int pmac_low_i2c_close(struct device_node *np);
39int pmac_low_i2c_setmode(struct device_node *np, int mode);
40int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len);
41
42
43#endif /* __PMAC_LOW_I2C_H__ */
diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h
deleted file mode 100644
index a14a82abe8d2..000000000000
--- a/include/asm-ppc/posix_types.h
+++ /dev/null
@@ -1,111 +0,0 @@
1#ifndef _PPC_POSIX_TYPES_H
2#define _PPC_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_ino_t;
11typedef unsigned int __kernel_mode_t;
12typedef unsigned short __kernel_nlink_t;
13typedef long __kernel_off_t;
14typedef int __kernel_pid_t;
15typedef unsigned int __kernel_uid_t;
16typedef unsigned int __kernel_gid_t;
17typedef unsigned int __kernel_size_t;
18typedef int __kernel_ssize_t;
19typedef long __kernel_ptrdiff_t;
20typedef long __kernel_time_t;
21typedef long __kernel_suseconds_t;
22typedef long __kernel_clock_t;
23typedef int __kernel_timer_t;
24typedef int __kernel_clockid_t;
25typedef int __kernel_daddr_t;
26typedef char * __kernel_caddr_t;
27typedef short __kernel_ipc_pid_t;
28typedef unsigned short __kernel_uid16_t;
29typedef unsigned short __kernel_gid16_t;
30typedef unsigned int __kernel_uid32_t;
31typedef unsigned int __kernel_gid32_t;
32
33typedef unsigned int __kernel_old_uid_t;
34typedef unsigned int __kernel_old_gid_t;
35typedef unsigned int __kernel_old_dev_t;
36
37#ifdef __GNUC__
38typedef long long __kernel_loff_t;
39#endif
40
41typedef struct {
42 int val[2];
43} __kernel_fsid_t;
44
45#ifndef __GNUC__
46
47#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
48#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
49#define __FD_ISSET(d, set) ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
50#define __FD_ZERO(set) \
51 ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
52
53#else /* __GNUC__ */
54
55#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
56 || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
57/* With GNU C, use inline functions instead so args are evaluated only once: */
58
59#undef __FD_SET
60static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
61{
62 unsigned long _tmp = fd / __NFDBITS;
63 unsigned long _rem = fd % __NFDBITS;
64 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
65}
66
67#undef __FD_CLR
68static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
69{
70 unsigned long _tmp = fd / __NFDBITS;
71 unsigned long _rem = fd % __NFDBITS;
72 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
73}
74
75#undef __FD_ISSET
76static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
77{
78 unsigned long _tmp = fd / __NFDBITS;
79 unsigned long _rem = fd % __NFDBITS;
80 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
81}
82
83/*
84 * This will unroll the loop for the normal constant case (8 ints,
85 * for a 256-bit fd_set)
86 */
87#undef __FD_ZERO
88static __inline__ void __FD_ZERO(__kernel_fd_set *p)
89{
90 unsigned int *tmp = (unsigned int *)p->fds_bits;
91 int i;
92
93 if (__builtin_constant_p(__FDSET_LONGS)) {
94 switch (__FDSET_LONGS) {
95 case 8:
96 tmp[0] = 0; tmp[1] = 0; tmp[2] = 0; tmp[3] = 0;
97 tmp[4] = 0; tmp[5] = 0; tmp[6] = 0; tmp[7] = 0;
98 return;
99 }
100 }
101 i = __FDSET_LONGS;
102 while (i) {
103 i--;
104 *tmp = 0;
105 tmp++;
106 }
107}
108
109#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
110#endif /* __GNUC__ */
111#endif /* _PPC_POSIX_TYPES_H */
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
deleted file mode 100644
index bb53e2def363..000000000000
--- a/include/asm-ppc/ppc_asm.h
+++ /dev/null
@@ -1,350 +0,0 @@
1/*
2 * include/asm-ppc/ppc_asm.h
3 *
4 * Definitions used by various bits of low-level assembly code on PowerPC.
5 *
6 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#include <linux/config.h>
15
16/*
17 * Macros for storing registers into and loading registers from
18 * exception frames.
19 */
20#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
21#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
22#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
23#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
24#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
25#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
26#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
27#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
28#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
29#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
30
31#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
32 SAVE_10GPRS(22, base)
33#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
34 REST_10GPRS(22, base)
35
36#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
37#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
38#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
39#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
40#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
41#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
42#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
43#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
44#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
45#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
46#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
47#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
48
49#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
50#define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
51#define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base)
52#define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base)
53#define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base)
54#define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base)
55#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
56#define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
57#define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base)
58#define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base)
59#define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base)
60#define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base)
61
62#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
63#define SAVE_2EVR(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
64#define SAVE_4EVR(n,s,base) SAVE_2EVR(n,s,base); SAVE_2EVR(n+2,s,base)
65#define SAVE_8EVR(n,s,base) SAVE_4EVR(n,s,base); SAVE_4EVR(n+4,s,base)
66#define SAVE_16EVR(n,s,base) SAVE_8EVR(n,s,base); SAVE_8EVR(n+8,s,base)
67#define SAVE_32EVR(n,s,base) SAVE_16EVR(n,s,base); SAVE_16EVR(n+16,s,base)
68
69#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
70#define REST_2EVR(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
71#define REST_4EVR(n,s,base) REST_2EVR(n,s,base); REST_2EVR(n+2,s,base)
72#define REST_8EVR(n,s,base) REST_4EVR(n,s,base); REST_4EVR(n+4,s,base)
73#define REST_16EVR(n,s,base) REST_8EVR(n,s,base); REST_8EVR(n+8,s,base)
74#define REST_32EVR(n,s,base) REST_16EVR(n,s,base); REST_16EVR(n+16,s,base)
75
76#ifdef CONFIG_PPC601_SYNC_FIX
77#define SYNC \
78BEGIN_FTR_SECTION \
79 sync; \
80 isync; \
81END_FTR_SECTION_IFSET(CPU_FTR_601)
82#define SYNC_601 \
83BEGIN_FTR_SECTION \
84 sync; \
85END_FTR_SECTION_IFSET(CPU_FTR_601)
86#define ISYNC_601 \
87BEGIN_FTR_SECTION \
88 isync; \
89END_FTR_SECTION_IFSET(CPU_FTR_601)
90#else
91#define SYNC
92#define SYNC_601
93#define ISYNC_601
94#endif
95
96#ifndef CONFIG_SMP
97#define TLBSYNC
98#else /* CONFIG_SMP */
99/* tlbsync is not implemented on 601 */
100#define TLBSYNC \
101BEGIN_FTR_SECTION \
102 tlbsync; \
103 sync; \
104END_FTR_SECTION_IFCLR(CPU_FTR_601)
105#endif
106
107/*
108 * This instruction is not implemented on the PPC 603 or 601; however, on
109 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
110 * All of these instructions exist in the 8xx, they have magical powers,
111 * and they must be used.
112 */
113
114#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
115#define tlbia \
116 li r4,1024; \
117 mtctr r4; \
118 lis r4,KERNELBASE@h; \
1190: tlbie r4; \
120 addi r4,r4,0x1000; \
121 bdnz 0b
122#endif
123
124#ifdef CONFIG_BOOKE
125#define tophys(rd,rs) \
126 addis rd,rs,0
127
128#define tovirt(rd,rs) \
129 addis rd,rs,0
130
131#else /* CONFIG_BOOKE */
132/*
133 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
134 * physical base address of RAM at compile time.
135 */
136#define tophys(rd,rs) \
1370: addis rd,rs,-KERNELBASE@h; \
138 .section ".vtop_fixup","aw"; \
139 .align 1; \
140 .long 0b; \
141 .previous
142
143#define tovirt(rd,rs) \
1440: addis rd,rs,KERNELBASE@h; \
145 .section ".ptov_fixup","aw"; \
146 .align 1; \
147 .long 0b; \
148 .previous
149#endif /* CONFIG_BOOKE */
150
151/*
152 * On 64-bit cpus, we use the rfid instruction instead of rfi, but
153 * we then have to make sure we preserve the top 32 bits except for
154 * the 64-bit mode bit, which we clear.
155 */
156#ifdef CONFIG_PPC64BRIDGE
157#define FIX_SRR1(ra, rb) \
158 mr rb,ra; \
159 mfmsr ra; \
160 clrldi ra,ra,1; /* turn off 64-bit mode */ \
161 rldimi ra,rb,0,32
162#define RFI .long 0x4c000024 /* rfid instruction */
163#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
164#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
165
166#else
167#define FIX_SRR1(ra, rb)
168#ifndef CONFIG_40x
169#define RFI rfi
170#else
171#define RFI rfi; b . /* Prevent prefetch past rfi */
172#endif
173#define MTMSRD(r) mtmsr r
174#define CLR_TOP32(r)
175#endif /* CONFIG_PPC64BRIDGE */
176
177#define RFCI .long 0x4c000066 /* rfci instruction */
178#define RFDI .long 0x4c00004e /* rfdi instruction */
179#define RFMCI .long 0x4c00004c /* rfmci instruction */
180
181#ifdef CONFIG_IBM405_ERR77
182#define PPC405_ERR77(ra,rb) dcbt ra, rb;
183#define PPC405_ERR77_SYNC sync;
184#else
185#define PPC405_ERR77(ra,rb)
186#define PPC405_ERR77_SYNC
187#endif
188
189#ifdef CONFIG_IBM440EP_ERR42
190#define PPC440EP_ERR42 isync
191#else
192#define PPC440EP_ERR42
193#endif
194
195/* The boring bits... */
196
197/* Condition Register Bit Fields */
198
199#define cr0 0
200#define cr1 1
201#define cr2 2
202#define cr3 3
203#define cr4 4
204#define cr5 5
205#define cr6 6
206#define cr7 7
207
208
209/* General Purpose Registers (GPRs) */
210
211#define r0 0
212#define r1 1
213#define r2 2
214#define r3 3
215#define r4 4
216#define r5 5
217#define r6 6
218#define r7 7
219#define r8 8
220#define r9 9
221#define r10 10
222#define r11 11
223#define r12 12
224#define r13 13
225#define r14 14
226#define r15 15
227#define r16 16
228#define r17 17
229#define r18 18
230#define r19 19
231#define r20 20
232#define r21 21
233#define r22 22
234#define r23 23
235#define r24 24
236#define r25 25
237#define r26 26
238#define r27 27
239#define r28 28
240#define r29 29
241#define r30 30
242#define r31 31
243
244
245/* Floating Point Registers (FPRs) */
246
247#define fr0 0
248#define fr1 1
249#define fr2 2
250#define fr3 3
251#define fr4 4
252#define fr5 5
253#define fr6 6
254#define fr7 7
255#define fr8 8
256#define fr9 9
257#define fr10 10
258#define fr11 11
259#define fr12 12
260#define fr13 13
261#define fr14 14
262#define fr15 15
263#define fr16 16
264#define fr17 17
265#define fr18 18
266#define fr19 19
267#define fr20 20
268#define fr21 21
269#define fr22 22
270#define fr23 23
271#define fr24 24
272#define fr25 25
273#define fr26 26
274#define fr27 27
275#define fr28 28
276#define fr29 29
277#define fr30 30
278#define fr31 31
279
280#define vr0 0
281#define vr1 1
282#define vr2 2
283#define vr3 3
284#define vr4 4
285#define vr5 5
286#define vr6 6
287#define vr7 7
288#define vr8 8
289#define vr9 9
290#define vr10 10
291#define vr11 11
292#define vr12 12
293#define vr13 13
294#define vr14 14
295#define vr15 15
296#define vr16 16
297#define vr17 17
298#define vr18 18
299#define vr19 19
300#define vr20 20
301#define vr21 21
302#define vr22 22
303#define vr23 23
304#define vr24 24
305#define vr25 25
306#define vr26 26
307#define vr27 27
308#define vr28 28
309#define vr29 29
310#define vr30 30
311#define vr31 31
312
313#define evr0 0
314#define evr1 1
315#define evr2 2
316#define evr3 3
317#define evr4 4
318#define evr5 5
319#define evr6 6
320#define evr7 7
321#define evr8 8
322#define evr9 9
323#define evr10 10
324#define evr11 11
325#define evr12 12
326#define evr13 13
327#define evr14 14
328#define evr15 15
329#define evr16 16
330#define evr17 17
331#define evr18 18
332#define evr19 19
333#define evr20 20
334#define evr21 21
335#define evr22 22
336#define evr23 23
337#define evr24 24
338#define evr25 25
339#define evr26 26
340#define evr27 27
341#define evr28 28
342#define evr29 29
343#define evr30 30
344#define evr31 31
345
346/* some stab codes */
347#define N_FUN 36
348#define N_RSYM 64
349#define N_SLINE 68
350#define N_SO 100
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
deleted file mode 100644
index b05b5d9cae20..000000000000
--- a/include/asm-ppc/processor.h
+++ /dev/null
@@ -1,201 +0,0 @@
1#ifdef __KERNEL__
2#ifndef __ASM_PPC_PROCESSOR_H
3#define __ASM_PPC_PROCESSOR_H
4
5/*
6 * Default implementation of macro that returns current
7 * instruction pointer ("program counter").
8 */
9#define current_text_addr() ({ __label__ _l; _l: &&_l;})
10
11#include <linux/config.h>
12#include <linux/stringify.h>
13
14#include <asm/ptrace.h>
15#include <asm/types.h>
16#include <asm/mpc8xx.h>
17#include <asm/reg.h>
18
19/* We only need to define a new _MACH_xxx for machines which are part of
20 * a configuration which supports more than one type of different machine.
21 * This is currently limited to CONFIG_PPC_MULTIPLATFORM and CHRP/PReP/PMac.
22 * -- Tom
23 */
24#define _MACH_prep 0x00000001
25#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */
26#define _MACH_chrp 0x00000004 /* chrp machine */
27
28/* see residual.h for these */
29#define _PREP_Motorola 0x01 /* motorola prep */
30#define _PREP_Firm 0x02 /* firmworks prep */
31#define _PREP_IBM 0x00 /* ibm prep */
32#define _PREP_Bull 0x03 /* bull prep */
33
34/* these are arbitrary */
35#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
36#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
37#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
38
39#define _GLOBAL(n)\
40 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
41 .globl n;\
42n:
43
44/*
45 * this is the minimum allowable io space due to the location
46 * of the io areas on prep (first one at 0x80000000) but
47 * as soon as I get around to remapping the io areas with the BATs
48 * to match the mac we can raise this. -- Cort
49 */
50#define TASK_SIZE (CONFIG_TASK_SIZE)
51
52#ifndef __ASSEMBLY__
53#ifdef CONFIG_PPC_MULTIPLATFORM
54extern int _machine;
55
56/* what kind of prep workstation we are */
57extern int _prep_type;
58extern int _chrp_type;
59
60/*
61 * This is used to identify the board type from a given PReP board
62 * vendor. Board revision is also made available.
63 */
64extern unsigned char ucSystemType;
65extern unsigned char ucBoardRev;
66extern unsigned char ucBoardRevMaj, ucBoardRevMin;
67#else
68#define _machine 0
69#endif /* CONFIG_PPC_MULTIPLATFORM */
70
71struct task_struct;
72void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
73void release_thread(struct task_struct *);
74
75/* Prepare to copy thread state - unlazy all lazy status */
76extern void prepare_to_copy(struct task_struct *tsk);
77
78/*
79 * Create a new kernel thread.
80 */
81extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
82
83/* Lazy FPU handling on uni-processor */
84extern struct task_struct *last_task_used_math;
85extern struct task_struct *last_task_used_altivec;
86extern struct task_struct *last_task_used_spe;
87
88/* This decides where the kernel will search for a free chunk of vm
89 * space during mmap's.
90 */
91#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
92
93typedef struct {
94 unsigned long seg;
95} mm_segment_t;
96
97struct thread_struct {
98 unsigned long ksp; /* Kernel stack pointer */
99 struct pt_regs *regs; /* Pointer to saved register state */
100 mm_segment_t fs; /* for get_fs() validation */
101 void *pgdir; /* root of page-table tree */
102 int fpexc_mode; /* floating-point exception mode */
103 signed long last_syscall;
104#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
105 unsigned long dbcr0; /* debug control register values */
106 unsigned long dbcr1;
107#endif
108 double fpr[32]; /* Complete floating point set */
109 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
110 unsigned long fpscr; /* Floating point status */
111#ifdef CONFIG_ALTIVEC
112 /* Complete AltiVec register set */
113 vector128 vr[32] __attribute((aligned(16)));
114 /* AltiVec status */
115 vector128 vscr __attribute((aligned(16)));
116 unsigned long vrsave;
117 int used_vr; /* set if process has used altivec */
118#endif /* CONFIG_ALTIVEC */
119#ifdef CONFIG_SPE
120 unsigned long evr[32]; /* upper 32-bits of SPE regs */
121 u64 acc; /* Accumulator */
122 unsigned long spefscr; /* SPE & eFP status */
123 int used_spe; /* set if process has used spe */
124#endif /* CONFIG_SPE */
125};
126
127#define ARCH_MIN_TASKALIGN 16
128
129#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
130
131#define INIT_THREAD { \
132 .ksp = INIT_SP, \
133 .fs = KERNEL_DS, \
134 .pgdir = swapper_pg_dir, \
135 .fpexc_mode = MSR_FE0 | MSR_FE1, \
136}
137
138/*
139 * Return saved PC of a blocked thread. For now, this is the "user" PC
140 */
141#define thread_saved_pc(tsk) \
142 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
143
144unsigned long get_wchan(struct task_struct *p);
145
146#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
147#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
148
149/* Get/set floating-point exception mode */
150#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
151#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
152
153extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
154extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
155
156static inline unsigned int __unpack_fe01(unsigned int msr_bits)
157{
158 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
159}
160
161static inline unsigned int __pack_fe01(unsigned int fpmode)
162{
163 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
164}
165
166/* in process.c - for early bootup debug -- Cort */
167int ll_printk(const char *, ...);
168void ll_puts(const char *);
169
170/* In misc.c */
171void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
172
173#define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac)
174
175#define cpu_relax() barrier()
176
177/*
178 * Prefetch macros.
179 */
180#define ARCH_HAS_PREFETCH
181#define ARCH_HAS_PREFETCHW
182#define ARCH_HAS_SPINLOCK_PREFETCH
183
184extern inline void prefetch(const void *x)
185{
186 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
187}
188
189extern inline void prefetchw(const void *x)
190{
191 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
192}
193
194#define spin_lock_prefetch(x) prefetchw(x)
195
196extern int emulate_altivec(struct pt_regs *regs);
197
198#endif /* !__ASSEMBLY__ */
199
200#endif /* __ASM_PPC_PROCESSOR_H */
201#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h
index 7043c164b537..c34fb4e37a97 100644
--- a/include/asm-ppc/ptrace.h
+++ b/include/asm-ppc/ptrace.h
@@ -57,7 +57,7 @@ extern unsigned long profile_pc(struct pt_regs *regs);
57 57
58#define force_successful_syscall_return() \ 58#define force_successful_syscall_return() \
59 do { \ 59 do { \
60 current_thread_info()->local_flags |= _TIFL_FORCE_NOERROR; \ 60 current_thread_info()->syscall_noerror = 1; \
61 } while(0) 61 } while(0)
62 62
63/* 63/*
diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
deleted file mode 100644
index 73c33e3ef9c6..000000000000
--- a/include/asm-ppc/reg.h
+++ /dev/null
@@ -1,440 +0,0 @@
1/*
2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
7 */
8
9#ifdef __KERNEL__
10#ifndef __ASM_PPC_REGS_H__
11#define __ASM_PPC_REGS_H__
12
13#include <linux/stringify.h>
14
15/* Pickup Book E specific registers. */
16#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
17#include <asm/reg_booke.h>
18#endif
19
20/* Machine State Register (MSR) Fields */
21#define MSR_SF (1<<63)
22#define MSR_ISF (1<<61)
23#define MSR_VEC (1<<25) /* Enable AltiVec */
24#define MSR_POW (1<<18) /* Enable Power Management */
25#define MSR_WE (1<<18) /* Wait State Enable */
26#define MSR_TGPR (1<<17) /* TLB Update registers in use */
27#define MSR_CE (1<<17) /* Critical Interrupt Enable */
28#define MSR_ILE (1<<16) /* Interrupt Little Endian */
29#define MSR_EE (1<<15) /* External Interrupt Enable */
30#define MSR_PR (1<<14) /* Problem State / Privilege Level */
31#define MSR_FP (1<<13) /* Floating Point enable */
32#define MSR_ME (1<<12) /* Machine Check Enable */
33#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
34#define MSR_SE (1<<10) /* Single Step */
35#define MSR_BE (1<<9) /* Branch Trace */
36#define MSR_DE (1<<9) /* Debug Exception Enable */
37#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
38#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
39#define MSR_IR (1<<5) /* Instruction Relocate */
40#define MSR_DR (1<<4) /* Data Relocate */
41#define MSR_PE (1<<3) /* Protection Enable */
42#define MSR_PX (1<<2) /* Protection Exclusive Mode */
43#define MSR_RI (1<<1) /* Recoverable Exception */
44#define MSR_LE (1<<0) /* Little Endian */
45
46/* Default MSR for kernel mode. */
47#ifdef CONFIG_APUS_FAST_EXCEPT
48#define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR)
49#endif
50
51#ifndef MSR_KERNEL
52#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
53#endif
54
55#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
56
57/* Floating Point Status and Control Register (FPSCR) Fields */
58#define FPSCR_FX 0x80000000 /* FPU exception summary */
59#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
60#define FPSCR_VX 0x20000000 /* Invalid operation summary */
61#define FPSCR_OX 0x10000000 /* Overflow exception summary */
62#define FPSCR_UX 0x08000000 /* Underflow exception summary */
63#define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
64#define FPSCR_XX 0x02000000 /* Inexact exception summary */
65#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
66#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
67#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
68#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
69#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
70#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
71#define FPSCR_FR 0x00040000 /* Fraction rounded */
72#define FPSCR_FI 0x00020000 /* Fraction inexact */
73#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
74#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
75#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
76#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
77#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
78#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
79#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
80#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
81#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
82#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
83#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
84#define FPSCR_RN 0x00000003 /* FPU rounding control */
85
86/* Special Purpose Registers (SPRNs)*/
87#define SPRN_CTR 0x009 /* Count Register */
88#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
89#define SPRN_DAR 0x013 /* Data Address Register */
90#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
91#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
92#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
93#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
94#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
95#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
96#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
97#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
98#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
99#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
100#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
101#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
102#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
103#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
104#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
105#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
106#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
107#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
108#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
109#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
110#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
111
112#define SPRN_DEC 0x016 /* Decrement Register */
113#define SPRN_DER 0x095 /* Debug Enable Regsiter */
114#define DER_RSTE 0x40000000 /* Reset Interrupt */
115#define DER_CHSTPE 0x20000000 /* Check Stop */
116#define DER_MCIE 0x10000000 /* Machine Check Interrupt */
117#define DER_EXTIE 0x02000000 /* External Interrupt */
118#define DER_ALIE 0x01000000 /* Alignment Interrupt */
119#define DER_PRIE 0x00800000 /* Program Interrupt */
120#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
121#define DER_DECIE 0x00200000 /* Decrementer Interrupt */
122#define DER_SYSIE 0x00040000 /* System Call Interrupt */
123#define DER_TRE 0x00020000 /* Trace Interrupt */
124#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
125#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
126#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
127#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
128#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
129#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
130#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
131#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
132#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
133#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
134#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
135#define SPRN_EAR 0x11A /* External Address Register */
136#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
137#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
138#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
139#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
140#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
141#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
142#define HID0_SBCLK (1<<27)
143#define HID0_EICE (1<<26)
144#define HID0_TBEN (1<<26) /* Timebase enable - 745x */
145#define HID0_ECLK (1<<25)
146#define HID0_PAR (1<<24)
147#define HID0_STEN (1<<24) /* Software table search enable - 745x */
148#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
149#define HID0_DOZE (1<<23)
150#define HID0_NAP (1<<22)
151#define HID0_SLEEP (1<<21)
152#define HID0_DPM (1<<20)
153#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
154#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
155#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
156#define HID0_ICE (1<<15) /* Instruction Cache Enable */
157#define HID0_DCE (1<<14) /* Data Cache Enable */
158#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
159#define HID0_DLOCK (1<<12) /* Data Cache Lock */
160#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
161#define HID0_DCI (1<<10) /* Data Cache Invalidate */
162#define HID0_SPD (1<<9) /* Speculative disable */
163#define HID0_DAPUEN (1<<8) /* Debug APU enable */
164#define HID0_SGE (1<<7) /* Store Gathering Enable */
165#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
166#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
167#define HID0_LRSTK (1<<4) /* Link register stack - 745x */
168#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
169#define HID0_ABE (1<<3) /* Address Broadcast Enable */
170#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
171#define HID0_BHTE (1<<2) /* Branch History Table Enable */
172#define HID0_BTCD (1<<1) /* Branch target cache disable */
173#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
174#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
175
176#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
177#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
178#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
179#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
180#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
181#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
182#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
183#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
184#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
185#define HID1_PS (1<<16) /* 750FX PLL selection */
186#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
187#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
188#define SPRN_HID4 0x3F4 /* 970 HID4 */
189#define SPRN_HID5 0x3F6 /* 970 HID5 */
190#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
191#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
192#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
193#endif
194#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
195#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
196#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
197#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
198#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
199#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
200#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
201#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
202#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
203#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
204#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
205#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
206#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
207#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
208#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
209#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
210#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
211#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
212#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
213#define ICTRL_EICE 0x08000000 /* enable icache parity errs */
214#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
215#define ICTRL_EICP 0x00000100 /* enable icache par. check */
216#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
217#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
218#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
219#define SPRN_L2CR2 0x3f8
220#define L2CR_L2E 0x80000000 /* L2 enable */
221#define L2CR_L2PE 0x40000000 /* L2 parity enable */
222#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
223#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
224#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
225#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
226#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
227#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
228#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
229#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
230#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
231#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
232#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
233#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
234#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
235#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
236#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
237#define L2CR_L2DO 0x00400000 /* L2 data only */
238#define L2CR_L2I 0x00200000 /* L2 global invalidate */
239#define L2CR_L2CTL 0x00100000 /* L2 RAM control */
240#define L2CR_L2WT 0x00080000 /* L2 write-through */
241#define L2CR_L2TS 0x00040000 /* L2 test support */
242#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
243#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
244#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
245#define L2CR_L2SL 0x00008000 /* L2 DLL slow */
246#define L2CR_L2DF 0x00004000 /* L2 differential clock */
247#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
248#define L2CR_L2IP 0x00000001 /* L2 GI in progress */
249#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
250#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
251#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
252#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
253#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */
254#define L3CR_L3E 0x80000000 /* L3 enable */
255#define L3CR_L3PE 0x40000000 /* L3 data parity enable */
256#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
257#define L3CR_L3SIZ 0x10000000 /* L3 size */
258#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
259#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
260#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
261#define L3CR_L3IO 0x00400000 /* L3 instruction only */
262#define L3CR_L3SPO 0x00040000 /* L3 sample point override */
263#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
264#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
265#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
266#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
267#define L3CR_L3I 0x00000400 /* L3 global invalidate */
268#define L3CR_L3RT 0x00000300 /* L3 SRAM type */
269#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
270#define L3CR_L3DO 0x00000040 /* L3 data only mode */
271#define L3CR_PMEN 0x00000004 /* L3 private memory enable */
272#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
273#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
274#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
275#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
276#define SPRN_LDSTDB 0x3f4 /* */
277#define SPRN_LR 0x008 /* Link Register */
278#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
279#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
280#ifndef SPRN_PIR
281#define SPRN_PIR 0x3FF /* Processor Identification Register */
282#endif
283#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
284#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
285#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
286#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
287#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
288#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
289#define SPRN_PVR 0x11F /* Processor Version Register */
290#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
291#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
292#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
293#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
294#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
295#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
296#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
297#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
298#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
299#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
300#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
301#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
302#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
303#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
304#ifndef SPRN_SVR
305#define SPRN_SVR 0x11E /* System Version Register */
306#endif
307#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
308/* these bits were defined in inverted endian sense originally, ugh, confusing */
309#define THRM1_TIN (1 << 31)
310#define THRM1_TIV (1 << 30)
311#define THRM1_THRES(x) ((x&0x7f)<<23)
312#define THRM3_SITV(x) ((x&0x3fff)<<1)
313#define THRM1_TID (1<<2)
314#define THRM1_TIE (1<<1)
315#define THRM1_V (1<<0)
316#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
317#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
318#define THRM3_E (1<<0)
319#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
320#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
321#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
322#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
323#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
324#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
325#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
326#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
327#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
328#define SPRN_XER 0x001 /* Fixed Point Exception Register */
329
330/* Bit definitions for MMCR0 and PMC1 / PMC2. */
331#define MMCR0_PMC1_CYCLES (1 << 7)
332#define MMCR0_PMC1_ICACHEMISS (5 << 7)
333#define MMCR0_PMC1_DTLB (6 << 7)
334#define MMCR0_PMC2_DCACHEMISS 0x6
335#define MMCR0_PMC2_CYCLES 0x1
336#define MMCR0_PMC2_ITLB 0x7
337#define MMCR0_PMC2_LOADMISSTIME 0x5
338#define MMCR0_PMXE (1 << 26)
339
340/* Processor Version Register */
341
342/* Processor Version Register (PVR) field extraction */
343
344#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
345#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
346
347/*
348 * IBM has further subdivided the standard PowerPC 16-bit version and
349 * revision subfields of the PVR for the PowerPC 403s into the following:
350 */
351
352#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
353#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
354#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
355#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
356#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
357#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
358
359/* Processor Version Numbers */
360
361#define PVR_403GA 0x00200000
362#define PVR_403GB 0x00200100
363#define PVR_403GC 0x00200200
364#define PVR_403GCX 0x00201400
365#define PVR_405GP 0x40110000
366#define PVR_STB03XXX 0x40310000
367#define PVR_NP405H 0x41410000
368#define PVR_NP405L 0x41610000
369#define PVR_601 0x00010000
370#define PVR_602 0x00050000
371#define PVR_603 0x00030000
372#define PVR_603e 0x00060000
373#define PVR_603ev 0x00070000
374#define PVR_603r 0x00071000
375#define PVR_604 0x00040000
376#define PVR_604e 0x00090000
377#define PVR_604r 0x000A0000
378#define PVR_620 0x00140000
379#define PVR_740 0x00080000
380#define PVR_750 PVR_740
381#define PVR_740P 0x10080000
382#define PVR_750P PVR_740P
383#define PVR_7400 0x000C0000
384#define PVR_7410 0x800C0000
385#define PVR_7450 0x80000000
386#define PVR_8540 0x80200000
387#define PVR_8560 0x80200000
388/*
389 * For the 8xx processors, all of them report the same PVR family for
390 * the PowerPC core. The various versions of these processors must be
391 * differentiated by the version number in the Communication Processor
392 * Module (CPM).
393 */
394#define PVR_821 0x00500000
395#define PVR_823 PVR_821
396#define PVR_850 PVR_821
397#define PVR_860 PVR_821
398#define PVR_8240 0x00810100
399#define PVR_8245 0x80811014
400#define PVR_8260 PVR_8240
401
402#if 0
403/* Segment Registers */
404#define SR0 0
405#define SR1 1
406#define SR2 2
407#define SR3 3
408#define SR4 4
409#define SR5 5
410#define SR6 6
411#define SR7 7
412#define SR8 8
413#define SR9 9
414#define SR10 10
415#define SR11 11
416#define SR12 12
417#define SR13 13
418#define SR14 14
419#define SR15 15
420#endif
421
422/* Macros for setting and retrieving special purpose registers */
423#ifndef __ASSEMBLY__
424#define mfmsr() ({unsigned int rval; \
425 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
426#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
427
428#define mfspr(rn) ({unsigned int rval; \
429 asm volatile("mfspr %0," __stringify(rn) \
430 : "=r" (rval)); rval;})
431#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
432
433#define mfsrin(v) ({unsigned int rval; \
434 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
435 rval;})
436
437#define proc_trap() asm volatile("trap")
438#endif /* __ASSEMBLY__ */
439#endif /* __ASM_PPC_REGS_H__ */
440#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/rwsem.h b/include/asm-ppc/rwsem.h
deleted file mode 100644
index 3501ea72f88c..000000000000
--- a/include/asm-ppc/rwsem.h
+++ /dev/null
@@ -1,177 +0,0 @@
1/*
2 * include/asm-ppc/rwsem.h: R/W semaphores for PPC using the stuff
3 * in lib/rwsem.c. Adapted largely from include/asm-i386/rwsem.h
4 * by Paul Mackerras <paulus@samba.org>.
5 */
6
7#ifndef _PPC_RWSEM_H
8#define _PPC_RWSEM_H
9
10#ifdef __KERNEL__
11#include <linux/list.h>
12#include <linux/spinlock.h>
13#include <asm/atomic.h>
14#include <asm/system.h>
15
16/*
17 * the semaphore definition
18 */
19struct rw_semaphore {
20 /* XXX this should be able to be an atomic_t -- paulus */
21 signed long count;
22#define RWSEM_UNLOCKED_VALUE 0x00000000
23#define RWSEM_ACTIVE_BIAS 0x00000001
24#define RWSEM_ACTIVE_MASK 0x0000ffff
25#define RWSEM_WAITING_BIAS (-0x00010000)
26#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
27#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
28 spinlock_t wait_lock;
29 struct list_head wait_list;
30#if RWSEM_DEBUG
31 int debug;
32#endif
33};
34
35/*
36 * initialisation
37 */
38#if RWSEM_DEBUG
39#define __RWSEM_DEBUG_INIT , 0
40#else
41#define __RWSEM_DEBUG_INIT /* */
42#endif
43
44#define __RWSEM_INITIALIZER(name) \
45 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
46 LIST_HEAD_INIT((name).wait_list) \
47 __RWSEM_DEBUG_INIT }
48
49#define DECLARE_RWSEM(name) \
50 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
51
52extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
53extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
54extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
55extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
56
57static inline void init_rwsem(struct rw_semaphore *sem)
58{
59 sem->count = RWSEM_UNLOCKED_VALUE;
60 spin_lock_init(&sem->wait_lock);
61 INIT_LIST_HEAD(&sem->wait_list);
62#if RWSEM_DEBUG
63 sem->debug = 0;
64#endif
65}
66
67/*
68 * lock for reading
69 */
70static inline void __down_read(struct rw_semaphore *sem)
71{
72 if (atomic_inc_return((atomic_t *)(&sem->count)) > 0)
73 smp_wmb();
74 else
75 rwsem_down_read_failed(sem);
76}
77
78static inline int __down_read_trylock(struct rw_semaphore *sem)
79{
80 int tmp;
81
82 while ((tmp = sem->count) >= 0) {
83 if (tmp == cmpxchg(&sem->count, tmp,
84 tmp + RWSEM_ACTIVE_READ_BIAS)) {
85 smp_wmb();
86 return 1;
87 }
88 }
89 return 0;
90}
91
92/*
93 * lock for writing
94 */
95static inline void __down_write(struct rw_semaphore *sem)
96{
97 int tmp;
98
99 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
100 (atomic_t *)(&sem->count));
101 if (tmp == RWSEM_ACTIVE_WRITE_BIAS)
102 smp_wmb();
103 else
104 rwsem_down_write_failed(sem);
105}
106
107static inline int __down_write_trylock(struct rw_semaphore *sem)
108{
109 int tmp;
110
111 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
112 RWSEM_ACTIVE_WRITE_BIAS);
113 smp_wmb();
114 return tmp == RWSEM_UNLOCKED_VALUE;
115}
116
117/*
118 * unlock after reading
119 */
120static inline void __up_read(struct rw_semaphore *sem)
121{
122 int tmp;
123
124 smp_wmb();
125 tmp = atomic_dec_return((atomic_t *)(&sem->count));
126 if (tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0)
127 rwsem_wake(sem);
128}
129
130/*
131 * unlock after writing
132 */
133static inline void __up_write(struct rw_semaphore *sem)
134{
135 smp_wmb();
136 if (atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
137 (atomic_t *)(&sem->count)) < 0)
138 rwsem_wake(sem);
139}
140
141/*
142 * implement atomic add functionality
143 */
144static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
145{
146 atomic_add(delta, (atomic_t *)(&sem->count));
147}
148
149/*
150 * downgrade write lock to read lock
151 */
152static inline void __downgrade_write(struct rw_semaphore *sem)
153{
154 int tmp;
155
156 smp_wmb();
157 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
158 if (tmp < 0)
159 rwsem_downgrade_wake(sem);
160}
161
162/*
163 * implement exchange and add functionality
164 */
165static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
166{
167 smp_mb();
168 return atomic_add_return(delta, (atomic_t *)(&sem->count));
169}
170
171static inline int rwsem_is_locked(struct rw_semaphore *sem)
172{
173 return (sem->count != 0);
174}
175
176#endif /* __KERNEL__ */
177#endif /* _PPC_RWSEM_XADD_H */
diff --git a/include/asm-ppc/scatterlist.h b/include/asm-ppc/scatterlist.h
deleted file mode 100644
index f21f18f56548..000000000000
--- a/include/asm-ppc/scatterlist.h
+++ /dev/null
@@ -1,25 +0,0 @@
1#ifdef __KERNEL__
2#ifndef _PPC_SCATTERLIST_H
3#define _PPC_SCATTERLIST_H
4
5#include <asm/dma.h>
6
7struct scatterlist {
8 struct page *page;
9 unsigned int offset;
10 dma_addr_t dma_address;
11 unsigned int length;
12};
13
14/*
15 * These macros should be used after a pci_map_sg call has been done
16 * to get bus addresses of each of the SG entries and their lengths.
17 * You should only work with the number of sg entries pci_map_sg
18 * returns, or alternatively stop on the first sg_dma_len(sg) which
19 * is 0.
20 */
21#define sg_dma_address(sg) ((sg)->dma_address)
22#define sg_dma_len(sg) ((sg)->length)
23
24#endif /* !(_PPC_SCATTERLIST_H) */
25#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/seccomp.h b/include/asm-ppc/seccomp.h
deleted file mode 100644
index 666c4da96d87..000000000000
--- a/include/asm-ppc/seccomp.h
+++ /dev/null
@@ -1,10 +0,0 @@
1#ifndef _ASM_SECCOMP_H
2
3#include <linux/unistd.h>
4
5#define __NR_seccomp_read __NR_read
6#define __NR_seccomp_write __NR_write
7#define __NR_seccomp_exit __NR_exit
8#define __NR_seccomp_sigreturn __NR_rt_sigreturn
9
10#endif /* _ASM_SECCOMP_H */
diff --git a/include/asm-ppc/sections.h b/include/asm-ppc/sections.h
deleted file mode 100644
index ba8f43ac9bf3..000000000000
--- a/include/asm-ppc/sections.h
+++ /dev/null
@@ -1,33 +0,0 @@
1#ifdef __KERNEL__
2#ifndef _PPC_SECTIONS_H
3#define _PPC_SECTIONS_H
4
5#include <asm-generic/sections.h>
6
7#define __pmac __attribute__ ((__section__ (".pmac.text")))
8#define __pmacdata __attribute__ ((__section__ (".pmac.data")))
9#define __pmacfunc(__argpmac) \
10 __argpmac __pmac; \
11 __argpmac
12
13#define __prep __attribute__ ((__section__ (".prep.text")))
14#define __prepdata __attribute__ ((__section__ (".prep.data")))
15#define __prepfunc(__argprep) \
16 __argprep __prep; \
17 __argprep
18
19#define __chrp __attribute__ ((__section__ (".chrp.text")))
20#define __chrpdata __attribute__ ((__section__ (".chrp.data")))
21#define __chrpfunc(__argchrp) \
22 __argchrp __chrp; \
23 __argchrp
24
25/* this is actually just common chrp/pmac code, not OF code -- Cort */
26#define __openfirmware __attribute__ ((__section__ (".openfirmware.text")))
27#define __openfirmwaredata __attribute__ ((__section__ (".openfirmware.data")))
28#define __openfirmwarefunc(__argopenfirmware) \
29 __argopenfirmware __openfirmware; \
30 __argopenfirmware
31
32#endif /* _PPC_SECTIONS_H */
33#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/semaphore.h b/include/asm-ppc/semaphore.h
deleted file mode 100644
index 89e6e73be08c..000000000000
--- a/include/asm-ppc/semaphore.h
+++ /dev/null
@@ -1,111 +0,0 @@
1#ifndef _PPC_SEMAPHORE_H
2#define _PPC_SEMAPHORE_H
3
4/*
5 * Swiped from asm-sparc/semaphore.h and modified
6 * -- Cort (cort@cs.nmt.edu)
7 *
8 * Stole some rw spinlock-based semaphore stuff from asm-alpha/semaphore.h
9 * -- Ani Joshi (ajoshi@unixbox.com)
10 *
11 * Remove spinlock-based RW semaphores; RW semaphore definitions are
12 * now in rwsem.h and we use the generic lib/rwsem.c implementation.
13 * Rework semaphores to use atomic_dec_if_positive.
14 * -- Paul Mackerras (paulus@samba.org)
15 */
16
17#ifdef __KERNEL__
18
19#include <asm/atomic.h>
20#include <asm/system.h>
21#include <linux/wait.h>
22#include <linux/rwsem.h>
23
24struct semaphore {
25 /*
26 * Note that any negative value of count is equivalent to 0,
27 * but additionally indicates that some process(es) might be
28 * sleeping on `wait'.
29 */
30 atomic_t count;
31 wait_queue_head_t wait;
32};
33
34#define __SEMAPHORE_INITIALIZER(name, n) \
35{ \
36 .count = ATOMIC_INIT(n), \
37 .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
38}
39
40#define __MUTEX_INITIALIZER(name) \
41 __SEMAPHORE_INITIALIZER(name, 1)
42
43#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
44 struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
45
46#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1)
47#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0)
48
49static inline void sema_init (struct semaphore *sem, int val)
50{
51 atomic_set(&sem->count, val);
52 init_waitqueue_head(&sem->wait);
53}
54
55static inline void init_MUTEX (struct semaphore *sem)
56{
57 sema_init(sem, 1);
58}
59
60static inline void init_MUTEX_LOCKED (struct semaphore *sem)
61{
62 sema_init(sem, 0);
63}
64
65extern void __down(struct semaphore * sem);
66extern int __down_interruptible(struct semaphore * sem);
67extern void __up(struct semaphore * sem);
68
69extern inline void down(struct semaphore * sem)
70{
71 might_sleep();
72
73 /*
74 * Try to get the semaphore, take the slow path if we fail.
75 */
76 if (atomic_dec_return(&sem->count) < 0)
77 __down(sem);
78 smp_wmb();
79}
80
81extern inline int down_interruptible(struct semaphore * sem)
82{
83 int ret = 0;
84
85 might_sleep();
86
87 if (atomic_dec_return(&sem->count) < 0)
88 ret = __down_interruptible(sem);
89 smp_wmb();
90 return ret;
91}
92
93extern inline int down_trylock(struct semaphore * sem)
94{
95 int ret;
96
97 ret = atomic_dec_if_positive(&sem->count) < 0;
98 smp_wmb();
99 return ret;
100}
101
102extern inline void up(struct semaphore * sem)
103{
104 smp_wmb();
105 if (atomic_inc_return(&sem->count) <= 0)
106 __up(sem);
107}
108
109#endif /* __KERNEL__ */
110
111#endif /* !(_PPC_SEMAPHORE_H) */
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h
index 829481c0a9dc..30e9268a888c 100644
--- a/include/asm-ppc/smp.h
+++ b/include/asm-ppc/smp.h
@@ -35,6 +35,7 @@ extern cpumask_t cpu_possible_map;
35extern unsigned long smp_proc_in_lock[]; 35extern unsigned long smp_proc_in_lock[];
36extern volatile unsigned long cpu_callin_map[]; 36extern volatile unsigned long cpu_callin_map[];
37extern int smp_tb_synchronized; 37extern int smp_tb_synchronized;
38extern struct smp_ops_t *smp_ops;
38 39
39extern void smp_send_tlb_invalidate(int); 40extern void smp_send_tlb_invalidate(int);
40extern void smp_send_xmon_break(int cpu); 41extern void smp_send_xmon_break(int cpu);
@@ -45,32 +46,31 @@ extern int __cpu_disable(void);
45extern void __cpu_die(unsigned int cpu); 46extern void __cpu_die(unsigned int cpu);
46extern void cpu_die(void) __attribute__((noreturn)); 47extern void cpu_die(void) __attribute__((noreturn));
47 48
48#define NO_PROC_ID 0xFF /* No processor magic marker */
49#define PROC_CHANGE_PENALTY 20
50
51#define raw_smp_processor_id() (current_thread_info()->cpu) 49#define raw_smp_processor_id() (current_thread_info()->cpu)
52 50
53extern int __cpu_up(unsigned int cpu); 51extern int __cpu_up(unsigned int cpu);
54 52
55extern int smp_hw_index[]; 53extern int smp_hw_index[];
56#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) 54#define hard_smp_processor_id() (smp_hw_index[smp_processor_id()])
57 55#define get_hard_smp_processor_id(cpu) (smp_hw_index[(cpu)])
58struct klock_info_struct { 56#define set_hard_smp_processor_id(cpu, phys)\
59 unsigned long kernel_flag; 57 (smp_hw_index[(cpu)] = (phys))
60 unsigned char akp; 58
61};
62
63extern struct klock_info_struct klock_info;
64#define KLOCK_HELD 0xffffffff
65#define KLOCK_CLEAR 0x0
66
67#endif /* __ASSEMBLY__ */ 59#endif /* __ASSEMBLY__ */
68 60
69#else /* !(CONFIG_SMP) */ 61#else /* !(CONFIG_SMP) */
70 62
71static inline void cpu_die(void) { } 63static inline void cpu_die(void) { }
64#define get_hard_smp_processor_id(cpu) 0
65#define set_hard_smp_processor_id(cpu, phys)
66#define hard_smp_processor_id() 0
72 67
73#endif /* !(CONFIG_SMP) */ 68#endif /* !(CONFIG_SMP) */
74 69
70#ifndef __ASSEMBLY__
71extern int boot_cpuid;
72extern int boot_cpuid_phys;
73#endif
74
75#endif /* !(_PPC_SMP_H) */ 75#endif /* !(_PPC_SMP_H) */
76#endif /* __KERNEL__ */ 76#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h
index 20edcf2a6e0c..5c64b75f0295 100644
--- a/include/asm-ppc/spinlock.h
+++ b/include/asm-ppc/spinlock.h
@@ -9,7 +9,7 @@
9 * (the type definitions are in asm/raw_spinlock_types.h) 9 * (the type definitions are in asm/raw_spinlock_types.h)
10 */ 10 */
11 11
12#define __raw_spin_is_locked(x) ((x)->lock != 0) 12#define __raw_spin_is_locked(x) ((x)->slock != 0)
13#define __raw_spin_unlock_wait(lock) \ 13#define __raw_spin_unlock_wait(lock) \
14 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0) 14 do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
15#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock) 15#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
@@ -31,17 +31,17 @@ static inline void __raw_spin_lock(raw_spinlock_t *lock)
31 bne- 2b\n\ 31 bne- 2b\n\
32 isync" 32 isync"
33 : "=&r"(tmp) 33 : "=&r"(tmp)
34 : "r"(&lock->lock), "r"(1) 34 : "r"(&lock->slock), "r"(1)
35 : "cr0", "memory"); 35 : "cr0", "memory");
36} 36}
37 37
38static inline void __raw_spin_unlock(raw_spinlock_t *lock) 38static inline void __raw_spin_unlock(raw_spinlock_t *lock)
39{ 39{
40 __asm__ __volatile__("eieio # __raw_spin_unlock": : :"memory"); 40 __asm__ __volatile__("eieio # __raw_spin_unlock": : :"memory");
41 lock->lock = 0; 41 lock->slock = 0;
42} 42}
43 43
44#define __raw_spin_trylock(l) (!test_and_set_bit(0,&(l)->lock)) 44#define __raw_spin_trylock(l) (!test_and_set_bit(0,(volatile unsigned long *)(&(l)->slock)))
45 45
46/* 46/*
47 * Read-write spinlocks, allowing multiple readers 47 * Read-write spinlocks, allowing multiple readers
diff --git a/include/asm-ppc/spinlock_types.h b/include/asm-ppc/spinlock_types.h
deleted file mode 100644
index 7919ccc75b8a..000000000000
--- a/include/asm-ppc/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __ASM_SPINLOCK_TYPES_H
2#define __ASM_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned long lock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile signed int lock;
16} raw_rwlock_t;
17
18#define __RAW_RW_LOCK_UNLOCKED { 0 }
19
20#endif
diff --git a/include/asm-ppc/statfs.h b/include/asm-ppc/statfs.h
deleted file mode 100644
index 807c69954a1b..000000000000
--- a/include/asm-ppc/statfs.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef _PPC_STATFS_H
2#define _PPC_STATFS_H
3
4#include <asm-generic/statfs.h>
5#endif
6
7
8
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h
index d754ab570fe0..bd99cb53a19f 100644
--- a/include/asm-ppc/system.h
+++ b/include/asm-ppc/system.h
@@ -70,25 +70,47 @@ extern void _set_L3CR(unsigned long);
70#endif 70#endif
71extern void via_cuda_init(void); 71extern void via_cuda_init(void);
72extern void pmac_nvram_init(void); 72extern void pmac_nvram_init(void);
73extern void chrp_nvram_init(void);
73extern void read_rtc_time(void); 74extern void read_rtc_time(void);
74extern void pmac_find_display(void); 75extern void pmac_find_display(void);
75extern void giveup_fpu(struct task_struct *); 76extern void giveup_fpu(struct task_struct *);
76extern void enable_kernel_fp(void); 77extern void enable_kernel_fp(void);
78extern void flush_fp_to_thread(struct task_struct *);
77extern void enable_kernel_altivec(void); 79extern void enable_kernel_altivec(void);
78extern void giveup_altivec(struct task_struct *); 80extern void giveup_altivec(struct task_struct *);
79extern void load_up_altivec(struct task_struct *); 81extern void load_up_altivec(struct task_struct *);
82extern int emulate_altivec(struct pt_regs *);
80extern void giveup_spe(struct task_struct *); 83extern void giveup_spe(struct task_struct *);
81extern void load_up_spe(struct task_struct *); 84extern void load_up_spe(struct task_struct *);
82extern int fix_alignment(struct pt_regs *); 85extern int fix_alignment(struct pt_regs *);
83extern void cvt_fd(float *from, double *to, unsigned long *fpscr); 86extern void cvt_fd(float *from, double *to, struct thread_struct *thread);
84extern void cvt_df(double *from, float *to, unsigned long *fpscr); 87extern void cvt_df(double *from, float *to, struct thread_struct *thread);
88
89#ifdef CONFIG_ALTIVEC
90extern void flush_altivec_to_thread(struct task_struct *);
91#else
92static inline void flush_altivec_to_thread(struct task_struct *t)
93{
94}
95#endif
96
97#ifdef CONFIG_SPE
98extern void flush_spe_to_thread(struct task_struct *);
99#else
100static inline void flush_spe_to_thread(struct task_struct *t)
101{
102}
103#endif
104
85extern int call_rtas(const char *, int, int, unsigned long *, ...); 105extern int call_rtas(const char *, int, int, unsigned long *, ...);
86extern void cacheable_memzero(void *p, unsigned int nb); 106extern void cacheable_memzero(void *p, unsigned int nb);
87extern void *cacheable_memcpy(void *, const void *, unsigned int); 107extern void *cacheable_memcpy(void *, const void *, unsigned int);
88extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long); 108extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
89extern void bad_page_fault(struct pt_regs *, unsigned long, int); 109extern void bad_page_fault(struct pt_regs *, unsigned long, int);
90extern void die(const char *, struct pt_regs *, long); 110extern int die(const char *, struct pt_regs *, long);
91extern void _exception(int, struct pt_regs *, int, unsigned long); 111extern void _exception(int, struct pt_regs *, int, unsigned long);
112void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
113
92#ifdef CONFIG_BOOKE_WDT 114#ifdef CONFIG_BOOKE_WDT
93extern u32 booke_wdt_enabled; 115extern u32 booke_wdt_enabled;
94extern u32 booke_wdt_period; 116extern u32 booke_wdt_period;
diff --git a/include/asm-ppc/thread_info.h b/include/asm-ppc/thread_info.h
deleted file mode 100644
index 27903db42efc..000000000000
--- a/include/asm-ppc/thread_info.h
+++ /dev/null
@@ -1,107 +0,0 @@
1/* thread_info.h: PPC low-level thread information
2 * adapted from the i386 version by Paul Mackerras
3 *
4 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
5 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
6 */
7
8#ifndef _ASM_THREAD_INFO_H
9#define _ASM_THREAD_INFO_H
10
11#ifdef __KERNEL__
12#ifndef __ASSEMBLY__
13/*
14 * low level task data.
15 * If you change this, change the TI_* offsets below to match.
16 */
17struct thread_info {
18 struct task_struct *task; /* main task structure */
19 struct exec_domain *exec_domain; /* execution domain */
20 unsigned long flags; /* low level flags */
21 unsigned long local_flags; /* non-racy flags */
22 int cpu; /* cpu we're on */
23 int preempt_count; /* 0 => preemptable,
24 <0 => BUG */
25 struct restart_block restart_block;
26};
27
28#define INIT_THREAD_INFO(tsk) \
29{ \
30 .task = &tsk, \
31 .exec_domain = &default_exec_domain, \
32 .flags = 0, \
33 .local_flags = 0, \
34 .cpu = 0, \
35 .preempt_count = 1, \
36 .restart_block = { \
37 .fn = do_no_restart_syscall, \
38 }, \
39}
40
41#define init_thread_info (init_thread_union.thread_info)
42#define init_stack (init_thread_union.stack)
43
44/*
45 * macros/functions for gaining access to the thread information structure
46 */
47
48/* how to get the thread information struct from C */
49static inline struct thread_info *current_thread_info(void)
50{
51 struct thread_info *ti;
52 __asm__("rlwinm %0,1,0,0,18" : "=r"(ti));
53 return ti;
54}
55
56/* thread information allocation */
57#define alloc_thread_info(tsk) ((struct thread_info *) \
58 __get_free_pages(GFP_KERNEL, 1))
59#define free_thread_info(ti) free_pages((unsigned long) (ti), 1)
60#define get_thread_info(ti) get_task_struct((ti)->task)
61#define put_thread_info(ti) put_task_struct((ti)->task)
62#endif /* __ASSEMBLY__ */
63
64/*
65 * Size of kernel stack for each process.
66 */
67#define THREAD_SIZE 8192 /* 2 pages */
68
69#define PREEMPT_ACTIVE 0x10000000
70
71/*
72 * thread information flag bit numbers
73 */
74#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
75#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
76#define TIF_SIGPENDING 2 /* signal pending */
77#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
78#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling
79 TIF_NEED_RESCHED */
80#define TIF_MEMDIE 5
81#define TIF_SYSCALL_AUDIT 6 /* syscall auditing active */
82#define TIF_SECCOMP 7 /* secure computing */
83
84/* as above, but as bit values */
85#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
86#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
87#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
88#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
89#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
90#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
91#define _TIF_SECCOMP (1<<TIF_SECCOMP)
92
93#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
94
95/*
96 * Non racy (local) flags bit numbers
97 */
98#define TIFL_FORCE_NOERROR 0 /* don't return error from current
99 syscall even if result < 0 */
100
101/* as above, but as bit values */
102#define _TIFL_FORCE_NOERROR (1<<TIFL_FORCE_NOERROR)
103
104
105#endif /* __KERNEL__ */
106
107#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h
deleted file mode 100644
index 77dc24d7d2ad..000000000000
--- a/include/asm-ppc/types.h
+++ /dev/null
@@ -1,69 +0,0 @@
1#ifndef _PPC_TYPES_H
2#define _PPC_TYPES_H
3
4#ifndef __ASSEMBLY__
5
6typedef __signed__ char __s8;
7typedef unsigned char __u8;
8
9typedef __signed__ short __s16;
10typedef unsigned short __u16;
11
12typedef __signed__ int __s32;
13typedef unsigned int __u32;
14
15#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
16typedef __signed__ long long __s64;
17typedef unsigned long long __u64;
18#endif
19
20typedef struct {
21 __u32 u[4];
22} __vector128;
23
24/*
25 * XXX allowed outside of __KERNEL__ for now, until glibc gets
26 * a proper set of asm headers of its own. -- paulus
27 */
28typedef unsigned short umode_t;
29
30#endif /* __ASSEMBLY__ */
31
32#ifdef __KERNEL__
33/*
34 * These aren't exported outside the kernel to avoid name space clashes
35 */
36#define BITS_PER_LONG 32
37
38#ifndef __ASSEMBLY__
39
40#include <linux/config.h>
41
42typedef signed char s8;
43typedef unsigned char u8;
44
45typedef signed short s16;
46typedef unsigned short u16;
47
48typedef signed int s32;
49typedef unsigned int u32;
50
51typedef signed long long s64;
52typedef unsigned long long u64;
53
54typedef __vector128 vector128;
55
56/* DMA addresses are 32-bits wide */
57typedef u32 dma_addr_t;
58typedef u64 dma64_addr_t;
59
60#ifdef CONFIG_LBD
61typedef u64 sector_t;
62#define HAVE_SECTOR_T
63#endif
64
65#endif /* __ASSEMBLY__ */
66
67#endif /* __KERNEL__ */
68
69#endif
diff --git a/include/asm-ppc/uninorth.h b/include/asm-ppc/uninorth.h
deleted file mode 100644
index f737732c3861..000000000000
--- a/include/asm-ppc/uninorth.h
+++ /dev/null
@@ -1,229 +0,0 @@
1/*
2 * uninorth.h: definitions for using the "UniNorth" host bridge chip
3 * from Apple. This chip is used on "Core99" machines
4 * This also includes U2 used on more recent MacRISC2/3
5 * machines and U3 (G5)
6 *
7 */
8#ifdef __KERNEL__
9#ifndef __ASM_UNINORTH_H__
10#define __ASM_UNINORTH_H__
11
12/*
13 * Uni-N and U3 config space reg. definitions
14 *
15 * (Little endian)
16 */
17
18/* Address ranges selection. This one should work with Bandit too */
19/* Not U3 */
20#define UNI_N_ADDR_SELECT 0x48
21#define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */
22#define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */
23
24/* AGP registers */
25/* Not U3 */
26#define UNI_N_CFG_GART_BASE 0x8c
27#define UNI_N_CFG_AGP_BASE 0x90
28#define UNI_N_CFG_GART_CTRL 0x94
29#define UNI_N_CFG_INTERNAL_STATUS 0x98
30#define UNI_N_CFG_GART_DUMMY_PAGE 0xa4
31
32/* UNI_N_CFG_GART_CTRL bits definitions */
33#define UNI_N_CFG_GART_INVAL 0x00000001
34#define UNI_N_CFG_GART_ENABLE 0x00000100
35#define UNI_N_CFG_GART_2xRESET 0x00010000
36#define UNI_N_CFG_GART_DISSBADET 0x00020000
37/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
38#define U3_N_CFG_GART_SYNCMODE 0x00040000
39#define U3_N_CFG_GART_PERFRD 0x00080000
40#define U3_N_CFG_GART_B2BGNT 0x00200000
41#define U3_N_CFG_GART_FASTDDR 0x00400000
42
43/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
44 * revision 1.5 (x4 AGP) may need further changes.
45 *
46 * AGP_BASE register contains the base address of the AGP aperture on
47 * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
48 * even if decoding of this address range is enabled in the address select
49 * register. Apparently, the only supported bases are 256Mb multiples
50 * (high 4 bits of that register).
51 *
52 * GART_BASE register appear to contain the physical address of the GART
53 * in system memory in the high address bits (page aligned), and the
54 * GART size in the low order bits (number of GART pages)
55 *
56 * The GART format itself is one 32bits word per physical memory page.
57 * This word contains, in little-endian format (!!!), the physical address
58 * of the page in the high bits, and what appears to be an "enable" bit
59 * in the LSB bit (0) that must be set to 1 when the entry is valid.
60 *
61 * Obviously, the GART is not cache coherent and so any change to it
62 * must be flushed to memory (or maybe just make the GART space non
63 * cachable). AGP memory itself doens't seem to be cache coherent neither.
64 *
65 * In order to invalidate the GART (which is probably necessary to inval
66 * the bridge internal TLBs), the following sequence has to be written,
67 * in order, to the GART_CTRL register:
68 *
69 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
70 * UNI_N_CFG_GART_ENABLE
71 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
72 * UNI_N_CFG_GART_ENABLE
73 *
74 * As far as AGP "features" are concerned, it looks like fast write may
75 * not be supported but this has to be confirmed.
76 *
77 * Turning on AGP seem to require a double invalidate operation, one before
78 * setting the AGP command register, on after.
79 *
80 * Turning off AGP seems to require the following sequence: first wait
81 * for the AGP to be idle by reading the internal status register, then
82 * write in that order to the GART_CTRL register:
83 *
84 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
85 * 0
86 * UNI_N_CFG_GART_2xRESET
87 * 0
88 */
89
90/*
91 * Uni-N memory mapped reg. definitions
92 *
93 * Those registers are Big-Endian !!
94 *
95 * Their meaning come from either Darwin and/or from experiments I made with
96 * the bootrom, I'm not sure about their exact meaning yet
97 *
98 */
99
100/* Version of the UniNorth chip */
101#define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */
102
103#define UNI_N_VERSION_107 0x0003 /* 1.0.7 */
104#define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */
105#define UNI_N_VERSION_150 0x0011 /* 1.5 */
106#define UNI_N_VERSION_200 0x0024 /* 2.0 */
107#define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */
108#define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
109#define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */
110
111/* This register is used to enable/disable various clocks */
112#define UNI_N_CLOCK_CNTL 0x0020
113#define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
114#define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
115#define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
116#define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
117
118/* Power Management control */
119#define UNI_N_POWER_MGT 0x0030
120#define UNI_N_POWER_MGT_NORMAL 0x00
121#define UNI_N_POWER_MGT_IDLE2 0x01
122#define UNI_N_POWER_MGT_SLEEP 0x02
123
124/* This register is configured by Darwin depending on the UniN
125 * revision
126 */
127#define UNI_N_ARB_CTRL 0x0040
128#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15
129#define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000
130#define UNI_N_ARB_CTRL_QACK_DELAY 0x30
131#define UNI_N_ARB_CTRL_QACK_DELAY105 0x00
132
133/* This one _might_ return the CPU number of the CPU reading it;
134 * the bootROM decides whether to boot or to sleep/spinloop depending
135 * on this register beeing 0 or not
136 */
137#define UNI_N_CPU_NUMBER 0x0050
138
139/* This register appear to be read by the bootROM to decide what
140 * to do on a non-recoverable reset (powerup or wakeup)
141 */
142#define UNI_N_HWINIT_STATE 0x0070
143#define UNI_N_HWINIT_STATE_SLEEPING 0x01
144#define UNI_N_HWINIT_STATE_RUNNING 0x02
145/* This last bit appear to be used by the bootROM to know the second
146 * CPU has started and will enter it's sleep loop with IP=0
147 */
148#define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000
149
150/* This register controls AACK delay, which is set when 2004 iBook/PowerBook
151 * is in low speed mode.
152 */
153#define UNI_N_AACK_DELAY 0x0100
154#define UNI_N_AACK_DELAY_ENABLE 0x00000001
155
156/* Clock status for Intrepid */
157#define UNI_N_CLOCK_STOP_STATUS0 0x0150
158#define UNI_N_CLOCK_STOPPED_EXTAGP 0x00200000
159#define UNI_N_CLOCK_STOPPED_AGPDEL 0x00100000
160#define UNI_N_CLOCK_STOPPED_I2S0_45_49 0x00080000
161#define UNI_N_CLOCK_STOPPED_I2S0_18 0x00040000
162#define UNI_N_CLOCK_STOPPED_I2S1_45_49 0x00020000
163#define UNI_N_CLOCK_STOPPED_I2S1_18 0x00010000
164#define UNI_N_CLOCK_STOPPED_TIMER 0x00008000
165#define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000
166#define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000
167#define UNI_N_CLOCK_STOPPED_SCC_VIA32 0x00001000
168#define UNI_N_CLOCK_STOPPED_SCC_SLOT0 0x00000800
169#define UNI_N_CLOCK_STOPPED_SCC_SLOT1 0x00000400
170#define UNI_N_CLOCK_STOPPED_SCC_SLOT2 0x00000200
171#define UNI_N_CLOCK_STOPPED_PCI_FBCLKO 0x00000100
172#define UNI_N_CLOCK_STOPPED_VEO0 0x00000080
173#define UNI_N_CLOCK_STOPPED_VEO1 0x00000040
174#define UNI_N_CLOCK_STOPPED_USB0 0x00000020
175#define UNI_N_CLOCK_STOPPED_USB1 0x00000010
176#define UNI_N_CLOCK_STOPPED_USB2 0x00000008
177#define UNI_N_CLOCK_STOPPED_32 0x00000004
178#define UNI_N_CLOCK_STOPPED_45 0x00000002
179#define UNI_N_CLOCK_STOPPED_49 0x00000001
180
181#define UNI_N_CLOCK_STOP_STATUS1 0x0160
182#define UNI_N_CLOCK_STOPPED_PLL4REF 0x00080000
183#define UNI_N_CLOCK_STOPPED_CPUDEL 0x00040000
184#define UNI_N_CLOCK_STOPPED_CPU 0x00020000
185#define UNI_N_CLOCK_STOPPED_BUF_REFCKO 0x00010000
186#define UNI_N_CLOCK_STOPPED_PCI2 0x00008000
187#define UNI_N_CLOCK_STOPPED_FW 0x00004000
188#define UNI_N_CLOCK_STOPPED_GB 0x00002000
189#define UNI_N_CLOCK_STOPPED_ATA66 0x00001000
190#define UNI_N_CLOCK_STOPPED_ATA100 0x00000800
191#define UNI_N_CLOCK_STOPPED_MAX 0x00000400
192#define UNI_N_CLOCK_STOPPED_PCI1 0x00000200
193#define UNI_N_CLOCK_STOPPED_KLPCI 0x00000100
194#define UNI_N_CLOCK_STOPPED_USB0PCI 0x00000080
195#define UNI_N_CLOCK_STOPPED_USB1PCI 0x00000040
196#define UNI_N_CLOCK_STOPPED_USB2PCI 0x00000020
197#define UNI_N_CLOCK_STOPPED_7PCI1 0x00000008
198#define UNI_N_CLOCK_STOPPED_AGP 0x00000004
199#define UNI_N_CLOCK_STOPPED_PCI0 0x00000002
200#define UNI_N_CLOCK_STOPPED_18 0x00000001
201
202/* Intrepid registe to OF do-platform-clockspreading */
203#define UNI_N_CLOCK_SPREADING 0x190
204
205/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
206
207
208/*
209 * U3 specific registers
210 */
211
212
213/* U3 Toggle */
214#define U3_TOGGLE_REG 0x00e0
215#define U3_PMC_START_STOP 0x0001
216#define U3_MPIC_RESET 0x0002
217#define U3_MPIC_OUTPUT_ENABLE 0x0004
218
219/* U3 API PHY Config 1 */
220#define U3_API_PHY_CONFIG_1 0x23030
221
222/* U3 HyperTransport registers */
223#define U3_HT_CONFIG_BASE 0x70000
224#define U3_HT_LINK_COMMAND 0x100
225#define U3_HT_LINK_CONFIG 0x110
226#define U3_HT_LINK_FREQ 0x120
227
228#endif /* __ASM_UNINORTH_H__ */
229#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h
deleted file mode 100644
index 3173ab3d2eb9..000000000000
--- a/include/asm-ppc/unistd.h
+++ /dev/null
@@ -1,493 +0,0 @@
1#ifndef _ASM_PPC_UNISTD_H_
2#define _ASM_PPC_UNISTD_H_
3
4/*
5 * This file contains the system call numbers.
6 */
7#define __NR_restart_syscall 0
8#define __NR_exit 1
9#define __NR_fork 2
10#define __NR_read 3
11#define __NR_write 4
12#define __NR_open 5
13#define __NR_close 6
14#define __NR_waitpid 7
15#define __NR_creat 8
16#define __NR_link 9
17#define __NR_unlink 10
18#define __NR_execve 11
19#define __NR_chdir 12
20#define __NR_time 13
21#define __NR_mknod 14
22#define __NR_chmod 15
23#define __NR_lchown 16
24#define __NR_break 17
25#define __NR_oldstat 18
26#define __NR_lseek 19
27#define __NR_getpid 20
28#define __NR_mount 21
29#define __NR_umount 22
30#define __NR_setuid 23
31#define __NR_getuid 24
32#define __NR_stime 25
33#define __NR_ptrace 26
34#define __NR_alarm 27
35#define __NR_oldfstat 28
36#define __NR_pause 29
37#define __NR_utime 30
38#define __NR_stty 31
39#define __NR_gtty 32
40#define __NR_access 33
41#define __NR_nice 34
42#define __NR_ftime 35
43#define __NR_sync 36
44#define __NR_kill 37
45#define __NR_rename 38
46#define __NR_mkdir 39
47#define __NR_rmdir 40
48#define __NR_dup 41
49#define __NR_pipe 42
50#define __NR_times 43
51#define __NR_prof 44
52#define __NR_brk 45
53#define __NR_setgid 46
54#define __NR_getgid 47
55#define __NR_signal 48
56#define __NR_geteuid 49
57#define __NR_getegid 50
58#define __NR_acct 51
59#define __NR_umount2 52
60#define __NR_lock 53
61#define __NR_ioctl 54
62#define __NR_fcntl 55
63#define __NR_mpx 56
64#define __NR_setpgid 57
65#define __NR_ulimit 58
66#define __NR_oldolduname 59
67#define __NR_umask 60
68#define __NR_chroot 61
69#define __NR_ustat 62
70#define __NR_dup2 63
71#define __NR_getppid 64
72#define __NR_getpgrp 65
73#define __NR_setsid 66
74#define __NR_sigaction 67
75#define __NR_sgetmask 68
76#define __NR_ssetmask 69
77#define __NR_setreuid 70
78#define __NR_setregid 71
79#define __NR_sigsuspend 72
80#define __NR_sigpending 73
81#define __NR_sethostname 74
82#define __NR_setrlimit 75
83#define __NR_getrlimit 76
84#define __NR_getrusage 77
85#define __NR_gettimeofday 78
86#define __NR_settimeofday 79
87#define __NR_getgroups 80
88#define __NR_setgroups 81
89#define __NR_select 82
90#define __NR_symlink 83
91#define __NR_oldlstat 84
92#define __NR_readlink 85
93#define __NR_uselib 86
94#define __NR_swapon 87
95#define __NR_reboot 88
96#define __NR_readdir 89
97#define __NR_mmap 90
98#define __NR_munmap 91
99#define __NR_truncate 92
100#define __NR_ftruncate 93
101#define __NR_fchmod 94
102#define __NR_fchown 95
103#define __NR_getpriority 96
104#define __NR_setpriority 97
105#define __NR_profil 98
106#define __NR_statfs 99
107#define __NR_fstatfs 100
108#define __NR_ioperm 101
109#define __NR_socketcall 102
110#define __NR_syslog 103
111#define __NR_setitimer 104
112#define __NR_getitimer 105
113#define __NR_stat 106
114#define __NR_lstat 107
115#define __NR_fstat 108
116#define __NR_olduname 109
117#define __NR_iopl 110
118#define __NR_vhangup 111
119#define __NR_idle 112
120#define __NR_vm86 113
121#define __NR_wait4 114
122#define __NR_swapoff 115
123#define __NR_sysinfo 116
124#define __NR_ipc 117
125#define __NR_fsync 118
126#define __NR_sigreturn 119
127#define __NR_clone 120
128#define __NR_setdomainname 121
129#define __NR_uname 122
130#define __NR_modify_ldt 123
131#define __NR_adjtimex 124
132#define __NR_mprotect 125
133#define __NR_sigprocmask 126
134#define __NR_create_module 127
135#define __NR_init_module 128
136#define __NR_delete_module 129
137#define __NR_get_kernel_syms 130
138#define __NR_quotactl 131
139#define __NR_getpgid 132
140#define __NR_fchdir 133
141#define __NR_bdflush 134
142#define __NR_sysfs 135
143#define __NR_personality 136
144#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
145#define __NR_setfsuid 138
146#define __NR_setfsgid 139
147#define __NR__llseek 140
148#define __NR_getdents 141
149#define __NR__newselect 142
150#define __NR_flock 143
151#define __NR_msync 144
152#define __NR_readv 145
153#define __NR_writev 146
154#define __NR_getsid 147
155#define __NR_fdatasync 148
156#define __NR__sysctl 149
157#define __NR_mlock 150
158#define __NR_munlock 151
159#define __NR_mlockall 152
160#define __NR_munlockall 153
161#define __NR_sched_setparam 154
162#define __NR_sched_getparam 155
163#define __NR_sched_setscheduler 156
164#define __NR_sched_getscheduler 157
165#define __NR_sched_yield 158
166#define __NR_sched_get_priority_max 159
167#define __NR_sched_get_priority_min 160
168#define __NR_sched_rr_get_interval 161
169#define __NR_nanosleep 162
170#define __NR_mremap 163
171#define __NR_setresuid 164
172#define __NR_getresuid 165
173#define __NR_query_module 166
174#define __NR_poll 167
175#define __NR_nfsservctl 168
176#define __NR_setresgid 169
177#define __NR_getresgid 170
178#define __NR_prctl 171
179#define __NR_rt_sigreturn 172
180#define __NR_rt_sigaction 173
181#define __NR_rt_sigprocmask 174
182#define __NR_rt_sigpending 175
183#define __NR_rt_sigtimedwait 176
184#define __NR_rt_sigqueueinfo 177
185#define __NR_rt_sigsuspend 178
186#define __NR_pread64 179
187#define __NR_pwrite64 180
188#define __NR_chown 181
189#define __NR_getcwd 182
190#define __NR_capget 183
191#define __NR_capset 184
192#define __NR_sigaltstack 185
193#define __NR_sendfile 186
194#define __NR_getpmsg 187 /* some people actually want streams */
195#define __NR_putpmsg 188 /* some people actually want streams */
196#define __NR_vfork 189
197#define __NR_ugetrlimit 190 /* SuS compliant getrlimit */
198#define __NR_readahead 191
199#define __NR_mmap2 192
200#define __NR_truncate64 193
201#define __NR_ftruncate64 194
202#define __NR_stat64 195
203#define __NR_lstat64 196
204#define __NR_fstat64 197
205#define __NR_pciconfig_read 198
206#define __NR_pciconfig_write 199
207#define __NR_pciconfig_iobase 200
208#define __NR_multiplexer 201
209#define __NR_getdents64 202
210#define __NR_pivot_root 203
211#define __NR_fcntl64 204
212#define __NR_madvise 205
213#define __NR_mincore 206
214#define __NR_gettid 207
215#define __NR_tkill 208
216#define __NR_setxattr 209
217#define __NR_lsetxattr 210
218#define __NR_fsetxattr 211
219#define __NR_getxattr 212
220#define __NR_lgetxattr 213
221#define __NR_fgetxattr 214
222#define __NR_listxattr 215
223#define __NR_llistxattr 216
224#define __NR_flistxattr 217
225#define __NR_removexattr 218
226#define __NR_lremovexattr 219
227#define __NR_fremovexattr 220
228#define __NR_futex 221
229#define __NR_sched_setaffinity 222
230#define __NR_sched_getaffinity 223
231/* 224 currently unused */
232#define __NR_tuxcall 225
233#define __NR_sendfile64 226
234#define __NR_io_setup 227
235#define __NR_io_destroy 228
236#define __NR_io_getevents 229
237#define __NR_io_submit 230
238#define __NR_io_cancel 231
239#define __NR_set_tid_address 232
240#define __NR_fadvise64 233
241#define __NR_exit_group 234
242#define __NR_lookup_dcookie 235
243#define __NR_epoll_create 236
244#define __NR_epoll_ctl 237
245#define __NR_epoll_wait 238
246#define __NR_remap_file_pages 239
247#define __NR_timer_create 240
248#define __NR_timer_settime 241
249#define __NR_timer_gettime 242
250#define __NR_timer_getoverrun 243
251#define __NR_timer_delete 244
252#define __NR_clock_settime 245
253#define __NR_clock_gettime 246
254#define __NR_clock_getres 247
255#define __NR_clock_nanosleep 248
256#define __NR_swapcontext 249
257#define __NR_tgkill 250
258#define __NR_utimes 251
259#define __NR_statfs64 252
260#define __NR_fstatfs64 253
261#define __NR_fadvise64_64 254
262#define __NR_rtas 255
263#define __NR_sys_debug_setcontext 256
264/* Number 257 is reserved for vserver */
265/* 258 currently unused */
266/* Number 259 is reserved for new sys_mbind */
267/* Number 260 is reserved for new sys_get_mempolicy */
268/* Number 261 is reserved for new sys_set_mempolicy */
269#define __NR_mq_open 262
270#define __NR_mq_unlink 263
271#define __NR_mq_timedsend 264
272#define __NR_mq_timedreceive 265
273#define __NR_mq_notify 266
274#define __NR_mq_getsetattr 267
275#define __NR_kexec_load 268
276#define __NR_add_key 269
277#define __NR_request_key 270
278#define __NR_keyctl 271
279#define __NR_waitid 272
280#define __NR_ioprio_set 273
281#define __NR_ioprio_get 274
282#define __NR_inotify_init 275
283#define __NR_inotify_add_watch 276
284#define __NR_inotify_rm_watch 277
285
286#define __NR_syscalls 278
287
288#define __NR(n) #n
289
290/* On powerpc a system call basically clobbers the same registers like a
291 * function call, with the exception of LR (which is needed for the
292 * "sc; bnslr" sequence) and CR (where only CR0.SO is clobbered to signal
293 * an error return status).
294 */
295
296#define __syscall_nr(nr, type, name, args...) \
297 unsigned long __sc_ret, __sc_err; \
298 { \
299 register unsigned long __sc_0 __asm__ ("r0"); \
300 register unsigned long __sc_3 __asm__ ("r3"); \
301 register unsigned long __sc_4 __asm__ ("r4"); \
302 register unsigned long __sc_5 __asm__ ("r5"); \
303 register unsigned long __sc_6 __asm__ ("r6"); \
304 register unsigned long __sc_7 __asm__ ("r7"); \
305 register unsigned long __sc_8 __asm__ ("r8"); \
306 \
307 __sc_loadargs_##nr(name, args); \
308 __asm__ __volatile__ \
309 ("sc \n\t" \
310 "mfcr %0 " \
311 : "=&r" (__sc_0), \
312 "=&r" (__sc_3), "=&r" (__sc_4), \
313 "=&r" (__sc_5), "=&r" (__sc_6), \
314 "=&r" (__sc_7), "=&r" (__sc_8) \
315 : __sc_asm_input_##nr \
316 : "cr0", "ctr", "memory", \
317 "r9", "r10","r11", "r12"); \
318 __sc_ret = __sc_3; \
319 __sc_err = __sc_0; \
320 } \
321 if (__sc_err & 0x10000000) \
322 { \
323 errno = __sc_ret; \
324 __sc_ret = -1; \
325 } \
326 return (type) __sc_ret
327
328#define __sc_loadargs_0(name, dummy...) \
329 __sc_0 = __NR_##name
330#define __sc_loadargs_1(name, arg1) \
331 __sc_loadargs_0(name); \
332 __sc_3 = (unsigned long) (arg1)
333#define __sc_loadargs_2(name, arg1, arg2) \
334 __sc_loadargs_1(name, arg1); \
335 __sc_4 = (unsigned long) (arg2)
336#define __sc_loadargs_3(name, arg1, arg2, arg3) \
337 __sc_loadargs_2(name, arg1, arg2); \
338 __sc_5 = (unsigned long) (arg3)
339#define __sc_loadargs_4(name, arg1, arg2, arg3, arg4) \
340 __sc_loadargs_3(name, arg1, arg2, arg3); \
341 __sc_6 = (unsigned long) (arg4)
342#define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5) \
343 __sc_loadargs_4(name, arg1, arg2, arg3, arg4); \
344 __sc_7 = (unsigned long) (arg5)
345#define __sc_loadargs_6(name, arg1, arg2, arg3, arg4, arg5, arg6) \
346 __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5); \
347 __sc_8 = (unsigned long) (arg6)
348
349#define __sc_asm_input_0 "0" (__sc_0)
350#define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3)
351#define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4)
352#define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5)
353#define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6)
354#define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7)
355#define __sc_asm_input_6 __sc_asm_input_5, "6" (__sc_8)
356
357#define _syscall0(type,name) \
358type name(void) \
359{ \
360 __syscall_nr(0, type, name); \
361}
362
363#define _syscall1(type,name,type1,arg1) \
364type name(type1 arg1) \
365{ \
366 __syscall_nr(1, type, name, arg1); \
367}
368
369#define _syscall2(type,name,type1,arg1,type2,arg2) \
370type name(type1 arg1, type2 arg2) \
371{ \
372 __syscall_nr(2, type, name, arg1, arg2); \
373}
374
375#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
376type name(type1 arg1, type2 arg2, type3 arg3) \
377{ \
378 __syscall_nr(3, type, name, arg1, arg2, arg3); \
379}
380
381#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
382type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
383{ \
384 __syscall_nr(4, type, name, arg1, arg2, arg3, arg4); \
385}
386
387#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
388type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \
389{ \
390 __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5); \
391}
392
393#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \
394type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \
395{ \
396 __syscall_nr(6, type, name, arg1, arg2, arg3, arg4, arg5, arg6); \
397}
398
399#ifdef __KERNEL__
400
401#define __NR__exit __NR_exit
402#define NR_syscalls __NR_syscalls
403
404#define __ARCH_WANT_IPC_PARSE_VERSION
405#define __ARCH_WANT_OLD_READDIR
406#define __ARCH_WANT_OLD_STAT
407#define __ARCH_WANT_STAT64
408#define __ARCH_WANT_SYS_ALARM
409#define __ARCH_WANT_SYS_GETHOSTNAME
410#define __ARCH_WANT_SYS_PAUSE
411#define __ARCH_WANT_SYS_SGETMASK
412#define __ARCH_WANT_SYS_SIGNAL
413#define __ARCH_WANT_SYS_TIME
414#define __ARCH_WANT_SYS_UTIME
415#define __ARCH_WANT_SYS_WAITPID
416#define __ARCH_WANT_SYS_SOCKETCALL
417#define __ARCH_WANT_SYS_FADVISE64
418#define __ARCH_WANT_SYS_GETPGRP
419#define __ARCH_WANT_SYS_LLSEEK
420#define __ARCH_WANT_SYS_NICE
421#define __ARCH_WANT_SYS_OLD_GETRLIMIT
422#define __ARCH_WANT_SYS_OLDUMOUNT
423#define __ARCH_WANT_SYS_SIGPENDING
424#define __ARCH_WANT_SYS_SIGPROCMASK
425#define __ARCH_WANT_SYS_RT_SIGACTION
426
427/*
428 * Forking from kernel space will result in the child getting a new,
429 * empty kernel stack area. Thus the child cannot access automatic
430 * variables set in the parent unless they are in registers, and the
431 * procedure where the fork was done cannot return to its caller in
432 * the child.
433 */
434
435#ifdef __KERNEL_SYSCALLS__
436
437#include <linux/compiler.h>
438#include <linux/types.h>
439
440/*
441 * System call prototypes.
442 */
443extern pid_t setsid(void);
444extern int write(int fd, const char *buf, off_t count);
445extern int read(int fd, char *buf, off_t count);
446extern off_t lseek(int fd, off_t offset, int count);
447extern int dup(int fd);
448extern int execve(const char *file, char **argv, char **envp);
449extern int open(const char *file, int flag, int mode);
450extern int close(int fd);
451extern pid_t waitpid(pid_t pid, int *wait_stat, int options);
452
453unsigned long sys_mmap(unsigned long addr, size_t len,
454 unsigned long prot, unsigned long flags,
455 unsigned long fd, off_t offset);
456unsigned long sys_mmap2(unsigned long addr, size_t len,
457 unsigned long prot, unsigned long flags,
458 unsigned long fd, unsigned long pgoff);
459struct pt_regs;
460int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
461 unsigned long a3, unsigned long a4, unsigned long a5,
462 struct pt_regs *regs);
463int sys_clone(unsigned long clone_flags, unsigned long usp,
464 int __user *parent_tidp, void __user *child_threadptr,
465 int __user *child_tidp, int p6,
466 struct pt_regs *regs);
467int sys_fork(int p1, int p2, int p3, int p4, int p5, int p6,
468 struct pt_regs *regs);
469int sys_vfork(int p1, int p2, int p3, int p4, int p5, int p6,
470 struct pt_regs *regs);
471int sys_pipe(int __user *fildes);
472int sys_ptrace(long request, long pid, long addr, long data);
473struct sigaction;
474long sys_rt_sigaction(int sig,
475 const struct sigaction __user *act,
476 struct sigaction __user *oact,
477 size_t sigsetsize);
478
479#endif /* __KERNEL_SYSCALLS__ */
480
481/*
482 * "Conditional" syscalls
483 *
484 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
485 * but it doesn't work on all toolchains, so we just do it by hand
486 */
487#ifndef cond_syscall
488#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
489#endif
490
491#endif /* __KERNEL__ */
492
493#endif /* _ASM_PPC_UNISTD_H_ */
diff --git a/include/asm-ppc/vga.h b/include/asm-ppc/vga.h
deleted file mode 100644
index c5864734e3e1..000000000000
--- a/include/asm-ppc/vga.h
+++ /dev/null
@@ -1,46 +0,0 @@
1/*
2 * Access to VGA videoram
3 *
4 * (c) 1998 Martin Mares <mj@ucw.cz>
5 */
6
7#ifdef __KERNEL__
8#ifndef _LINUX_ASM_VGA_H_
9#define _LINUX_ASM_VGA_H_
10
11#include <asm/io.h>
12
13#include <linux/config.h>
14
15#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
16
17#define VT_BUF_HAVE_RW
18/*
19 * These are only needed for supporting VGA or MDA text mode, which use little
20 * endian byte ordering.
21 * In other cases, we can optimize by using native byte ordering and
22 * <linux/vt_buffer.h> has already done the right job for us.
23 */
24
25extern inline void scr_writew(u16 val, volatile u16 *addr)
26{
27 st_le16(addr, val);
28}
29
30extern inline u16 scr_readw(volatile const u16 *addr)
31{
32 return ld_le16(addr);
33}
34
35#define VT_BUF_HAVE_MEMCPYW
36#define scr_memcpyw memcpy
37
38#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
39
40extern unsigned long vgacon_remap_base;
41#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
42#define vga_readb(x) (*(x))
43#define vga_writeb(x,y) (*(y) = (x))
44
45#endif
46#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/xmon.h b/include/asm-ppc/xmon.h
deleted file mode 100644
index 042b83e6680d..000000000000
--- a/include/asm-ppc/xmon.h
+++ /dev/null
@@ -1,17 +0,0 @@
1#ifndef __PPC_XMON_H
2#define __PPC_XMON_H
3#ifdef __KERNEL__
4
5struct pt_regs;
6
7extern void xmon(struct pt_regs *excp);
8extern void xmon_printf(const char *fmt, ...);
9extern void xmon_map_scc(void);
10extern int xmon_bpt(struct pt_regs *regs);
11extern int xmon_sstep(struct pt_regs *regs);
12extern int xmon_iabr_match(struct pt_regs *regs);
13extern int xmon_dabr_match(struct pt_regs *regs);
14extern void (*xmon_fault_handler)(struct pt_regs *regs);
15
16#endif
17#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 09:52:40 -0500