aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-ppc
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-ppc')
-rw-r--r--include/asm-ppc/ibm44x.h34
-rw-r--r--include/asm-ppc/ibm4xx.h4
-rw-r--r--include/asm-ppc/ibm_ocp.h12
-rw-r--r--include/asm-ppc/pci.h4
-rw-r--r--include/asm-ppc/pgtable.h52
-rw-r--r--include/asm-ppc/ppc_asm.h6
-rw-r--r--include/asm-ppc/unistd.h5
7 files changed, 109 insertions, 8 deletions
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index 87f051138b9d..21e41c9b7267 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -35,8 +35,10 @@
35#define PPC44x_LOW_SLOT 63 35#define PPC44x_LOW_SLOT 63
36 36
37/* LS 32-bits of UART0 physical address location for early serial text debug */ 37/* LS 32-bits of UART0 physical address location for early serial text debug */
38#ifdef CONFIG_440SP 38#if defined(CONFIG_440SP)
39#define UART0_PHYS_IO_BASE 0xf0000200 39#define UART0_PHYS_IO_BASE 0xf0000200
40#elif defined(CONFIG_440EP)
41#define UART0_PHYS_IO_BASE 0xe0000000
40#else 42#else
41#define UART0_PHYS_IO_BASE 0x40000200 43#define UART0_PHYS_IO_BASE 0x40000200
42#endif 44#endif
@@ -49,11 +51,16 @@
49/* 51/*
50 * Standard 4GB "page" definitions 52 * Standard 4GB "page" definitions
51 */ 53 */
52#ifdef CONFIG_440SP 54#if defined(CONFIG_440SP)
53#define PPC44x_IO_PAGE 0x0000000100000000ULL 55#define PPC44x_IO_PAGE 0x0000000100000000ULL
54#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL 56#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
55#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 57#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
56#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL 58#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
59#elif defined(CONFIG_440EP)
60#define PPC44x_IO_PAGE 0x0000000000000000ULL
61#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
62#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
63#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
57#else 64#else
58#define PPC44x_IO_PAGE 0x0000000100000000ULL 65#define PPC44x_IO_PAGE 0x0000000100000000ULL
59#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL 66#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
@@ -64,7 +71,7 @@
64/* 71/*
65 * 36-bit trap ranges 72 * 36-bit trap ranges
66 */ 73 */
67#ifdef CONFIG_440SP 74#if defined(CONFIG_440SP)
68#define PPC44x_IO_LO 0xf0000000UL 75#define PPC44x_IO_LO 0xf0000000UL
69#define PPC44x_IO_HI 0xf0000fffUL 76#define PPC44x_IO_HI 0xf0000fffUL
70#define PPC44x_PCI0CFG_LO 0x0ec00000UL 77#define PPC44x_PCI0CFG_LO 0x0ec00000UL
@@ -75,6 +82,13 @@
75#define PPC44x_PCI2CFG_HI 0x2ec00007UL 82#define PPC44x_PCI2CFG_HI 0x2ec00007UL
76#define PPC44x_PCIMEM_LO 0x80000000UL 83#define PPC44x_PCIMEM_LO 0x80000000UL
77#define PPC44x_PCIMEM_HI 0xdfffffffUL 84#define PPC44x_PCIMEM_HI 0xdfffffffUL
85#elif defined(CONFIG_440EP)
86#define PPC44x_IO_LO 0xef500000UL
87#define PPC44x_IO_HI 0xefffffffUL
88#define PPC44x_PCI0CFG_LO 0xeec00000UL
89#define PPC44x_PCI0CFG_HI 0xeecfffffUL
90#define PPC44x_PCIMEM_LO 0xa0000000UL
91#define PPC44x_PCIMEM_HI 0xdfffffffUL
78#else 92#else
79#define PPC44x_IO_LO 0x40000000UL 93#define PPC44x_IO_LO 0x40000000UL
80#define PPC44x_IO_HI 0x40000fffUL 94#define PPC44x_IO_HI 0x40000fffUL
@@ -152,6 +166,12 @@
152#define DCRN_SDR_UART0 0x0120 166#define DCRN_SDR_UART0 0x0120
153#define DCRN_SDR_UART1 0x0121 167#define DCRN_SDR_UART1 0x0121
154 168
169#ifdef CONFIG_440EP
170#define DCRN_SDR_UART2 0x0122
171#define DCRN_SDR_UART3 0x0123
172#define DCRN_SDR_CUST0 0x4000
173#endif
174
155/* SDR read/write helper macros */ 175/* SDR read/write helper macros */
156#define SDR_READ(offset) ({\ 176#define SDR_READ(offset) ({\
157 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 177 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
@@ -169,6 +189,14 @@
169#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */ 189#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
170#define DCRN_MAL_BASE 0x180 190#define DCRN_MAL_BASE 0x180
171 191
192#ifdef CONFIG_440EP
193#define DCRN_DMA2P40_BASE 0x300
194#define DCRN_DMA2P41_BASE 0x308
195#define DCRN_DMA2P42_BASE 0x310
196#define DCRN_DMA2P43_BASE 0x318
197#define DCRN_DMA2P4SR_BASE 0x320
198#endif
199
172/* UIC */ 200/* UIC */
173#define DCRN_UIC0_BASE 0xc0 201#define DCRN_UIC0_BASE 0xc0
174#define DCRN_UIC1_BASE 0xd0 202#define DCRN_UIC1_BASE 0xd0
diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h
index 35260afa33a9..e807be96e981 100644
--- a/include/asm-ppc/ibm4xx.h
+++ b/include/asm-ppc/ibm4xx.h
@@ -97,6 +97,10 @@ void ppc4xx_init(unsigned long r3, unsigned long r4, unsigned long r5,
97 97
98#elif CONFIG_44x 98#elif CONFIG_44x
99 99
100#if defined(CONFIG_BAMBOO)
101#include <platforms/4xx/bamboo.h>
102#endif
103
100#if defined(CONFIG_EBONY) 104#if defined(CONFIG_EBONY)
101#include <platforms/4xx/ebony.h> 105#include <platforms/4xx/ebony.h>
102#endif 106#endif
diff --git a/include/asm-ppc/ibm_ocp.h b/include/asm-ppc/ibm_ocp.h
index 8c61d93043af..3f7b5669e6d5 100644
--- a/include/asm-ppc/ibm_ocp.h
+++ b/include/asm-ppc/ibm_ocp.h
@@ -71,6 +71,8 @@ struct ocp_func_emac_data {
71 71
72/* Sysfs support */ 72/* Sysfs support */
73#define OCP_SYSFS_EMAC_DATA() \ 73#define OCP_SYSFS_EMAC_DATA() \
74OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_idx) \
75OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, rgmii_mux) \
74OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \ 76OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_idx) \
75OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \ 77OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, zmii_mux) \
76OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \ 78OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_idx) \
@@ -78,9 +80,14 @@ OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_rx_chan) \
78OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \ 80OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mal_tx_chan) \
79OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \ 81OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, wol_irq) \
80OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \ 82OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, mdio_idx) \
83OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, tah_idx) \
84OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "%d\n", emac, phy_mode) \
85OCP_SYSFS_ADDTL(struct ocp_func_emac_data, "0x%08x\n", emac, phy_map) \
81 \ 86 \
82void ocp_show_emac_data(struct device *dev) \ 87void ocp_show_emac_data(struct device *dev) \
83{ \ 88{ \
89 device_create_file(dev, &dev_attr_emac_rgmii_idx); \
90 device_create_file(dev, &dev_attr_emac_rgmii_mux); \
84 device_create_file(dev, &dev_attr_emac_zmii_idx); \ 91 device_create_file(dev, &dev_attr_emac_zmii_idx); \
85 device_create_file(dev, &dev_attr_emac_zmii_mux); \ 92 device_create_file(dev, &dev_attr_emac_zmii_mux); \
86 device_create_file(dev, &dev_attr_emac_mal_idx); \ 93 device_create_file(dev, &dev_attr_emac_mal_idx); \
@@ -88,6 +95,9 @@ void ocp_show_emac_data(struct device *dev) \
88 device_create_file(dev, &dev_attr_emac_mal_tx_chan); \ 95 device_create_file(dev, &dev_attr_emac_mal_tx_chan); \
89 device_create_file(dev, &dev_attr_emac_wol_irq); \ 96 device_create_file(dev, &dev_attr_emac_wol_irq); \
90 device_create_file(dev, &dev_attr_emac_mdio_idx); \ 97 device_create_file(dev, &dev_attr_emac_mdio_idx); \
98 device_create_file(dev, &dev_attr_emac_tah_idx); \
99 device_create_file(dev, &dev_attr_emac_phy_mode); \
100 device_create_file(dev, &dev_attr_emac_phy_map); \
91} 101}
92 102
93#ifdef CONFIG_40x 103#ifdef CONFIG_40x
@@ -157,7 +167,7 @@ OCP_SYSFS_ADDTL(struct ocp_func_iic_data, "%d\n", iic, fast_mode) \
157 \ 167 \
158void ocp_show_iic_data(struct device *dev) \ 168void ocp_show_iic_data(struct device *dev) \
159{ \ 169{ \
160 device_create_file(dev, &dev_attr_iic_fast_mode); \ 170 device_create_file(dev, &dev_attr_iic_fast_mode); \
161} 171}
162#endif /* __IBM_OCP_H__ */ 172#endif /* __IBM_OCP_H__ */
163#endif /* __KERNEL__ */ 173#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h
index a13d55870e62..a811e440c978 100644
--- a/include/asm-ppc/pci.h
+++ b/include/asm-ppc/pci.h
@@ -105,6 +105,10 @@ extern void
105pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region, 105pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
106 struct resource *res); 106 struct resource *res);
107 107
108extern void
109pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
110 struct pci_bus_region *region);
111
108extern void pcibios_add_platform_entries(struct pci_dev *dev); 112extern void pcibios_add_platform_entries(struct pci_dev *dev);
109 113
110struct file; 114struct file;
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index 4d4b20c9de78..92f30b28b252 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -202,18 +202,64 @@ extern unsigned long ioremap_bot, ioremap_base;
202 * 202 *
203 * Note that these bits preclude future use of a page size 203 * Note that these bits preclude future use of a page size
204 * less than 4KB. 204 * less than 4KB.
205 *
206 *
207 * PPC 440 core has following TLB attribute fields;
208 *
209 * TLB1:
210 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
211 * RPN................................. - - - - - - ERPN.......
212 *
213 * TLB2:
214 * 0 1 2 3 4 ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
215 * - - - - - - U0 U1 U2 U3 W I M G E - UX UW UR SX SW SR
216 *
217 * There are some constrains and options, to decide mapping software bits
218 * into TLB entry.
219 *
220 * - PRESENT *must* be in the bottom three bits because swap cache
221 * entries use the top 29 bits for TLB2.
222 *
223 * - FILE *must* be in the bottom three bits because swap cache
224 * entries use the top 29 bits for TLB2.
225 *
226 * - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
227 * doesn't support SMP. So we can use this as software bit, like
228 * DIRTY.
229 *
230 * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
231 * for memory protection related functions (see PTE structure in
232 * include/asm-ppc/mmu.h). The _PAGE_XXX definitions in this file map to the
233 * above bits. Note that the bit values are CPU specific, not architecture
234 * specific.
235 *
236 * The kernel PTE entry holds an arch-dependent swp_entry structure under
237 * certain situations. In other words, in such situations some portion of
238 * the PTE bits are used as a swp_entry. In the PPC implementation, the
239 * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
240 * hold protection values. That means the three protection bits are
241 * reserved for both PTE and SWAP entry at the most significant three
242 * LSBs.
243 *
244 * There are three protection bits available for SWAP entry:
245 * _PAGE_PRESENT
246 * _PAGE_FILE
247 * _PAGE_HASHPTE (if HW has)
248 *
249 * So those three bits have to be inside of 0-2nd LSB of PTE.
250 *
205 */ 251 */
252
206#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */ 253#define _PAGE_PRESENT 0x00000001 /* S: PTE valid */
207#define _PAGE_RW 0x00000002 /* S: Write permission */ 254#define _PAGE_RW 0x00000002 /* S: Write permission */
208#define _PAGE_DIRTY 0x00000004 /* S: Page dirty */ 255#define _PAGE_FILE 0x00000004 /* S: nonlinear file mapping */
209#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */ 256#define _PAGE_ACCESSED 0x00000008 /* S: Page referenced */
210#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */ 257#define _PAGE_HWWRITE 0x00000010 /* H: Dirty & RW */
211#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */ 258#define _PAGE_HWEXEC 0x00000020 /* H: Execute permission */
212#define _PAGE_USER 0x00000040 /* S: User page */ 259#define _PAGE_USER 0x00000040 /* S: User page */
213#define _PAGE_ENDIAN 0x00000080 /* H: E bit */ 260#define _PAGE_ENDIAN 0x00000080 /* H: E bit */
214#define _PAGE_GUARDED 0x00000100 /* H: G bit */ 261#define _PAGE_GUARDED 0x00000100 /* H: G bit */
215#define _PAGE_COHERENT 0x00000200 /* H: M bit */ 262#define _PAGE_DIRTY 0x00000200 /* S: Page dirty */
216#define _PAGE_FILE 0x00000400 /* S: nonlinear file mapping */
217#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */ 263#define _PAGE_NO_CACHE 0x00000400 /* H: I bit */
218#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */ 264#define _PAGE_WRITETHRU 0x00000800 /* H: W bit */
219 265
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
index f76221def484..bb53e2def363 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-ppc/ppc_asm.h
@@ -186,6 +186,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
186#define PPC405_ERR77_SYNC 186#define PPC405_ERR77_SYNC
187#endif 187#endif
188 188
189#ifdef CONFIG_IBM440EP_ERR42
190#define PPC440EP_ERR42 isync
191#else
192#define PPC440EP_ERR42
193#endif
194
189/* The boring bits... */ 195/* The boring bits... */
190 196
191/* Condition Register Bit Fields */ 197/* Condition Register Bit Fields */
diff --git a/include/asm-ppc/unistd.h b/include/asm-ppc/unistd.h
index a7894e0fbbb1..3173ab3d2eb9 100644
--- a/include/asm-ppc/unistd.h
+++ b/include/asm-ppc/unistd.h
@@ -279,8 +279,11 @@
279#define __NR_waitid 272 279#define __NR_waitid 272
280#define __NR_ioprio_set 273 280#define __NR_ioprio_set 273
281#define __NR_ioprio_get 274 281#define __NR_ioprio_get 274
282#define __NR_inotify_init 275
283#define __NR_inotify_add_watch 276
284#define __NR_inotify_rm_watch 277
282 285
283#define __NR_syscalls 275 286#define __NR_syscalls 278
284 287
285#define __NR(n) #n 288#define __NR(n) #n
286 289