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-rw-r--r--include/asm-ppc/mmu.h2
-rw-r--r--include/asm-ppc/mmu_context.h2
-rw-r--r--include/asm-ppc/ppc_asm.h2
-rw-r--r--include/asm-ppc/reg.h1
-rw-r--r--include/asm-ppc/reg_booke.h18
5 files changed, 22 insertions, 3 deletions
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index d465aee1c82e..9205db404c7a 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -405,7 +405,7 @@ typedef struct _P601_BAT {
405 405
406#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) 406#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
407#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) 407#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
408#define MAS0_NV 0x00000FFF 408#define MAS0_NV(x) ((x) & 0x00000FFF)
409 409
410#define MAS1_VALID 0x80000000 410#define MAS1_VALID 0x80000000
411#define MAS1_IPROT 0x40000000 411#define MAS1_IPROT 0x40000000
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index 9222fa6ca172..ccabbce39d85 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -63,7 +63,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
63#define LAST_CONTEXT 255 63#define LAST_CONTEXT 255
64#define FIRST_CONTEXT 1 64#define FIRST_CONTEXT 1
65 65
66#elif defined(CONFIG_E500) 66#elif defined(CONFIG_E200) || defined(CONFIG_E500)
67#define NO_CONTEXT 256 67#define NO_CONTEXT 256
68#define LAST_CONTEXT 255 68#define LAST_CONTEXT 255
69#define FIRST_CONTEXT 1 69#define FIRST_CONTEXT 1
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
index 13fa8e7483c1..f76221def484 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-ppc/ppc_asm.h
@@ -174,6 +174,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
174#define CLR_TOP32(r) 174#define CLR_TOP32(r)
175#endif /* CONFIG_PPC64BRIDGE */ 175#endif /* CONFIG_PPC64BRIDGE */
176 176
177#define RFCI .long 0x4c000066 /* rfci instruction */
178#define RFDI .long 0x4c00004e /* rfdi instruction */
177#define RFMCI .long 0x4c00004c /* rfmci instruction */ 179#define RFMCI .long 0x4c00004c /* rfmci instruction */
178 180
179#ifdef CONFIG_IBM405_ERR77 181#ifdef CONFIG_IBM405_ERR77
diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
index c418aab7cd34..88b4222154d4 100644
--- a/include/asm-ppc/reg.h
+++ b/include/asm-ppc/reg.h
@@ -160,6 +160,7 @@
160#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 160#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
161#define HID0_DCI (1<<10) /* Data Cache Invalidate */ 161#define HID0_DCI (1<<10) /* Data Cache Invalidate */
162#define HID0_SPD (1<<9) /* Speculative disable */ 162#define HID0_SPD (1<<9) /* Speculative disable */
163#define HID0_DAPUEN (1<<8) /* Debug APU enable */
163#define HID0_SGE (1<<7) /* Store Gathering Enable */ 164#define HID0_SGE (1<<7) /* Store Gathering Enable */
164#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 165#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
165#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ 166#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 45c5e6f2b7ab..00ad9c754c78 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -165,6 +165,8 @@ do { \
165#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 165#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
166#define SPRN_MCSR 0x23C /* Machine Check Status Register */ 166#define SPRN_MCSR 0x23C /* Machine Check Status Register */
167#define SPRN_MCAR 0x23D /* Machine Check Address Register */ 167#define SPRN_MCAR 0x23D /* Machine Check Address Register */
168#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
169#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
168#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 170#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
169#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 171#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
170#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 172#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
@@ -264,6 +266,17 @@ do { \
264#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ 266#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
265#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ 267#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
266#endif 268#endif
269#ifdef CONFIG_E200
270#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
271#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
272#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
273#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
274 fetch for an exception handler */
275#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
276#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
277#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
278 store or cache line push */
279#endif
267 280
268/* Bit definitions for the DBSR. */ 281/* Bit definitions for the DBSR. */
269/* 282/*
@@ -311,6 +324,7 @@ do { \
311#define ESR_ST 0x00800000 /* Store Operation */ 324#define ESR_ST 0x00800000 /* Store Operation */
312#define ESR_DLK 0x00200000 /* Data Cache Locking */ 325#define ESR_DLK 0x00200000 /* Data Cache Locking */
313#define ESR_ILK 0x00100000 /* Instr. Cache Locking */ 326#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
327#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
314#define ESR_BO 0x00020000 /* Byte Ordering */ 328#define ESR_BO 0x00020000 /* Byte Ordering */
315 329
316/* Bit definitions related to the DBCR0. */ 330/* Bit definitions related to the DBCR0. */
@@ -387,10 +401,12 @@ do { \
387#define ICCR_CACHE 1 /* Cacheable */ 401#define ICCR_CACHE 1 /* Cacheable */
388 402
389/* Bit definitions for L1CSR0. */ 403/* Bit definitions for L1CSR0. */
404#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
390#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 405#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
406#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
391#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 407#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
392 408
393/* Bit definitions for L1CSR0. */ 409/* Bit definitions for L1CSR1. */
394#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ 410#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
395#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ 411#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
396#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ 412#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */