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-rw-r--r--include/asm-ppc/agp.h10
-rw-r--r--include/asm-ppc/cpm2.h46
-rw-r--r--include/asm-ppc/fsl_ocp.h54
-rw-r--r--include/asm-ppc/irq.h34
-rw-r--r--include/asm-ppc/kexec.h38
-rw-r--r--include/asm-ppc/m8260_pci.h1
-rw-r--r--include/asm-ppc/machdep.h31
-rw-r--r--include/asm-ppc/mmu.h2
-rw-r--r--include/asm-ppc/mmu_context.h2
-rw-r--r--include/asm-ppc/mpc10x.h6
-rw-r--r--include/asm-ppc/mpc8260.h2
-rw-r--r--include/asm-ppc/mpc85xx.h60
-rw-r--r--include/asm-ppc/ocp.h6
-rw-r--r--include/asm-ppc/pgtable.h2
-rw-r--r--include/asm-ppc/ppc_asm.h2
-rw-r--r--include/asm-ppc/ppc_sys.h2
-rw-r--r--include/asm-ppc/reg.h1
-rw-r--r--include/asm-ppc/reg_booke.h18
-rw-r--r--include/asm-ppc/seccomp.h10
-rw-r--r--include/asm-ppc/sigcontext.h2
-rw-r--r--include/asm-ppc/smp.h2
-rw-r--r--include/asm-ppc/thread_info.h10
22 files changed, 257 insertions, 84 deletions
diff --git a/include/asm-ppc/agp.h b/include/asm-ppc/agp.h
index be27cfa8c5b0..ca9e423307f4 100644
--- a/include/asm-ppc/agp.h
+++ b/include/asm-ppc/agp.h
@@ -10,4 +10,14 @@
10#define flush_agp_mappings() 10#define flush_agp_mappings()
11#define flush_agp_cache() mb() 11#define flush_agp_cache() mb()
12 12
13/* Convert a physical address to an address suitable for the GART. */
14#define phys_to_gart(x) (x)
15#define gart_to_phys(x) (x)
16
17/* GATT allocation. Returns/accepts GATT kernel virtual address. */
18#define alloc_gatt_pages(order) \
19 ((char *)__get_free_pages(GFP_KERNEL, (order)))
20#define free_gatt_pages(table, order) \
21 free_pages((unsigned long)(table), (order))
22
13#endif 23#endif
diff --git a/include/asm-ppc/cpm2.h b/include/asm-ppc/cpm2.h
index 42fd1068cf2a..c5883dbed63f 100644
--- a/include/asm-ppc/cpm2.h
+++ b/include/asm-ppc/cpm2.h
@@ -1039,6 +1039,52 @@ typedef struct im_idma {
1039#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */ 1039#define CMXSCR_TS4CS_CLK7 0x00000006 /* SCC4 Tx Clock Source is CLK7 */
1040#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */ 1040#define CMXSCR_TS4CS_CLK8 0x00000007 /* SCC4 Tx Clock Source is CLK8 */
1041 1041
1042/*-----------------------------------------------------------------------
1043 * SIUMCR - SIU Module Configuration Register 4-31
1044 */
1045#define SIUMCR_BBD 0x80000000 /* Bus Busy Disable */
1046#define SIUMCR_ESE 0x40000000 /* External Snoop Enable */
1047#define SIUMCR_PBSE 0x20000000 /* Parity Byte Select Enable */
1048#define SIUMCR_CDIS 0x10000000 /* Core Disable */
1049#define SIUMCR_DPPC00 0x00000000 /* Data Parity Pins Configuration*/
1050#define SIUMCR_DPPC01 0x04000000 /* - " - */
1051#define SIUMCR_DPPC10 0x08000000 /* - " - */
1052#define SIUMCR_DPPC11 0x0c000000 /* - " - */
1053#define SIUMCR_L2CPC00 0x00000000 /* L2 Cache Pins Configuration */
1054#define SIUMCR_L2CPC01 0x01000000 /* - " - */
1055#define SIUMCR_L2CPC10 0x02000000 /* - " - */
1056#define SIUMCR_L2CPC11 0x03000000 /* - " - */
1057#define SIUMCR_LBPC00 0x00000000 /* Local Bus Pins Configuration */
1058#define SIUMCR_LBPC01 0x00400000 /* - " - */
1059#define SIUMCR_LBPC10 0x00800000 /* - " - */
1060#define SIUMCR_LBPC11 0x00c00000 /* - " - */
1061#define SIUMCR_APPC00 0x00000000 /* Address Parity Pins Configuration*/
1062#define SIUMCR_APPC01 0x00100000 /* - " - */
1063#define SIUMCR_APPC10 0x00200000 /* - " - */
1064#define SIUMCR_APPC11 0x00300000 /* - " - */
1065#define SIUMCR_CS10PC00 0x00000000 /* CS10 Pin Configuration */
1066#define SIUMCR_CS10PC01 0x00040000 /* - " - */
1067#define SIUMCR_CS10PC10 0x00080000 /* - " - */
1068#define SIUMCR_CS10PC11 0x000c0000 /* - " - */
1069#define SIUMCR_BCTLC00 0x00000000 /* Buffer Control Configuration */
1070#define SIUMCR_BCTLC01 0x00010000 /* - " - */
1071#define SIUMCR_BCTLC10 0x00020000 /* - " - */
1072#define SIUMCR_BCTLC11 0x00030000 /* - " - */
1073#define SIUMCR_MMR00 0x00000000 /* Mask Masters Requests */
1074#define SIUMCR_MMR01 0x00004000 /* - " - */
1075#define SIUMCR_MMR10 0x00008000 /* - " - */
1076#define SIUMCR_MMR11 0x0000c000 /* - " - */
1077#define SIUMCR_LPBSE 0x00002000 /* LocalBus Parity Byte Select Enable*/
1078
1079/*-----------------------------------------------------------------------
1080 * SCCR - System Clock Control Register 9-8
1081*/
1082#define SCCR_PCI_MODE 0x00000100 /* PCI Mode */
1083#define SCCR_PCI_MODCK 0x00000080 /* Value of PCI_MODCK pin */
1084#define SCCR_PCIDF_MSK 0x00000078 /* PCI division factor */
1085#define SCCR_PCIDF_SHIFT 3
1086
1087
1042#endif /* __CPM2__ */ 1088#endif /* __CPM2__ */
1043#endif /* __KERNEL__ */ 1089#endif /* __KERNEL__ */
1044 1090
diff --git a/include/asm-ppc/fsl_ocp.h b/include/asm-ppc/fsl_ocp.h
deleted file mode 100644
index 050fbba8d049..000000000000
--- a/include/asm-ppc/fsl_ocp.h
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * include/asm-ppc/fsl_ocp.h
3 *
4 * Definitions for the on-chip peripherals on Freescale PPC processors
5 *
6 * Maintainer: Kumar Gala (kumar.gala@freescale.com)
7 *
8 * Copyright 2004 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_FS_OCP_H__
18#define __ASM_FS_OCP_H__
19
20/* A table of information for supporting the Gianfar Ethernet Controller
21 * This helps identify which enet controller we are dealing with,
22 * and what type of enet controller it is
23 */
24struct ocp_gfar_data {
25 uint interruptTransmit;
26 uint interruptError;
27 uint interruptReceive;
28 uint interruptPHY;
29 uint flags;
30 uint phyid;
31 uint phyregidx;
32 unsigned char mac_addr[6];
33};
34
35/* Flags in the flags field */
36#define GFAR_HAS_COALESCE 0x20
37#define GFAR_HAS_RMON 0x10
38#define GFAR_HAS_MULTI_INTR 0x08
39#define GFAR_FIRM_SET_MACADDR 0x04
40#define GFAR_HAS_PHY_INTR 0x02 /* if not set use a timer */
41#define GFAR_HAS_GIGABIT 0x01
42
43/* Data structure for I2C support. Just contains a couple flags
44 * to distinguish various I2C implementations*/
45struct ocp_fs_i2c_data {
46 uint flags;
47};
48
49/* Flags for I2C */
50#define FS_I2C_SEPARATE_DFSRR 0x02
51#define FS_I2C_CLOCK_5200 0x01
52
53#endif /* __ASM_FS_OCP_H__ */
54#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h
index 06b86be61ed1..a9b33324f562 100644
--- a/include/asm-ppc/irq.h
+++ b/include/asm-ppc/irq.h
@@ -176,7 +176,7 @@ static __inline__ int irq_canonicalize(int irq)
176*/ 176*/
177#include <asm/mpc85xx.h> 177#include <asm/mpc85xx.h>
178 178
179/* The MPC8560 openpic has 32 internal interrupts and 12 external 179/* The MPC8548 openpic has 48 internal interrupts and 12 external
180 * interrupts. 180 * interrupts.
181 * 181 *
182 * We are "flattening" the interrupt vectors of the cascaded CPM 182 * We are "flattening" the interrupt vectors of the cascaded CPM
@@ -184,7 +184,7 @@ static __inline__ int irq_canonicalize(int irq)
184 * single integer. 184 * single integer.
185 */ 185 */
186#define NR_CPM_INTS 64 186#define NR_CPM_INTS 64
187#define NR_EPIC_INTS 44 187#define NR_EPIC_INTS 60
188#ifndef NR_8259_INTS 188#ifndef NR_8259_INTS
189#define NR_8259_INTS 0 189#define NR_8259_INTS 0
190#endif 190#endif
@@ -223,9 +223,15 @@ static __inline__ int irq_canonicalize(int irq)
223#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) 223#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
224#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) 224#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
225#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) 225#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
226#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
227#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
228#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
226#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) 229#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
227#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) 230#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
228#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) 231#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
232#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
233#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
234#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
229#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) 235#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
230#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) 236#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
231#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) 237#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
@@ -235,18 +241,18 @@ static __inline__ int irq_canonicalize(int irq)
235#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) 241#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
236 242
237/* The 12 external interrupt lines */ 243/* The 12 external interrupt lines */
238#define MPC85xx_IRQ_EXT0 (32 + MPC85xx_OPENPIC_IRQ_OFFSET) 244#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
239#define MPC85xx_IRQ_EXT1 (33 + MPC85xx_OPENPIC_IRQ_OFFSET) 245#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
240#define MPC85xx_IRQ_EXT2 (34 + MPC85xx_OPENPIC_IRQ_OFFSET) 246#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
241#define MPC85xx_IRQ_EXT3 (35 + MPC85xx_OPENPIC_IRQ_OFFSET) 247#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
242#define MPC85xx_IRQ_EXT4 (36 + MPC85xx_OPENPIC_IRQ_OFFSET) 248#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
243#define MPC85xx_IRQ_EXT5 (37 + MPC85xx_OPENPIC_IRQ_OFFSET) 249#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
244#define MPC85xx_IRQ_EXT6 (38 + MPC85xx_OPENPIC_IRQ_OFFSET) 250#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
245#define MPC85xx_IRQ_EXT7 (39 + MPC85xx_OPENPIC_IRQ_OFFSET) 251#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
246#define MPC85xx_IRQ_EXT8 (40 + MPC85xx_OPENPIC_IRQ_OFFSET) 252#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
247#define MPC85xx_IRQ_EXT9 (41 + MPC85xx_OPENPIC_IRQ_OFFSET) 253#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
248#define MPC85xx_IRQ_EXT10 (42 + MPC85xx_OPENPIC_IRQ_OFFSET) 254#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
249#define MPC85xx_IRQ_EXT11 (43 + MPC85xx_OPENPIC_IRQ_OFFSET) 255#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
250 256
251/* CPM related interrupts */ 257/* CPM related interrupts */
252#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) 258#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
diff --git a/include/asm-ppc/kexec.h b/include/asm-ppc/kexec.h
new file mode 100644
index 000000000000..73191310d8db
--- /dev/null
+++ b/include/asm-ppc/kexec.h
@@ -0,0 +1,38 @@
1#ifndef _PPC_KEXEC_H
2#define _PPC_KEXEC_H
3
4#ifdef CONFIG_KEXEC
5
6/*
7 * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
8 * I.e. Maximum page that is mapped directly into kernel memory,
9 * and kmap is not required.
10 *
11 * Someone correct me if FIXADDR_START - PAGEOFFSET is not the correct
12 * calculation for the amount of memory directly mappable into the
13 * kernel memory space.
14 */
15
16/* Maximum physical address we can use pages from */
17#define KEXEC_SOURCE_MEMORY_LIMIT (-1UL)
18/* Maximum address we can reach in physical address mode */
19#define KEXEC_DESTINATION_MEMORY_LIMIT (-1UL)
20/* Maximum address we can use for the control code buffer */
21#define KEXEC_CONTROL_MEMORY_LIMIT TASK_SIZE
22
23#define KEXEC_CONTROL_CODE_SIZE 4096
24
25/* The native architecture */
26#define KEXEC_ARCH KEXEC_ARCH_PPC
27
28#ifndef __ASSEMBLY__
29
30struct kimage;
31
32extern void machine_kexec_simple(struct kimage *image);
33
34#endif /* __ASSEMBLY__ */
35
36#endif /* CONFIG_KEXEC */
37
38#endif /* _PPC_KEXEC_H */
diff --git a/include/asm-ppc/m8260_pci.h b/include/asm-ppc/m8260_pci.h
index 163a6b91d5b2..bf9e05dd54b5 100644
--- a/include/asm-ppc/m8260_pci.h
+++ b/include/asm-ppc/m8260_pci.h
@@ -19,6 +19,7 @@
19 * Define the vendor/device ID for the MPC8265. 19 * Define the vendor/device ID for the MPC8265.
20 */ 20 */
21#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA) 21#define PCI_DEVICE_ID_MPC8265 ((0x18C0 << 16) | PCI_VENDOR_ID_MOTOROLA)
22#define PCI_DEVICE_ID_MPC8272 ((0x18C1 << 16) | PCI_VENDOR_ID_MOTOROLA)
22 23
23#define M8265_PCIBR0 0x101ac 24#define M8265_PCIBR0 0x101ac
24#define M8265_PCIBR1 0x101b0 25#define M8265_PCIBR1 0x101b0
diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h
index b78d40870c95..1d4ab70a56f3 100644
--- a/include/asm-ppc/machdep.h
+++ b/include/asm-ppc/machdep.h
@@ -4,6 +4,7 @@
4 4
5#include <linux/config.h> 5#include <linux/config.h>
6#include <linux/init.h> 6#include <linux/init.h>
7#include <linux/kexec.h>
7 8
8#include <asm/setup.h> 9#include <asm/setup.h>
9#include <asm/page.h> 10#include <asm/page.h>
@@ -114,6 +115,36 @@ struct machdep_calls {
114 /* functions for dealing with other cpus */ 115 /* functions for dealing with other cpus */
115 struct smp_ops_t *smp_ops; 116 struct smp_ops_t *smp_ops;
116#endif /* CONFIG_SMP */ 117#endif /* CONFIG_SMP */
118
119#ifdef CONFIG_KEXEC
120 /* Called to shutdown machine specific hardware not already controlled
121 * by other drivers.
122 * XXX Should we move this one out of kexec scope?
123 */
124 void (*machine_shutdown)(void);
125
126 /* Called to do the minimal shutdown needed to run a kexec'd kernel
127 * to run successfully.
128 * XXX Should we move this one out of kexec scope?
129 */
130 void (*machine_crash_shutdown)(void);
131
132 /* Called to do what every setup is needed on image and the
133 * reboot code buffer. Returns 0 on success.
134 * Provide your own (maybe dummy) implementation if your platform
135 * claims to support kexec.
136 */
137 int (*machine_kexec_prepare)(struct kimage *image);
138
139 /* Called to handle any machine specific cleanup on image */
140 void (*machine_kexec_cleanup)(struct kimage *image);
141
142 /* Called to perform the _real_ kexec.
143 * Do NOT allocate memory or fail here. We are past the point of
144 * no return.
145 */
146 void (*machine_kexec)(struct kimage *image);
147#endif /* CONFIG_KEXEC */
117}; 148};
118 149
119extern struct machdep_calls ppc_md; 150extern struct machdep_calls ppc_md;
diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
index d465aee1c82e..9205db404c7a 100644
--- a/include/asm-ppc/mmu.h
+++ b/include/asm-ppc/mmu.h
@@ -405,7 +405,7 @@ typedef struct _P601_BAT {
405 405
406#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000) 406#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
407#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000) 407#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
408#define MAS0_NV 0x00000FFF 408#define MAS0_NV(x) ((x) & 0x00000FFF)
409 409
410#define MAS1_VALID 0x80000000 410#define MAS1_VALID 0x80000000
411#define MAS1_IPROT 0x40000000 411#define MAS1_IPROT 0x40000000
diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h
index 9222fa6ca172..ccabbce39d85 100644
--- a/include/asm-ppc/mmu_context.h
+++ b/include/asm-ppc/mmu_context.h
@@ -63,7 +63,7 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
63#define LAST_CONTEXT 255 63#define LAST_CONTEXT 255
64#define FIRST_CONTEXT 1 64#define FIRST_CONTEXT 1
65 65
66#elif defined(CONFIG_E500) 66#elif defined(CONFIG_E200) || defined(CONFIG_E500)
67#define NO_CONTEXT 256 67#define NO_CONTEXT 256
68#define LAST_CONTEXT 255 68#define LAST_CONTEXT 255
69#define FIRST_CONTEXT 1 69#define FIRST_CONTEXT 1
diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h
index d8e7e2d6128e..f5196a4efbe0 100644
--- a/include/asm-ppc/mpc10x.h
+++ b/include/asm-ppc/mpc10x.h
@@ -159,6 +159,12 @@ extern unsigned long ioremap_base;
159#define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE) 159#define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE)
160#define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE 160#define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE
161 161
162enum ppc_sys_devices {
163 MPC10X_IIC1,
164 MPC10X_DMA0,
165 MPC10X_DMA1,
166 MPC10X_DUART,
167};
162 168
163int mpc10x_bridge_init(struct pci_controller *hose, 169int mpc10x_bridge_init(struct pci_controller *hose,
164 uint current_map, 170 uint current_map,
diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h
index d820894e5991..89eb8a2ac693 100644
--- a/include/asm-ppc/mpc8260.h
+++ b/include/asm-ppc/mpc8260.h
@@ -41,7 +41,7 @@
41#endif 41#endif
42 42
43#ifdef CONFIG_PCI_8260 43#ifdef CONFIG_PCI_8260
44#include <syslib/m8260_pci.h> 44#include <syslib/m82xx_pci.h>
45#endif 45#endif
46 46
47/* Make sure the memory translation stuff is there if PCI not used. 47/* Make sure the memory translation stuff is there if PCI not used.
diff --git a/include/asm-ppc/mpc85xx.h b/include/asm-ppc/mpc85xx.h
index 22713e331585..516984ee14b5 100644
--- a/include/asm-ppc/mpc85xx.h
+++ b/include/asm-ppc/mpc85xx.h
@@ -25,7 +25,7 @@
25#ifdef CONFIG_MPC8540_ADS 25#ifdef CONFIG_MPC8540_ADS
26#include <platforms/85xx/mpc8540_ads.h> 26#include <platforms/85xx/mpc8540_ads.h>
27#endif 27#endif
28#ifdef CONFIG_MPC8555_CDS 28#if defined(CONFIG_MPC8555_CDS) || defined(CONFIG_MPC8548_CDS)
29#include <platforms/85xx/mpc8555_cds.h> 29#include <platforms/85xx/mpc8555_cds.h>
30#endif 30#endif
31#ifdef CONFIG_MPC8560_ADS 31#ifdef CONFIG_MPC8560_ADS
@@ -74,7 +74,7 @@ extern unsigned char __res[];
74#define MPC85xx_GUTS_OFFSET (0xe0000) 74#define MPC85xx_GUTS_OFFSET (0xe0000)
75#define MPC85xx_GUTS_SIZE (0x01000) 75#define MPC85xx_GUTS_SIZE (0x01000)
76#define MPC85xx_IIC1_OFFSET (0x03000) 76#define MPC85xx_IIC1_OFFSET (0x03000)
77#define MPC85xx_IIC1_SIZE (0x01000) 77#define MPC85xx_IIC1_SIZE (0x00100)
78#define MPC85xx_OPENPIC_OFFSET (0x40000) 78#define MPC85xx_OPENPIC_OFFSET (0x40000)
79#define MPC85xx_OPENPIC_SIZE (0x40000) 79#define MPC85xx_OPENPIC_SIZE (0x40000)
80#define MPC85xx_PCI1_OFFSET (0x08000) 80#define MPC85xx_PCI1_OFFSET (0x08000)
@@ -127,8 +127,64 @@ enum ppc_sys_devices {
127 MPC85xx_CPM_MCC2, 127 MPC85xx_CPM_MCC2,
128 MPC85xx_CPM_SMC1, 128 MPC85xx_CPM_SMC1,
129 MPC85xx_CPM_SMC2, 129 MPC85xx_CPM_SMC2,
130 MPC85xx_eTSEC1,
131 MPC85xx_eTSEC2,
132 MPC85xx_eTSEC3,
133 MPC85xx_eTSEC4,
134 MPC85xx_IIC2,
130}; 135};
131 136
137/* Internal interrupts are all Level Sensitive, and Positive Polarity */
138#define MPC85XX_INTERNAL_IRQ_SENSES \
139 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 0 */ \
140 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 1 */ \
141 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 2 */ \
142 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 3 */ \
143 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 4 */ \
144 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 5 */ \
145 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 6 */ \
146 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 7 */ \
147 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 8 */ \
148 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 9 */ \
149 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 10 */ \
150 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 11 */ \
151 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 12 */ \
152 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 13 */ \
153 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 14 */ \
154 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 15 */ \
155 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 16 */ \
156 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 17 */ \
157 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 18 */ \
158 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 19 */ \
159 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 20 */ \
160 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 21 */ \
161 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 22 */ \
162 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 23 */ \
163 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 24 */ \
164 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 25 */ \
165 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 26 */ \
166 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 27 */ \
167 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 28 */ \
168 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 29 */ \
169 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 30 */ \
170 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 31 */ \
171 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 32 */ \
172 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 33 */ \
173 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 34 */ \
174 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 35 */ \
175 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 36 */ \
176 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 37 */ \
177 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 38 */ \
178 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 39 */ \
179 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 40 */ \
180 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 41 */ \
181 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 42 */ \
182 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 43 */ \
183 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 44 */ \
184 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 45 */ \
185 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE), /* Internal 46 */ \
186 (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE) /* Internal 47 */
187
132#endif /* CONFIG_85xx */ 188#endif /* CONFIG_85xx */
133#endif /* __ASM_MPC85xx_H__ */ 189#endif /* __ASM_MPC85xx_H__ */
134#endif /* __KERNEL__ */ 190#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/ocp.h b/include/asm-ppc/ocp.h
index b98db3cdae83..983116f59d90 100644
--- a/include/asm-ppc/ocp.h
+++ b/include/asm-ppc/ocp.h
@@ -189,7 +189,7 @@ extern void ocp_for_each_device(void(*callback)(struct ocp_device *, void *arg),
189/* Sysfs support */ 189/* Sysfs support */
190#define OCP_SYSFS_ADDTL(type, format, name, field) \ 190#define OCP_SYSFS_ADDTL(type, format, name, field) \
191static ssize_t \ 191static ssize_t \
192show_##name##_##field(struct device *dev, char *buf) \ 192show_##name##_##field(struct device *dev, struct device_attribute *attr, char *buf) \
193{ \ 193{ \
194 struct ocp_device *odev = to_ocp_dev(dev); \ 194 struct ocp_device *odev = to_ocp_dev(dev); \
195 type *add = odev->def->additions; \ 195 type *add = odev->def->additions; \
@@ -202,10 +202,6 @@ static DEVICE_ATTR(name##_##field, S_IRUGO, show_##name##_##field, NULL);
202#include <asm/ibm_ocp.h> 202#include <asm/ibm_ocp.h>
203#endif 203#endif
204 204
205#ifdef CONFIG_FSL_OCP
206#include <asm/fsl_ocp.h>
207#endif
208
209#endif /* CONFIG_PPC_OCP */ 205#endif /* CONFIG_PPC_OCP */
210#endif /* __OCP_H__ */ 206#endif /* __OCP_H__ */
211#endif /* __KERNEL__ */ 207#endif /* __KERNEL__ */
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index a38606d15549..4d4b20c9de78 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -267,8 +267,6 @@ extern unsigned long ioremap_bot, ioremap_base;
267#define _PMD_PRESENT_MASK (PAGE_MASK) 267#define _PMD_PRESENT_MASK (PAGE_MASK)
268#define _PMD_BAD (~PAGE_MASK) 268#define _PMD_BAD (~PAGE_MASK)
269 269
270#define NUM_TLBCAMS (16)
271
272#elif defined(CONFIG_8xx) 270#elif defined(CONFIG_8xx)
273/* Definitions for 8xx embedded chips. */ 271/* Definitions for 8xx embedded chips. */
274#define _PAGE_PRESENT 0x0001 /* Page is valid */ 272#define _PAGE_PRESENT 0x0001 /* Page is valid */
diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h
index 13fa8e7483c1..f76221def484 100644
--- a/include/asm-ppc/ppc_asm.h
+++ b/include/asm-ppc/ppc_asm.h
@@ -174,6 +174,8 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
174#define CLR_TOP32(r) 174#define CLR_TOP32(r)
175#endif /* CONFIG_PPC64BRIDGE */ 175#endif /* CONFIG_PPC64BRIDGE */
176 176
177#define RFCI .long 0x4c000066 /* rfci instruction */
178#define RFDI .long 0x4c00004e /* rfdi instruction */
177#define RFMCI .long 0x4c00004c /* rfmci instruction */ 179#define RFMCI .long 0x4c00004c /* rfmci instruction */
178 180
179#ifdef CONFIG_IBM405_ERR77 181#ifdef CONFIG_IBM405_ERR77
diff --git a/include/asm-ppc/ppc_sys.h b/include/asm-ppc/ppc_sys.h
index 24b991c42769..8ea624566231 100644
--- a/include/asm-ppc/ppc_sys.h
+++ b/include/asm-ppc/ppc_sys.h
@@ -27,6 +27,8 @@
27#include <asm/mpc85xx.h> 27#include <asm/mpc85xx.h>
28#elif defined(CONFIG_PPC_MPC52xx) 28#elif defined(CONFIG_PPC_MPC52xx)
29#include <asm/mpc52xx.h> 29#include <asm/mpc52xx.h>
30#elif defined(CONFIG_MPC10X_BRIDGE)
31#include <asm/mpc10x.h>
30#else 32#else
31#error "need definition of ppc_sys_devices" 33#error "need definition of ppc_sys_devices"
32#endif 34#endif
diff --git a/include/asm-ppc/reg.h b/include/asm-ppc/reg.h
index c418aab7cd34..88b4222154d4 100644
--- a/include/asm-ppc/reg.h
+++ b/include/asm-ppc/reg.h
@@ -160,6 +160,7 @@
160#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */ 160#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
161#define HID0_DCI (1<<10) /* Data Cache Invalidate */ 161#define HID0_DCI (1<<10) /* Data Cache Invalidate */
162#define HID0_SPD (1<<9) /* Speculative disable */ 162#define HID0_SPD (1<<9) /* Speculative disable */
163#define HID0_DAPUEN (1<<8) /* Debug APU enable */
163#define HID0_SGE (1<<7) /* Store Gathering Enable */ 164#define HID0_SGE (1<<7) /* Store Gathering Enable */
164#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ 165#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
165#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ 166#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h
index 45c5e6f2b7ab..00ad9c754c78 100644
--- a/include/asm-ppc/reg_booke.h
+++ b/include/asm-ppc/reg_booke.h
@@ -165,6 +165,8 @@ do { \
165#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 165#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
166#define SPRN_MCSR 0x23C /* Machine Check Status Register */ 166#define SPRN_MCSR 0x23C /* Machine Check Status Register */
167#define SPRN_MCAR 0x23D /* Machine Check Address Register */ 167#define SPRN_MCAR 0x23D /* Machine Check Address Register */
168#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
169#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
168#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 170#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
169#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 171#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
170#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 172#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
@@ -264,6 +266,17 @@ do { \
264#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ 266#define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
265#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ 267#define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
266#endif 268#endif
269#ifdef CONFIG_E200
270#define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
271#define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */
272#define MCSR_CPERR 0x10000000UL /* Cache Parity Error */
273#define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn
274 fetch for an exception handler */
275#define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/
276#define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */
277#define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered
278 store or cache line push */
279#endif
267 280
268/* Bit definitions for the DBSR. */ 281/* Bit definitions for the DBSR. */
269/* 282/*
@@ -311,6 +324,7 @@ do { \
311#define ESR_ST 0x00800000 /* Store Operation */ 324#define ESR_ST 0x00800000 /* Store Operation */
312#define ESR_DLK 0x00200000 /* Data Cache Locking */ 325#define ESR_DLK 0x00200000 /* Data Cache Locking */
313#define ESR_ILK 0x00100000 /* Instr. Cache Locking */ 326#define ESR_ILK 0x00100000 /* Instr. Cache Locking */
327#define ESR_PUO 0x00040000 /* Unimplemented Operation exception */
314#define ESR_BO 0x00020000 /* Byte Ordering */ 328#define ESR_BO 0x00020000 /* Byte Ordering */
315 329
316/* Bit definitions related to the DBCR0. */ 330/* Bit definitions related to the DBCR0. */
@@ -387,10 +401,12 @@ do { \
387#define ICCR_CACHE 1 /* Cacheable */ 401#define ICCR_CACHE 1 /* Cacheable */
388 402
389/* Bit definitions for L1CSR0. */ 403/* Bit definitions for L1CSR0. */
404#define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */
390#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 405#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
406#define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */
391#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 407#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
392 408
393/* Bit definitions for L1CSR0. */ 409/* Bit definitions for L1CSR1. */
394#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ 410#define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
395#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ 411#define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
396#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ 412#define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
diff --git a/include/asm-ppc/seccomp.h b/include/asm-ppc/seccomp.h
new file mode 100644
index 000000000000..666c4da96d87
--- /dev/null
+++ b/include/asm-ppc/seccomp.h
@@ -0,0 +1,10 @@
1#ifndef _ASM_SECCOMP_H
2
3#include <linux/unistd.h>
4
5#define __NR_seccomp_read __NR_read
6#define __NR_seccomp_write __NR_write
7#define __NR_seccomp_exit __NR_exit
8#define __NR_seccomp_sigreturn __NR_rt_sigreturn
9
10#endif /* _ASM_SECCOMP_H */
diff --git a/include/asm-ppc/sigcontext.h b/include/asm-ppc/sigcontext.h
index f82dcccdee1e..b7a417e0a921 100644
--- a/include/asm-ppc/sigcontext.h
+++ b/include/asm-ppc/sigcontext.h
@@ -2,7 +2,7 @@
2#define _ASM_PPC_SIGCONTEXT_H 2#define _ASM_PPC_SIGCONTEXT_H
3 3
4#include <asm/ptrace.h> 4#include <asm/ptrace.h>
5 5#include <linux/compiler.h>
6 6
7struct sigcontext { 7struct sigcontext {
8 unsigned long _unused[4]; 8 unsigned long _unused[4];
diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h
index ebfb614f55f6..17530c232c76 100644
--- a/include/asm-ppc/smp.h
+++ b/include/asm-ppc/smp.h
@@ -44,7 +44,7 @@ extern void smp_message_recv(int, struct pt_regs *);
44#define NO_PROC_ID 0xFF /* No processor magic marker */ 44#define NO_PROC_ID 0xFF /* No processor magic marker */
45#define PROC_CHANGE_PENALTY 20 45#define PROC_CHANGE_PENALTY 20
46 46
47#define smp_processor_id() (current_thread_info()->cpu) 47#define raw_smp_processor_id() (current_thread_info()->cpu)
48 48
49extern int __cpu_up(unsigned int cpu); 49extern int __cpu_up(unsigned int cpu);
50 50
diff --git a/include/asm-ppc/thread_info.h b/include/asm-ppc/thread_info.h
index f7f01524e8a8..27903db42efc 100644
--- a/include/asm-ppc/thread_info.h
+++ b/include/asm-ppc/thread_info.h
@@ -20,7 +20,8 @@ struct thread_info {
20 unsigned long flags; /* low level flags */ 20 unsigned long flags; /* low level flags */
21 unsigned long local_flags; /* non-racy flags */ 21 unsigned long local_flags; /* non-racy flags */
22 int cpu; /* cpu we're on */ 22 int cpu; /* cpu we're on */
23 int preempt_count; 23 int preempt_count; /* 0 => preemptable,
24 <0 => BUG */
24 struct restart_block restart_block; 25 struct restart_block restart_block;
25}; 26};
26 27
@@ -77,12 +78,19 @@ static inline struct thread_info *current_thread_info(void)
77#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling 78#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling
78 TIF_NEED_RESCHED */ 79 TIF_NEED_RESCHED */
79#define TIF_MEMDIE 5 80#define TIF_MEMDIE 5
81#define TIF_SYSCALL_AUDIT 6 /* syscall auditing active */
82#define TIF_SECCOMP 7 /* secure computing */
83
80/* as above, but as bit values */ 84/* as above, but as bit values */
81#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) 85#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
82#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) 86#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
83#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) 87#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
84#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) 88#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
85#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) 89#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
90#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
91#define _TIF_SECCOMP (1<<TIF_SECCOMP)
92
93#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
86 94
87/* 95/*
88 * Non racy (local) flags bit numbers 96 * Non racy (local) flags bit numbers
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 09:39:19 -0500