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-rw-r--r--include/asm-ppc64/atomic.h197
-rw-r--r--include/asm-ppc64/bitops.h2
-rw-r--r--include/asm-ppc64/futex.h2
-rw-r--r--include/asm-ppc64/io.h2
-rw-r--r--include/asm-ppc64/memory.h61
-rw-r--r--include/asm-ppc64/processor.h8
-rw-r--r--include/asm-ppc64/system.h4
7 files changed, 13 insertions, 263 deletions
diff --git a/include/asm-ppc64/atomic.h b/include/asm-ppc64/atomic.h
deleted file mode 100644
index 0e5f25e83bc0..000000000000
--- a/include/asm-ppc64/atomic.h
+++ /dev/null
@@ -1,197 +0,0 @@
1/*
2 * PowerPC64 atomic operations
3 *
4 * Copyright (C) 2001 Paul Mackerras <paulus@au.ibm.com>, IBM
5 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifndef _ASM_PPC64_ATOMIC_H_
14#define _ASM_PPC64_ATOMIC_H_
15
16#include <asm/memory.h>
17
18typedef struct { volatile int counter; } atomic_t;
19
20#define ATOMIC_INIT(i) { (i) }
21
22#define atomic_read(v) ((v)->counter)
23#define atomic_set(v,i) (((v)->counter) = (i))
24
25static __inline__ void atomic_add(int a, atomic_t *v)
26{
27 int t;
28
29 __asm__ __volatile__(
30"1: lwarx %0,0,%3 # atomic_add\n\
31 add %0,%2,%0\n\
32 stwcx. %0,0,%3\n\
33 bne- 1b"
34 : "=&r" (t), "=m" (v->counter)
35 : "r" (a), "r" (&v->counter), "m" (v->counter)
36 : "cc");
37}
38
39static __inline__ int atomic_add_return(int a, atomic_t *v)
40{
41 int t;
42
43 __asm__ __volatile__(
44 EIEIO_ON_SMP
45"1: lwarx %0,0,%2 # atomic_add_return\n\
46 add %0,%1,%0\n\
47 stwcx. %0,0,%2\n\
48 bne- 1b"
49 ISYNC_ON_SMP
50 : "=&r" (t)
51 : "r" (a), "r" (&v->counter)
52 : "cc", "memory");
53
54 return t;
55}
56
57#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
58
59static __inline__ void atomic_sub(int a, atomic_t *v)
60{
61 int t;
62
63 __asm__ __volatile__(
64"1: lwarx %0,0,%3 # atomic_sub\n\
65 subf %0,%2,%0\n\
66 stwcx. %0,0,%3\n\
67 bne- 1b"
68 : "=&r" (t), "=m" (v->counter)
69 : "r" (a), "r" (&v->counter), "m" (v->counter)
70 : "cc");
71}
72
73static __inline__ int atomic_sub_return(int a, atomic_t *v)
74{
75 int t;
76
77 __asm__ __volatile__(
78 EIEIO_ON_SMP
79"1: lwarx %0,0,%2 # atomic_sub_return\n\
80 subf %0,%1,%0\n\
81 stwcx. %0,0,%2\n\
82 bne- 1b"
83 ISYNC_ON_SMP
84 : "=&r" (t)
85 : "r" (a), "r" (&v->counter)
86 : "cc", "memory");
87
88 return t;
89}
90
91static __inline__ void atomic_inc(atomic_t *v)
92{
93 int t;
94
95 __asm__ __volatile__(
96"1: lwarx %0,0,%2 # atomic_inc\n\
97 addic %0,%0,1\n\
98 stwcx. %0,0,%2\n\
99 bne- 1b"
100 : "=&r" (t), "=m" (v->counter)
101 : "r" (&v->counter), "m" (v->counter)
102 : "cc");
103}
104
105static __inline__ int atomic_inc_return(atomic_t *v)
106{
107 int t;
108
109 __asm__ __volatile__(
110 EIEIO_ON_SMP
111"1: lwarx %0,0,%1 # atomic_inc_return\n\
112 addic %0,%0,1\n\
113 stwcx. %0,0,%1\n\
114 bne- 1b"
115 ISYNC_ON_SMP
116 : "=&r" (t)
117 : "r" (&v->counter)
118 : "cc", "memory");
119
120 return t;
121}
122
123/*
124 * atomic_inc_and_test - increment and test
125 * @v: pointer of type atomic_t
126 *
127 * Atomically increments @v by 1
128 * and returns true if the result is zero, or false for all
129 * other cases.
130 */
131#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
132
133static __inline__ void atomic_dec(atomic_t *v)
134{
135 int t;
136
137 __asm__ __volatile__(
138"1: lwarx %0,0,%2 # atomic_dec\n\
139 addic %0,%0,-1\n\
140 stwcx. %0,0,%2\n\
141 bne- 1b"
142 : "=&r" (t), "=m" (v->counter)
143 : "r" (&v->counter), "m" (v->counter)
144 : "cc");
145}
146
147static __inline__ int atomic_dec_return(atomic_t *v)
148{
149 int t;
150
151 __asm__ __volatile__(
152 EIEIO_ON_SMP
153"1: lwarx %0,0,%1 # atomic_dec_return\n\
154 addic %0,%0,-1\n\
155 stwcx. %0,0,%1\n\
156 bne- 1b"
157 ISYNC_ON_SMP
158 : "=&r" (t)
159 : "r" (&v->counter)
160 : "cc", "memory");
161
162 return t;
163}
164
165#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
166#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
167
168/*
169 * Atomically test *v and decrement if it is greater than 0.
170 * The function returns the old value of *v minus 1.
171 */
172static __inline__ int atomic_dec_if_positive(atomic_t *v)
173{
174 int t;
175
176 __asm__ __volatile__(
177 EIEIO_ON_SMP
178"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
179 addic. %0,%0,-1\n\
180 blt- 2f\n\
181 stwcx. %0,0,%1\n\
182 bne- 1b"
183 ISYNC_ON_SMP
184 "\n\
1852:" : "=&r" (t)
186 : "r" (&v->counter)
187 : "cc", "memory");
188
189 return t;
190}
191
192#define smp_mb__before_atomic_dec() smp_mb()
193#define smp_mb__after_atomic_dec() smp_mb()
194#define smp_mb__before_atomic_inc() smp_mb()
195#define smp_mb__after_atomic_inc() smp_mb()
196
197#endif /* _ASM_PPC64_ATOMIC_H_ */
diff --git a/include/asm-ppc64/bitops.h b/include/asm-ppc64/bitops.h
index a0f831224f96..dbfa42ef4a99 100644
--- a/include/asm-ppc64/bitops.h
+++ b/include/asm-ppc64/bitops.h
@@ -42,7 +42,7 @@
42 42
43#ifdef __KERNEL__ 43#ifdef __KERNEL__
44 44
45#include <asm/memory.h> 45#include <asm/synch.h>
46 46
47/* 47/*
48 * clear_bit doesn't imply a memory barrier 48 * clear_bit doesn't imply a memory barrier
diff --git a/include/asm-ppc64/futex.h b/include/asm-ppc64/futex.h
index cb2640b3a408..266b460de44e 100644
--- a/include/asm-ppc64/futex.h
+++ b/include/asm-ppc64/futex.h
@@ -5,7 +5,7 @@
5 5
6#include <linux/futex.h> 6#include <linux/futex.h>
7#include <asm/errno.h> 7#include <asm/errno.h>
8#include <asm/memory.h> 8#include <asm/synch.h>
9#include <asm/uaccess.h> 9#include <asm/uaccess.h>
10 10
11#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 11#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
diff --git a/include/asm-ppc64/io.h b/include/asm-ppc64/io.h
index 59c958aea4db..bd7c9532d77b 100644
--- a/include/asm-ppc64/io.h
+++ b/include/asm-ppc64/io.h
@@ -15,7 +15,7 @@
15#ifdef CONFIG_PPC_ISERIES 15#ifdef CONFIG_PPC_ISERIES
16#include <asm/iSeries/iSeries_io.h> 16#include <asm/iSeries/iSeries_io.h>
17#endif 17#endif
18#include <asm/memory.h> 18#include <asm/synch.h>
19#include <asm/delay.h> 19#include <asm/delay.h>
20 20
21#include <asm-generic/iomap.h> 21#include <asm-generic/iomap.h>
diff --git a/include/asm-ppc64/memory.h b/include/asm-ppc64/memory.h
deleted file mode 100644
index af53ffb55726..000000000000
--- a/include/asm-ppc64/memory.h
+++ /dev/null
@@ -1,61 +0,0 @@
1#ifndef _ASM_PPC64_MEMORY_H_
2#define _ASM_PPC64_MEMORY_H_
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <linux/config.h>
12
13/*
14 * Arguably the bitops and *xchg operations don't imply any memory barrier
15 * or SMP ordering, but in fact a lot of drivers expect them to imply
16 * both, since they do on x86 cpus.
17 */
18#ifdef CONFIG_SMP
19#define EIEIO_ON_SMP "eieio\n"
20#define ISYNC_ON_SMP "\n\tisync"
21#define SYNC_ON_SMP "lwsync\n\t"
22#else
23#define EIEIO_ON_SMP
24#define ISYNC_ON_SMP
25#define SYNC_ON_SMP
26#endif
27
28static inline void eieio(void)
29{
30 __asm__ __volatile__ ("eieio" : : : "memory");
31}
32
33static inline void isync(void)
34{
35 __asm__ __volatile__ ("isync" : : : "memory");
36}
37
38#ifdef CONFIG_SMP
39#define eieio_on_smp() eieio()
40#define isync_on_smp() isync()
41#else
42#define eieio_on_smp() __asm__ __volatile__("": : :"memory")
43#define isync_on_smp() __asm__ __volatile__("": : :"memory")
44#endif
45
46/* Macros for adjusting thread priority (hardware multi-threading) */
47#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
48#define HMT_low() asm volatile("or 1,1,1 # low priority")
49#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
50#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
51#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
52#define HMT_high() asm volatile("or 3,3,3 # high priority")
53
54#define HMT_VERY_LOW "\tor 31,31,31 # very low priority\n"
55#define HMT_LOW "\tor 1,1,1 # low priority\n"
56#define HMT_MEDIUM_LOW "\tor 6,6,6 # medium low priority\n"
57#define HMT_MEDIUM "\tor 2,2,2 # medium priority\n"
58#define HMT_MEDIUM_HIGH "\tor 5,5,5 # medium high priority\n"
59#define HMT_HIGH "\tor 3,3,3 # high priority\n"
60
61#endif
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
index 4146189006e3..e5fc18531ec1 100644
--- a/include/asm-ppc64/processor.h
+++ b/include/asm-ppc64/processor.h
@@ -368,6 +368,14 @@ GLUE(.,name):
368#define mfasr() ({unsigned long rval; \ 368#define mfasr() ({unsigned long rval; \
369 asm volatile("mfasr %0" : "=r" (rval)); rval;}) 369 asm volatile("mfasr %0" : "=r" (rval)); rval;})
370 370
371/* Macros for adjusting thread priority (hardware multi-threading) */
372#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
373#define HMT_low() asm volatile("or 1,1,1 # low priority")
374#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
375#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
376#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
377#define HMT_high() asm volatile("or 3,3,3 # high priority")
378
371static inline void set_tb(unsigned int upper, unsigned int lower) 379static inline void set_tb(unsigned int upper, unsigned int lower)
372{ 380{
373 mttbl(0); 381 mttbl(0);
diff --git a/include/asm-ppc64/system.h b/include/asm-ppc64/system.h
index 375015c62f20..1fbdc9f0590c 100644
--- a/include/asm-ppc64/system.h
+++ b/include/asm-ppc64/system.h
@@ -13,7 +13,7 @@
13#include <asm/page.h> 13#include <asm/page.h>
14#include <asm/processor.h> 14#include <asm/processor.h>
15#include <asm/hw_irq.h> 15#include <asm/hw_irq.h>
16#include <asm/memory.h> 16#include <asm/synch.h>
17 17
18/* 18/*
19 * Memory barrier. 19 * Memory barrier.
@@ -48,7 +48,7 @@
48#ifdef CONFIG_SMP 48#ifdef CONFIG_SMP
49#define smp_mb() mb() 49#define smp_mb() mb()
50#define smp_rmb() rmb() 50#define smp_rmb() rmb()
51#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory") 51#define smp_wmb() eieio()
52#define smp_read_barrier_depends() read_barrier_depends() 52#define smp_read_barrier_depends() read_barrier_depends()
53#else 53#else
54#define smp_mb() __asm__ __volatile__("": : :"memory") 54#define smp_mb() __asm__ __volatile__("": : :"memory")
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