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-rw-r--r--include/asm-ppc64/a.out.h39
-rw-r--r--include/asm-ppc64/atomic.h197
-rw-r--r--include/asm-ppc64/auxvec.h19
-rw-r--r--include/asm-ppc64/bitops.h2
-rw-r--r--include/asm-ppc64/bug.h69
-rw-r--r--include/asm-ppc64/byteorder.h86
-rw-r--r--include/asm-ppc64/cputable.h167
-rw-r--r--include/asm-ppc64/dart.h59
-rw-r--r--include/asm-ppc64/dma.h329
-rw-r--r--include/asm-ppc64/elf.h387
-rw-r--r--include/asm-ppc64/futex.h2
-rw-r--r--include/asm-ppc64/hardirq.h27
-rw-r--r--include/asm-ppc64/hw_irq.h104
-rw-r--r--include/asm-ppc64/iSeries/HvCallSm.h38
-rw-r--r--include/asm-ppc64/iSeries/HvReleaseData.h64
-rw-r--r--include/asm-ppc64/iSeries/IoHriMainStore.h166
-rw-r--r--include/asm-ppc64/iSeries/IoHriProcessorVpd.h86
-rw-r--r--include/asm-ppc64/iSeries/ItIplParmsReal.h71
-rw-r--r--include/asm-ppc64/iSeries/ItSpCommArea.h37
-rw-r--r--include/asm-ppc64/iSeries/ItVpdAreas.h89
-rw-r--r--include/asm-ppc64/iSeries/iSeries_irq.h8
-rw-r--r--include/asm-ppc64/iSeries/iSeries_pci.h30
-rw-r--r--include/asm-ppc64/io.h2
-rw-r--r--include/asm-ppc64/iommu.h40
-rw-r--r--include/asm-ppc64/irq.h120
-rw-r--r--include/asm-ppc64/kdebug.h43
-rw-r--r--include/asm-ppc64/kmap_types.h23
-rw-r--r--include/asm-ppc64/kprobes.h67
-rw-r--r--include/asm-ppc64/lmb.h81
-rw-r--r--include/asm-ppc64/machdep.h5
-rw-r--r--include/asm-ppc64/memory.h61
-rw-r--r--include/asm-ppc64/mmu.h7
-rw-r--r--include/asm-ppc64/of_device.h2
-rw-r--r--include/asm-ppc64/oprofile_impl.h111
-rw-r--r--include/asm-ppc64/page.h8
-rw-r--r--include/asm-ppc64/pci-bridge.h22
-rw-r--r--include/asm-ppc64/posix_types.h119
-rw-r--r--include/asm-ppc64/ppc_asm.h242
-rw-r--r--include/asm-ppc64/processor.h558
-rw-r--r--include/asm-ppc64/prom.h3
-rw-r--r--include/asm-ppc64/rwsem.h167
-rw-r--r--include/asm-ppc64/seccomp.h21
-rw-r--r--include/asm-ppc64/sections.h29
-rw-r--r--include/asm-ppc64/semaphore.h98
-rw-r--r--include/asm-ppc64/spinlock_types.h20
-rw-r--r--include/asm-ppc64/statfs.h61
-rw-r--r--include/asm-ppc64/system.h15
-rw-r--r--include/asm-ppc64/tce.h64
-rw-r--r--include/asm-ppc64/thread_info.h6
-rw-r--r--include/asm-ppc64/tlbflush.h7
-rw-r--r--include/asm-ppc64/unistd.h487
-rw-r--r--include/asm-ppc64/vga.h50
52 files changed, 180 insertions, 4435 deletions
diff --git a/include/asm-ppc64/a.out.h b/include/asm-ppc64/a.out.h
deleted file mode 100644
index 3871e252a6f1..000000000000
--- a/include/asm-ppc64/a.out.h
+++ /dev/null
@@ -1,39 +0,0 @@
1#ifndef __PPC64_A_OUT_H__
2#define __PPC64_A_OUT_H__
3
4/*
5 * c 2001 PPC 64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13struct exec
14{
15 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
16 unsigned a_text; /* length of text, in bytes */
17 unsigned a_data; /* length of data, in bytes */
18 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
19 unsigned a_syms; /* length of symbol table data in file, in bytes */
20 unsigned a_entry; /* start address */
21 unsigned a_trsize; /* length of relocation info for text, in bytes */
22 unsigned a_drsize; /* length of relocation info for data, in bytes */
23};
24
25#define N_TRSIZE(a) ((a).a_trsize)
26#define N_DRSIZE(a) ((a).a_drsize)
27#define N_SYMSIZE(a) ((a).a_syms)
28
29#ifdef __KERNEL__
30
31#define STACK_TOP_USER64 TASK_SIZE_USER64
32#define STACK_TOP_USER32 TASK_SIZE_USER32
33
34#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
35 STACK_TOP_USER32 : STACK_TOP_USER64)
36
37#endif /* __KERNEL__ */
38
39#endif /* __PPC64_A_OUT_H__ */
diff --git a/include/asm-ppc64/atomic.h b/include/asm-ppc64/atomic.h
deleted file mode 100644
index 0e5f25e83bc0..000000000000
--- a/include/asm-ppc64/atomic.h
+++ /dev/null
@@ -1,197 +0,0 @@
1/*
2 * PowerPC64 atomic operations
3 *
4 * Copyright (C) 2001 Paul Mackerras <paulus@au.ibm.com>, IBM
5 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifndef _ASM_PPC64_ATOMIC_H_
14#define _ASM_PPC64_ATOMIC_H_
15
16#include <asm/memory.h>
17
18typedef struct { volatile int counter; } atomic_t;
19
20#define ATOMIC_INIT(i) { (i) }
21
22#define atomic_read(v) ((v)->counter)
23#define atomic_set(v,i) (((v)->counter) = (i))
24
25static __inline__ void atomic_add(int a, atomic_t *v)
26{
27 int t;
28
29 __asm__ __volatile__(
30"1: lwarx %0,0,%3 # atomic_add\n\
31 add %0,%2,%0\n\
32 stwcx. %0,0,%3\n\
33 bne- 1b"
34 : "=&r" (t), "=m" (v->counter)
35 : "r" (a), "r" (&v->counter), "m" (v->counter)
36 : "cc");
37}
38
39static __inline__ int atomic_add_return(int a, atomic_t *v)
40{
41 int t;
42
43 __asm__ __volatile__(
44 EIEIO_ON_SMP
45"1: lwarx %0,0,%2 # atomic_add_return\n\
46 add %0,%1,%0\n\
47 stwcx. %0,0,%2\n\
48 bne- 1b"
49 ISYNC_ON_SMP
50 : "=&r" (t)
51 : "r" (a), "r" (&v->counter)
52 : "cc", "memory");
53
54 return t;
55}
56
57#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
58
59static __inline__ void atomic_sub(int a, atomic_t *v)
60{
61 int t;
62
63 __asm__ __volatile__(
64"1: lwarx %0,0,%3 # atomic_sub\n\
65 subf %0,%2,%0\n\
66 stwcx. %0,0,%3\n\
67 bne- 1b"
68 : "=&r" (t), "=m" (v->counter)
69 : "r" (a), "r" (&v->counter), "m" (v->counter)
70 : "cc");
71}
72
73static __inline__ int atomic_sub_return(int a, atomic_t *v)
74{
75 int t;
76
77 __asm__ __volatile__(
78 EIEIO_ON_SMP
79"1: lwarx %0,0,%2 # atomic_sub_return\n\
80 subf %0,%1,%0\n\
81 stwcx. %0,0,%2\n\
82 bne- 1b"
83 ISYNC_ON_SMP
84 : "=&r" (t)
85 : "r" (a), "r" (&v->counter)
86 : "cc", "memory");
87
88 return t;
89}
90
91static __inline__ void atomic_inc(atomic_t *v)
92{
93 int t;
94
95 __asm__ __volatile__(
96"1: lwarx %0,0,%2 # atomic_inc\n\
97 addic %0,%0,1\n\
98 stwcx. %0,0,%2\n\
99 bne- 1b"
100 : "=&r" (t), "=m" (v->counter)
101 : "r" (&v->counter), "m" (v->counter)
102 : "cc");
103}
104
105static __inline__ int atomic_inc_return(atomic_t *v)
106{
107 int t;
108
109 __asm__ __volatile__(
110 EIEIO_ON_SMP
111"1: lwarx %0,0,%1 # atomic_inc_return\n\
112 addic %0,%0,1\n\
113 stwcx. %0,0,%1\n\
114 bne- 1b"
115 ISYNC_ON_SMP
116 : "=&r" (t)
117 : "r" (&v->counter)
118 : "cc", "memory");
119
120 return t;
121}
122
123/*
124 * atomic_inc_and_test - increment and test
125 * @v: pointer of type atomic_t
126 *
127 * Atomically increments @v by 1
128 * and returns true if the result is zero, or false for all
129 * other cases.
130 */
131#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
132
133static __inline__ void atomic_dec(atomic_t *v)
134{
135 int t;
136
137 __asm__ __volatile__(
138"1: lwarx %0,0,%2 # atomic_dec\n\
139 addic %0,%0,-1\n\
140 stwcx. %0,0,%2\n\
141 bne- 1b"
142 : "=&r" (t), "=m" (v->counter)
143 : "r" (&v->counter), "m" (v->counter)
144 : "cc");
145}
146
147static __inline__ int atomic_dec_return(atomic_t *v)
148{
149 int t;
150
151 __asm__ __volatile__(
152 EIEIO_ON_SMP
153"1: lwarx %0,0,%1 # atomic_dec_return\n\
154 addic %0,%0,-1\n\
155 stwcx. %0,0,%1\n\
156 bne- 1b"
157 ISYNC_ON_SMP
158 : "=&r" (t)
159 : "r" (&v->counter)
160 : "cc", "memory");
161
162 return t;
163}
164
165#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
166#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
167
168/*
169 * Atomically test *v and decrement if it is greater than 0.
170 * The function returns the old value of *v minus 1.
171 */
172static __inline__ int atomic_dec_if_positive(atomic_t *v)
173{
174 int t;
175
176 __asm__ __volatile__(
177 EIEIO_ON_SMP
178"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
179 addic. %0,%0,-1\n\
180 blt- 2f\n\
181 stwcx. %0,0,%1\n\
182 bne- 1b"
183 ISYNC_ON_SMP
184 "\n\
1852:" : "=&r" (t)
186 : "r" (&v->counter)
187 : "cc", "memory");
188
189 return t;
190}
191
192#define smp_mb__before_atomic_dec() smp_mb()
193#define smp_mb__after_atomic_dec() smp_mb()
194#define smp_mb__before_atomic_inc() smp_mb()
195#define smp_mb__after_atomic_inc() smp_mb()
196
197#endif /* _ASM_PPC64_ATOMIC_H_ */
diff --git a/include/asm-ppc64/auxvec.h b/include/asm-ppc64/auxvec.h
deleted file mode 100644
index ac6381a106e1..000000000000
--- a/include/asm-ppc64/auxvec.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef __PPC64_AUXVEC_H
2#define __PPC64_AUXVEC_H
3
4/*
5 * We need to put in some extra aux table entries to tell glibc what
6 * the cache block size is, so it can use the dcbz instruction safely.
7 */
8#define AT_DCACHEBSIZE 19
9#define AT_ICACHEBSIZE 20
10#define AT_UCACHEBSIZE 21
11/* A special ignored type value for PPC, for glibc compatibility. */
12#define AT_IGNOREPPC 22
13
14/* The vDSO location. We have to use the same value as x86 for glibc's
15 * sake :-)
16 */
17#define AT_SYSINFO_EHDR 33
18
19#endif /* __PPC64_AUXVEC_H */
diff --git a/include/asm-ppc64/bitops.h b/include/asm-ppc64/bitops.h
index a0f831224f96..dbfa42ef4a99 100644
--- a/include/asm-ppc64/bitops.h
+++ b/include/asm-ppc64/bitops.h
@@ -42,7 +42,7 @@
42 42
43#ifdef __KERNEL__ 43#ifdef __KERNEL__
44 44
45#include <asm/memory.h> 45#include <asm/synch.h>
46 46
47/* 47/*
48 * clear_bit doesn't imply a memory barrier 48 * clear_bit doesn't imply a memory barrier
diff --git a/include/asm-ppc64/bug.h b/include/asm-ppc64/bug.h
deleted file mode 100644
index 160178278861..000000000000
--- a/include/asm-ppc64/bug.h
+++ /dev/null
@@ -1,69 +0,0 @@
1#ifndef _PPC64_BUG_H
2#define _PPC64_BUG_H
3
4/*
5 * Define an illegal instr to trap on the bug.
6 * We don't use 0 because that marks the end of a function
7 * in the ELF ABI. That's "Boo Boo" in case you wonder...
8 */
9#define BUG_OPCODE .long 0x00b00b00 /* For asm */
10#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
11
12#ifndef __ASSEMBLY__
13
14struct bug_entry {
15 unsigned long bug_addr;
16 long line;
17 const char *file;
18 const char *function;
19};
20
21struct bug_entry *find_bug(unsigned long bugaddr);
22
23/*
24 * If this bit is set in the line number it means that the trap
25 * is for WARN_ON rather than BUG or BUG_ON.
26 */
27#define BUG_WARNING_TRAP 0x1000000
28
29#ifdef CONFIG_BUG
30
31#define BUG() do { \
32 __asm__ __volatile__( \
33 "1: twi 31,0,0\n" \
34 ".section __bug_table,\"a\"\n\t" \
35 " .llong 1b,%0,%1,%2\n" \
36 ".previous" \
37 : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
38} while (0)
39
40#define BUG_ON(x) do { \
41 __asm__ __volatile__( \
42 "1: tdnei %0,0\n" \
43 ".section __bug_table,\"a\"\n\t" \
44 " .llong 1b,%1,%2,%3\n" \
45 ".previous" \
46 : : "r" ((long long)(x)), "i" (__LINE__), \
47 "i" (__FILE__), "i" (__FUNCTION__)); \
48} while (0)
49
50#define WARN_ON(x) do { \
51 __asm__ __volatile__( \
52 "1: tdnei %0,0\n" \
53 ".section __bug_table,\"a\"\n\t" \
54 " .llong 1b,%1,%2,%3\n" \
55 ".previous" \
56 : : "r" ((long long)(x)), \
57 "i" (__LINE__ + BUG_WARNING_TRAP), \
58 "i" (__FILE__), "i" (__FUNCTION__)); \
59} while (0)
60
61#define HAVE_ARCH_BUG
62#define HAVE_ARCH_BUG_ON
63#define HAVE_ARCH_WARN_ON
64#endif
65#endif
66
67#include <asm-generic/bug.h>
68
69#endif
diff --git a/include/asm-ppc64/byteorder.h b/include/asm-ppc64/byteorder.h
deleted file mode 100644
index 8b57da62b674..000000000000
--- a/include/asm-ppc64/byteorder.h
+++ /dev/null
@@ -1,86 +0,0 @@
1#ifndef _PPC64_BYTEORDER_H
2#define _PPC64_BYTEORDER_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <asm/types.h>
12#include <linux/compiler.h>
13
14#ifdef __GNUC__
15#ifdef __KERNEL__
16
17static __inline__ __u16 ld_le16(const volatile __u16 *addr)
18{
19 __u16 val;
20
21 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
22 return val;
23}
24
25static __inline__ void st_le16(volatile __u16 *addr, const __u16 val)
26{
27 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
28}
29
30static __inline__ __u32 ld_le32(const volatile __u32 *addr)
31{
32 __u32 val;
33
34 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
35 return val;
36}
37
38static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
39{
40 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
41}
42
43static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
44{
45 __u16 result;
46
47 __asm__("rlwimi %0,%1,8,16,23"
48 : "=r" (result)
49 : "r" (value), "0" (value >> 8));
50 return result;
51}
52
53static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
54{
55 __u32 result;
56
57 __asm__("rlwimi %0,%1,24,16,23\n\t"
58 "rlwimi %0,%1,8,8,15\n\t"
59 "rlwimi %0,%1,24,0,7"
60 : "=r" (result)
61 : "r" (value), "0" (value >> 24));
62 return result;
63}
64
65#define __arch__swab16(x) ___arch__swab16(x)
66#define __arch__swab32(x) ___arch__swab32(x)
67
68/* The same, but returns converted value from the location pointer by addr. */
69#define __arch__swab16p(addr) ld_le16(addr)
70#define __arch__swab32p(addr) ld_le32(addr)
71
72/* The same, but do the conversion in situ, ie. put the value back to addr. */
73#define __arch__swab16s(addr) st_le16(addr,*addr)
74#define __arch__swab32s(addr) st_le32(addr,*addr)
75
76#endif /* __KERNEL__ */
77
78#ifndef __STRICT_ANSI__
79#define __BYTEORDER_HAS_U64__
80#endif
81
82#endif /* __GNUC__ */
83
84#include <linux/byteorder/big_endian.h>
85
86#endif /* _PPC64_BYTEORDER_H */
diff --git a/include/asm-ppc64/cputable.h b/include/asm-ppc64/cputable.h
deleted file mode 100644
index acc9b4d6c168..000000000000
--- a/include/asm-ppc64/cputable.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * include/asm-ppc64/cputable.h
3 *
4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * Modifications for ppc64:
7 * Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#ifndef __ASM_PPC_CPUTABLE_H
16#define __ASM_PPC_CPUTABLE_H
17
18#include <linux/config.h>
19#include <asm/page.h> /* for ASM_CONST */
20
21/* Exposed to userland CPU features - Must match ppc32 definitions */
22#define PPC_FEATURE_32 0x80000000
23#define PPC_FEATURE_64 0x40000000
24#define PPC_FEATURE_601_INSTR 0x20000000
25#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
26#define PPC_FEATURE_HAS_FPU 0x08000000
27#define PPC_FEATURE_HAS_MMU 0x04000000
28#define PPC_FEATURE_HAS_4xxMAC 0x02000000
29#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
30
31#ifdef __KERNEL__
32
33#ifndef __ASSEMBLY__
34
35/* This structure can grow, it's real size is used by head.S code
36 * via the mkdefs mechanism.
37 */
38struct cpu_spec;
39struct op_ppc64_model;
40
41typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
42
43struct cpu_spec {
44 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
45 unsigned int pvr_mask;
46 unsigned int pvr_value;
47
48 char *cpu_name;
49 unsigned long cpu_features; /* Kernel features */
50 unsigned int cpu_user_features; /* Userland features */
51
52 /* cache line sizes */
53 unsigned int icache_bsize;
54 unsigned int dcache_bsize;
55
56 /* number of performance monitor counters */
57 unsigned int num_pmcs;
58
59 /* this is called to initialize various CPU bits like L1 cache,
60 * BHT, SPD, etc... from head.S before branching to identify_machine
61 */
62 cpu_setup_t cpu_setup;
63
64 /* Used by oprofile userspace to select the right counters */
65 char *oprofile_cpu_type;
66
67 /* Processor specific oprofile operations */
68 struct op_ppc64_model *oprofile_model;
69};
70
71extern struct cpu_spec cpu_specs[];
72extern struct cpu_spec *cur_cpu_spec;
73
74static inline unsigned long cpu_has_feature(unsigned long feature)
75{
76 return cur_cpu_spec->cpu_features & feature;
77}
78
79#endif /* __ASSEMBLY__ */
80
81/* CPU kernel features */
82
83/* Retain the 32b definitions for the time being - use bottom half of word */
84#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
85#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
86#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
87#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
88#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
89#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
90#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
91#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
92#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
93#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
94#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
95#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
96#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
97#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
98#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
99
100/* Add the 64b processor unique features in the top half of the word */
101#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
102#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
103#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
104#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
105#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
106#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
107#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
108/* unused ASM_CONST(0x0000008000000000) */
109#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
110#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
111#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
112#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
113#define CPU_FTR_CTRL ASM_CONST(0x0000100000000000)
114
115#ifndef __ASSEMBLY__
116
117#define COMMON_USER_PPC64 (PPC_FEATURE_32 | PPC_FEATURE_64 | \
118 PPC_FEATURE_HAS_FPU | PPC_FEATURE_HAS_MMU)
119
120#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
121 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
122 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
123
124/* iSeries doesn't support large pages */
125#ifdef CONFIG_PPC_ISERIES
126#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
127#else
128#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
129#endif /* CONFIG_PPC_ISERIES */
130
131#endif /* __ASSEMBLY */
132
133#ifdef __ASSEMBLY__
134
135#define BEGIN_FTR_SECTION 98:
136
137#define END_FTR_SECTION(msk, val) \
13899: \
139 .section __ftr_fixup,"a"; \
140 .align 3; \
141 .llong msk; \
142 .llong val; \
143 .llong 98b; \
144 .llong 99b; \
145 .previous
146
147#else
148
149#define BEGIN_FTR_SECTION "98:\n"
150#define END_FTR_SECTION(msk, val) \
151"99:\n" \
152" .section __ftr_fixup,\"a\";\n" \
153" .align 3;\n" \
154" .llong "#msk";\n" \
155" .llong "#val";\n" \
156" .llong 98b;\n" \
157" .llong 99b;\n" \
158" .previous\n"
159
160#endif /* __ASSEMBLY__ */
161
162#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
163#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
164
165#endif /* __ASM_PPC_CPUTABLE_H */
166#endif /* __KERNEL__ */
167
diff --git a/include/asm-ppc64/dart.h b/include/asm-ppc64/dart.h
new file mode 100644
index 000000000000..cdf8a2dec05f
--- /dev/null
+++ b/include/asm-ppc64/dart.h
@@ -0,0 +1,59 @@
1/*
2 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 */
18
19#ifndef _ASM_DART_H
20#define _ASM_DART_H
21
22
23/* physical base of DART registers */
24#define DART_BASE 0xf8033000UL
25
26/* Offset from base to control register */
27#define DARTCNTL 0
28/* Offset from base to exception register */
29#define DARTEXCP 0x10
30/* Offset from base to TLB tag registers */
31#define DARTTAG 0x1000
32
33
34/* Control Register fields */
35
36/* base address of table (pfn) */
37#define DARTCNTL_BASE_MASK 0xfffff
38#define DARTCNTL_BASE_SHIFT 12
39
40#define DARTCNTL_FLUSHTLB 0x400
41#define DARTCNTL_ENABLE 0x200
42
43/* size of table in pages */
44#define DARTCNTL_SIZE_MASK 0x1ff
45#define DARTCNTL_SIZE_SHIFT 0
46
47
48/* DART table fields */
49
50#define DARTMAP_VALID 0x80000000
51#define DARTMAP_RPNMASK 0x00ffffff
52
53
54#define DART_PAGE_SHIFT 12
55#define DART_PAGE_SIZE (1 << DART_PAGE_SHIFT)
56#define DART_PAGE_FACTOR (PAGE_SHIFT - DART_PAGE_SHIFT)
57
58
59#endif
diff --git a/include/asm-ppc64/dma.h b/include/asm-ppc64/dma.h
deleted file mode 100644
index dfd1f69059ba..000000000000
--- a/include/asm-ppc64/dma.h
+++ /dev/null
@@ -1,329 +0,0 @@
1/*
2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 * Changes for ppc sound by Christoph Nadig
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#ifndef _ASM_DMA_H
15#define _ASM_DMA_H
16
17#include <linux/config.h>
18#include <asm/io.h>
19#include <linux/spinlock.h>
20#include <asm/system.h>
21
22#ifndef MAX_DMA_CHANNELS
23#define MAX_DMA_CHANNELS 8
24#endif
25
26/* The maximum address that we can perform a DMA transfer to on this platform */
27/* Doesn't really apply... */
28#define MAX_DMA_ADDRESS (~0UL)
29
30#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
31
32#define dma_outb outb
33#define dma_inb inb
34
35/*
36 * NOTES about DMA transfers:
37 *
38 * controller 1: channels 0-3, byte operations, ports 00-1F
39 * controller 2: channels 4-7, word operations, ports C0-DF
40 *
41 * - ALL registers are 8 bits only, regardless of transfer size
42 * - channel 4 is not used - cascades 1 into 2.
43 * - channels 0-3 are byte - addresses/counts are for physical bytes
44 * - channels 5-7 are word - addresses/counts are for physical words
45 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
46 * - transfer count loaded to registers is 1 less than actual count
47 * - controller 2 offsets are all even (2x offsets for controller 1)
48 * - page registers for 5-7 don't use data bit 0, represent 128K pages
49 * - page registers for 0-3 use bit 0, represent 64K pages
50 *
51 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
52 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
53 * Note that addresses loaded into registers must be _physical_ addresses,
54 * not logical addresses (which may differ if paging is active).
55 *
56 * Address mapping for channels 0-3:
57 *
58 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
59 * | ... | | ... | | ... |
60 * | ... | | ... | | ... |
61 * | ... | | ... | | ... |
62 * P7 ... P0 A7 ... A0 A7 ... A0
63 * | Page | Addr MSB | Addr LSB | (DMA registers)
64 *
65 * Address mapping for channels 5-7:
66 *
67 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
68 * | ... | \ \ ... \ \ \ ... \ \
69 * | ... | \ \ ... \ \ \ ... \ (not used)
70 * | ... | \ \ ... \ \ \ ... \
71 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
72 * | Page | Addr MSB | Addr LSB | (DMA registers)
73 *
74 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
75 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
76 * the hardware level, so odd-byte transfers aren't possible).
77 *
78 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
79 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
80 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
81 *
82 */
83
84/* 8237 DMA controllers */
85#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
86#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
87
88/* DMA controller registers */
89#define DMA1_CMD_REG 0x08 /* command register (w) */
90#define DMA1_STAT_REG 0x08 /* status register (r) */
91#define DMA1_REQ_REG 0x09 /* request register (w) */
92#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
93#define DMA1_MODE_REG 0x0B /* mode register (w) */
94#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
95#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
96#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
97#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
98#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
99
100#define DMA2_CMD_REG 0xD0 /* command register (w) */
101#define DMA2_STAT_REG 0xD0 /* status register (r) */
102#define DMA2_REQ_REG 0xD2 /* request register (w) */
103#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
104#define DMA2_MODE_REG 0xD6 /* mode register (w) */
105#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
106#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
107#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
108#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
109#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
110
111#define DMA_ADDR_0 0x00 /* DMA address registers */
112#define DMA_ADDR_1 0x02
113#define DMA_ADDR_2 0x04
114#define DMA_ADDR_3 0x06
115#define DMA_ADDR_4 0xC0
116#define DMA_ADDR_5 0xC4
117#define DMA_ADDR_6 0xC8
118#define DMA_ADDR_7 0xCC
119
120#define DMA_CNT_0 0x01 /* DMA count registers */
121#define DMA_CNT_1 0x03
122#define DMA_CNT_2 0x05
123#define DMA_CNT_3 0x07
124#define DMA_CNT_4 0xC2
125#define DMA_CNT_5 0xC6
126#define DMA_CNT_6 0xCA
127#define DMA_CNT_7 0xCE
128
129#define DMA_LO_PAGE_0 0x87 /* DMA page registers */
130#define DMA_LO_PAGE_1 0x83
131#define DMA_LO_PAGE_2 0x81
132#define DMA_LO_PAGE_3 0x82
133#define DMA_LO_PAGE_5 0x8B
134#define DMA_LO_PAGE_6 0x89
135#define DMA_LO_PAGE_7 0x8A
136
137#define DMA_HI_PAGE_0 0x487 /* DMA page registers */
138#define DMA_HI_PAGE_1 0x483
139#define DMA_HI_PAGE_2 0x481
140#define DMA_HI_PAGE_3 0x482
141#define DMA_HI_PAGE_5 0x48B
142#define DMA_HI_PAGE_6 0x489
143#define DMA_HI_PAGE_7 0x48A
144
145#define DMA1_EXT_REG 0x40B
146#define DMA2_EXT_REG 0x4D6
147
148#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
149#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
150#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
151
152#define DMA_AUTOINIT 0x10
153
154extern spinlock_t dma_spin_lock;
155
156static __inline__ unsigned long claim_dma_lock(void)
157{
158 unsigned long flags;
159 spin_lock_irqsave(&dma_spin_lock, flags);
160 return flags;
161}
162
163static __inline__ void release_dma_lock(unsigned long flags)
164{
165 spin_unlock_irqrestore(&dma_spin_lock, flags);
166}
167
168/* enable/disable a specific DMA channel */
169static __inline__ void enable_dma(unsigned int dmanr)
170{
171 unsigned char ucDmaCmd=0x00;
172
173 if (dmanr != 4)
174 {
175 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
176 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
177 }
178 if (dmanr<=3)
179 {
180 dma_outb(dmanr, DMA1_MASK_REG);
181 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
182 } else
183 {
184 dma_outb(dmanr & 3, DMA2_MASK_REG);
185 }
186}
187
188static __inline__ void disable_dma(unsigned int dmanr)
189{
190 if (dmanr<=3)
191 dma_outb(dmanr | 4, DMA1_MASK_REG);
192 else
193 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
194}
195
196/* Clear the 'DMA Pointer Flip Flop'.
197 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
198 * Use this once to initialize the FF to a known state.
199 * After that, keep track of it. :-)
200 * --- In order to do that, the DMA routines below should ---
201 * --- only be used while interrupts are disabled! ---
202 */
203static __inline__ void clear_dma_ff(unsigned int dmanr)
204{
205 if (dmanr<=3)
206 dma_outb(0, DMA1_CLEAR_FF_REG);
207 else
208 dma_outb(0, DMA2_CLEAR_FF_REG);
209}
210
211/* set mode (above) for a specific DMA channel */
212static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
213{
214 if (dmanr<=3)
215 dma_outb(mode | dmanr, DMA1_MODE_REG);
216 else
217 dma_outb(mode | (dmanr&3), DMA2_MODE_REG);
218}
219
220/* Set only the page register bits of the transfer address.
221 * This is used for successive transfers when we know the contents of
222 * the lower 16 bits of the DMA current address register, but a 64k boundary
223 * may have been crossed.
224 */
225static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
226{
227 switch(dmanr) {
228 case 0:
229 dma_outb(pagenr, DMA_LO_PAGE_0);
230 dma_outb(pagenr>>8, DMA_HI_PAGE_0);
231 break;
232 case 1:
233 dma_outb(pagenr, DMA_LO_PAGE_1);
234 dma_outb(pagenr>>8, DMA_HI_PAGE_1);
235 break;
236 case 2:
237 dma_outb(pagenr, DMA_LO_PAGE_2);
238 dma_outb(pagenr>>8, DMA_HI_PAGE_2);
239 break;
240 case 3:
241 dma_outb(pagenr, DMA_LO_PAGE_3);
242 dma_outb(pagenr>>8, DMA_HI_PAGE_3);
243 break;
244 case 5:
245 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
246 dma_outb(pagenr>>8, DMA_HI_PAGE_5);
247 break;
248 case 6:
249 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
250 dma_outb(pagenr>>8, DMA_HI_PAGE_6);
251 break;
252 case 7:
253 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
254 dma_outb(pagenr>>8, DMA_HI_PAGE_7);
255 break;
256 }
257}
258
259
260/* Set transfer address & page bits for specific DMA channel.
261 * Assumes dma flipflop is clear.
262 */
263static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
264{
265 if (dmanr <= 3) {
266 dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
267 dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
268 } else {
269 dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
270 dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
271 }
272 set_dma_page(dmanr, phys>>16);
273}
274
275
276/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
277 * a specific DMA channel.
278 * You must ensure the parameters are valid.
279 * NOTE: from a manual: "the number of transfers is one more
280 * than the initial word count"! This is taken into account.
281 * Assumes dma flip-flop is clear.
282 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
283 */
284static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
285{
286 count--;
287 if (dmanr <= 3) {
288 dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
289 dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
290 } else {
291 dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
292 dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
293 }
294}
295
296
297/* Get DMA residue count. After a DMA transfer, this
298 * should return zero. Reading this while a DMA transfer is
299 * still in progress will return unpredictable results.
300 * If called before the channel has been used, it may return 1.
301 * Otherwise, it returns the number of _bytes_ left to transfer.
302 *
303 * Assumes DMA flip-flop is clear.
304 */
305static __inline__ int get_dma_residue(unsigned int dmanr)
306{
307 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
308 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
309
310 /* using short to get 16-bit wrap around */
311 unsigned short count;
312
313 count = 1 + dma_inb(io_port);
314 count += dma_inb(io_port) << 8;
315
316 return (dmanr <= 3)? count : (count<<1);
317}
318
319/* These are in kernel/dma.c: */
320extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */
321extern void free_dma(unsigned int dmanr); /* release it again */
322
323#ifdef CONFIG_PCI
324extern int isa_dma_bridge_buggy;
325#else
326#define isa_dma_bridge_buggy (0)
327#endif
328#endif /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
329#endif /* _ASM_DMA_H */
diff --git a/include/asm-ppc64/elf.h b/include/asm-ppc64/elf.h
deleted file mode 100644
index c919a89343db..000000000000
--- a/include/asm-ppc64/elf.h
+++ /dev/null
@@ -1,387 +0,0 @@
1#ifndef __PPC64_ELF_H
2#define __PPC64_ELF_H
3
4#include <asm/types.h>
5#include <asm/ptrace.h>
6#include <asm/cputable.h>
7#include <asm/auxvec.h>
8
9/* PowerPC relocations defined by the ABIs */
10#define R_PPC_NONE 0
11#define R_PPC_ADDR32 1 /* 32bit absolute address */
12#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
13#define R_PPC_ADDR16 3 /* 16bit absolute address */
14#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
15#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
16#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
17#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
18#define R_PPC_ADDR14_BRTAKEN 8
19#define R_PPC_ADDR14_BRNTAKEN 9
20#define R_PPC_REL24 10 /* PC relative 26 bit */
21#define R_PPC_REL14 11 /* PC relative 16 bit */
22#define R_PPC_REL14_BRTAKEN 12
23#define R_PPC_REL14_BRNTAKEN 13
24#define R_PPC_GOT16 14
25#define R_PPC_GOT16_LO 15
26#define R_PPC_GOT16_HI 16
27#define R_PPC_GOT16_HA 17
28#define R_PPC_PLTREL24 18
29#define R_PPC_COPY 19
30#define R_PPC_GLOB_DAT 20
31#define R_PPC_JMP_SLOT 21
32#define R_PPC_RELATIVE 22
33#define R_PPC_LOCAL24PC 23
34#define R_PPC_UADDR32 24
35#define R_PPC_UADDR16 25
36#define R_PPC_REL32 26
37#define R_PPC_PLT32 27
38#define R_PPC_PLTREL32 28
39#define R_PPC_PLT16_LO 29
40#define R_PPC_PLT16_HI 30
41#define R_PPC_PLT16_HA 31
42#define R_PPC_SDAREL16 32
43#define R_PPC_SECTOFF 33
44#define R_PPC_SECTOFF_LO 34
45#define R_PPC_SECTOFF_HI 35
46#define R_PPC_SECTOFF_HA 36
47
48/* PowerPC relocations defined for the TLS access ABI. */
49#define R_PPC_TLS 67 /* none (sym+add)@tls */
50#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
51#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
52#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
53#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
54#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
55#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
56#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
57#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
58#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
59#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
60#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
61#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
62#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
63#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
64#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
65#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
66#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
67#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
68#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
69#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
70#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
71#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
72#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
73#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
74#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
75#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
76#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
77
78/* Keep this the last entry. */
79#define R_PPC_NUM 95
80
81/*
82 * ELF register definitions..
83 *
84 * This program is free software; you can redistribute it and/or
85 * modify it under the terms of the GNU General Public License
86 * as published by the Free Software Foundation; either version
87 * 2 of the License, or (at your option) any later version.
88 */
89#include <asm/ptrace.h>
90
91#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
92#define ELF_NFPREG 33 /* includes fpscr */
93#define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
94#define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
95
96typedef unsigned long elf_greg_t64;
97typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
98
99typedef unsigned int elf_greg_t32;
100typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
101
102/*
103 * These are used to set parameters in the core dumps.
104 */
105#ifndef ELF_ARCH
106# define ELF_ARCH EM_PPC64
107# define ELF_CLASS ELFCLASS64
108# define ELF_DATA ELFDATA2MSB
109 typedef elf_greg_t64 elf_greg_t;
110 typedef elf_gregset_t64 elf_gregset_t;
111# define elf_addr_t unsigned long
112#else
113 /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
114 typedef elf_greg_t32 elf_greg_t;
115 typedef elf_gregset_t32 elf_gregset_t;
116# define elf_addr_t u32
117#endif
118
119typedef double elf_fpreg_t;
120typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
121
122/* Altivec registers */
123/*
124 * The entries with indexes 0-31 contain the corresponding vector registers.
125 * The entry with index 32 contains the vscr as the last word (offset 12)
126 * within the quadword. This allows the vscr to be stored as either a
127 * quadword (since it must be copied via a vector register to/from storage)
128 * or as a word. The entry with index 33 contains the vrsave as the first
129 * word (offset 0) within the quadword.
130 *
131 * This definition of the VMX state is compatible with the current PPC32
132 * ptrace interface. This allows signal handling and ptrace to use the same
133 * structures. This also simplifies the implementation of a bi-arch
134 * (combined (32- and 64-bit) gdb.
135 *
136 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
137 * vrsave along with vscr and so only uses 33 vectors for the register set
138 */
139typedef __vector128 elf_vrreg_t;
140typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
141typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
142
143/*
144 * This is used to ensure we don't load something for the wrong architecture.
145 */
146#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
147
148#define USE_ELF_CORE_DUMP
149#define ELF_EXEC_PAGESIZE 4096
150
151/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
152 use of this is to invoke "./ld.so someprog" to test out a new version of
153 the loader. We need to make sure that it is out of the way of the program
154 that it will "exec", and that there is sufficient room for the brk. */
155
156#define ELF_ET_DYN_BASE (0x08000000)
157
158#ifdef __KERNEL__
159
160/* Common routine for both 32-bit and 64-bit processes */
161static inline void ppc64_elf_core_copy_regs(elf_gregset_t elf_regs,
162 struct pt_regs *regs)
163{
164 int i;
165 int gprs = sizeof(struct pt_regs)/sizeof(elf_greg_t64);
166
167 if (gprs > ELF_NGREG)
168 gprs = ELF_NGREG;
169
170 for (i=0; i < gprs; i++)
171 elf_regs[i] = (elf_greg_t)((elf_greg_t64 *)regs)[i];
172}
173#define ELF_CORE_COPY_REGS(gregs, regs) ppc64_elf_core_copy_regs(gregs, regs);
174
175static inline int dump_task_regs(struct task_struct *tsk,
176 elf_gregset_t *elf_regs)
177{
178 struct pt_regs *regs = tsk->thread.regs;
179 if (regs)
180 ppc64_elf_core_copy_regs(*elf_regs, regs);
181
182 return 1;
183}
184#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
185
186extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
187#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
188
189/* XXX Should we define the XFPREGS using altivec ??? */
190
191#endif
192
193/* This yields a mask that user programs can use to figure out what
194 instruction set this cpu supports. This could be done in userspace,
195 but it's not easy, and we've already done it here. */
196
197#define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
198
199/* This yields a string that ld.so will use to load implementation
200 specific libraries for optimization. This is more specific in
201 intent than poking at uname or /proc/cpuinfo.
202
203 For the moment, we have only optimizations for the Intel generations,
204 but that could change... */
205
206#define ELF_PLATFORM (NULL)
207
208#define ELF_PLAT_INIT(_r, load_addr) do { \
209 memset(_r->gpr, 0, sizeof(_r->gpr)); \
210 _r->ctr = _r->link = _r->xer = _r->ccr = 0; \
211 _r->gpr[2] = load_addr; \
212} while (0)
213
214#ifdef __KERNEL__
215#define SET_PERSONALITY(ex, ibcs2) \
216do { \
217 unsigned long new_flags = 0; \
218 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
219 new_flags = _TIF_32BIT; \
220 if ((current_thread_info()->flags & _TIF_32BIT) \
221 != new_flags) \
222 set_thread_flag(TIF_ABI_PENDING); \
223 else \
224 clear_thread_flag(TIF_ABI_PENDING); \
225 if (personality(current->personality) != PER_LINUX32) \
226 set_personality(PER_LINUX); \
227} while (0)
228
229/*
230 * An executable for which elf_read_implies_exec() returns TRUE will
231 * have the READ_IMPLIES_EXEC personality flag set automatically. This
232 * is only required to work around bugs in old 32bit toolchains. Since
233 * the 64bit ABI has never had these issues dont enable the workaround
234 * even if we have an executable stack.
235 */
236#define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
237 (exec_stk != EXSTACK_DISABLE_X) : 0)
238
239#endif
240
241extern int dcache_bsize;
242extern int icache_bsize;
243extern int ucache_bsize;
244
245/* We do have an arch_setup_additional_pages for vDSO matters */
246#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
247struct linux_binprm;
248extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack);
249
250/*
251 * The requirements here are:
252 * - keep the final alignment of sp (sp & 0xf)
253 * - make sure the 32-bit value at the first 16 byte aligned position of
254 * AUXV is greater than 16 for glibc compatibility.
255 * AT_IGNOREPPC is used for that.
256 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
257 * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
258 */
259#define ARCH_DLINFO \
260do { \
261 /* Handle glibc compatibility. */ \
262 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
263 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
264 /* Cache size items */ \
265 NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
266 NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
267 NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
268 /* vDSO base */ \
269 NEW_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base); \
270 } while (0)
271
272/* PowerPC64 relocations defined by the ABIs */
273#define R_PPC64_NONE R_PPC_NONE
274#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
275#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
276#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
277#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
278#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
279#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
280#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
281#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
282#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
283#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
284#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
285#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
286#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
287#define R_PPC64_GOT16 R_PPC_GOT16
288#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
289#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
290#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
291
292#define R_PPC64_COPY R_PPC_COPY
293#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
294#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
295#define R_PPC64_RELATIVE R_PPC_RELATIVE
296
297#define R_PPC64_UADDR32 R_PPC_UADDR32
298#define R_PPC64_UADDR16 R_PPC_UADDR16
299#define R_PPC64_REL32 R_PPC_REL32
300#define R_PPC64_PLT32 R_PPC_PLT32
301#define R_PPC64_PLTREL32 R_PPC_PLTREL32
302#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
303#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
304#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
305
306#define R_PPC64_SECTOFF R_PPC_SECTOFF
307#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
308#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
309#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
310#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
311#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
312#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
313#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
314#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
315#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
316#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
317#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
318#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
319#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
320#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
321#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
322#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
323#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
324#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
325#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
326#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
327#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
328#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
329
330#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
331#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
332#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
333#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
334#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
335#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
336#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
337#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
338#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
339#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
340#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
341
342/* PowerPC64 relocations defined for the TLS access ABI. */
343#define R_PPC64_TLS 67 /* none (sym+add)@tls */
344#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
345#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
346#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
347#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
348#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
349#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
350#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
351#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
352#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
353#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
354#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
355#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
356#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
357#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
358#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
359#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
360#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
361#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
362#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
363#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
364#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
365#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
366#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
367#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
368#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
369#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
370#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
371#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
372#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
373#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
374#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
375#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
376#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
377#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
378#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
379#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
380#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
381#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
382#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
383
384/* Keep this the last entry. */
385#define R_PPC64_NUM 107
386
387#endif /* __PPC64_ELF_H */
diff --git a/include/asm-ppc64/futex.h b/include/asm-ppc64/futex.h
index cb2640b3a408..266b460de44e 100644
--- a/include/asm-ppc64/futex.h
+++ b/include/asm-ppc64/futex.h
@@ -5,7 +5,7 @@
5 5
6#include <linux/futex.h> 6#include <linux/futex.h>
7#include <asm/errno.h> 7#include <asm/errno.h>
8#include <asm/memory.h> 8#include <asm/synch.h>
9#include <asm/uaccess.h> 9#include <asm/uaccess.h>
10 10
11#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 11#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
diff --git a/include/asm-ppc64/hardirq.h b/include/asm-ppc64/hardirq.h
deleted file mode 100644
index 4ee72bb1fd48..000000000000
--- a/include/asm-ppc64/hardirq.h
+++ /dev/null
@@ -1,27 +0,0 @@
1#ifndef __ASM_HARDIRQ_H
2#define __ASM_HARDIRQ_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <linux/config.h>
12#include <linux/cache.h>
13#include <linux/preempt.h>
14
15typedef struct {
16 unsigned int __softirq_pending;
17} ____cacheline_aligned irq_cpustat_t;
18
19#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
20
21static inline void ack_bad_irq(int irq)
22{
23 printk(KERN_CRIT "illegal vector %d received!\n", irq);
24 BUG();
25}
26
27#endif /* __ASM_HARDIRQ_H */
diff --git a/include/asm-ppc64/hw_irq.h b/include/asm-ppc64/hw_irq.h
deleted file mode 100644
index baea40e695ec..000000000000
--- a/include/asm-ppc64/hw_irq.h
+++ /dev/null
@@ -1,104 +0,0 @@
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 *
4 * Use inline IRQs where possible - Anton Blanchard <anton@au.ibm.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11#ifdef __KERNEL__
12#ifndef _PPC64_HW_IRQ_H
13#define _PPC64_HW_IRQ_H
14
15#include <linux/config.h>
16#include <linux/errno.h>
17#include <asm/irq.h>
18
19int timer_interrupt(struct pt_regs *);
20extern void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq);
21
22#ifdef CONFIG_PPC_ISERIES
23
24extern unsigned long local_get_flags(void);
25extern unsigned long local_irq_disable(void);
26extern void local_irq_restore(unsigned long);
27
28#define local_irq_enable() local_irq_restore(1)
29#define local_save_flags(flags) ((flags) = local_get_flags())
30#define local_irq_save(flags) ((flags) = local_irq_disable())
31
32#define irqs_disabled() (local_get_flags() == 0)
33
34#else
35
36#define local_save_flags(flags) ((flags) = mfmsr())
37#define local_irq_restore(flags) do { \
38 __asm__ __volatile__("": : :"memory"); \
39 __mtmsrd((flags), 1); \
40} while(0)
41
42static inline void local_irq_disable(void)
43{
44 unsigned long msr;
45 msr = mfmsr();
46 __mtmsrd(msr & ~MSR_EE, 1);
47 __asm__ __volatile__("": : :"memory");
48}
49
50static inline void local_irq_enable(void)
51{
52 unsigned long msr;
53 __asm__ __volatile__("": : :"memory");
54 msr = mfmsr();
55 __mtmsrd(msr | MSR_EE, 1);
56}
57
58static inline void __do_save_and_cli(unsigned long *flags)
59{
60 unsigned long msr;
61 msr = mfmsr();
62 *flags = msr;
63 __mtmsrd(msr & ~MSR_EE, 1);
64 __asm__ __volatile__("": : :"memory");
65}
66
67#define local_irq_save(flags) __do_save_and_cli(&flags)
68
69#define irqs_disabled() \
70({ \
71 unsigned long flags; \
72 local_save_flags(flags); \
73 !(flags & MSR_EE); \
74})
75
76#endif /* CONFIG_PPC_ISERIES */
77
78#define mask_irq(irq) \
79 ({ \
80 irq_desc_t *desc = get_irq_desc(irq); \
81 if (desc->handler && desc->handler->disable) \
82 desc->handler->disable(irq); \
83 })
84#define unmask_irq(irq) \
85 ({ \
86 irq_desc_t *desc = get_irq_desc(irq); \
87 if (desc->handler && desc->handler->enable) \
88 desc->handler->enable(irq); \
89 })
90#define ack_irq(irq) \
91 ({ \
92 irq_desc_t *desc = get_irq_desc(irq); \
93 if (desc->handler && desc->handler->ack) \
94 desc->handler->ack(irq); \
95 })
96
97/* Should we handle this via lost interrupts and IPIs or should we don't care like
98 * we do now ? --BenH.
99 */
100struct hw_interrupt_type;
101static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
102
103#endif /* _PPC64_HW_IRQ_H */
104#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/iSeries/HvCallSm.h b/include/asm-ppc64/iSeries/HvCallSm.h
deleted file mode 100644
index 8a3dbb071a43..000000000000
--- a/include/asm-ppc64/iSeries/HvCallSm.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * HvCallSm.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _HVCALLSM_H
20#define _HVCALLSM_H
21
22/*
23 * This file contains the "hypervisor call" interface which is used to
24 * drive the hypervisor from the OS.
25 */
26
27#include <asm/iSeries/HvCallSc.h>
28#include <asm/iSeries/HvTypes.h>
29
30#define HvCallSmGet64BitsOfAccessMap HvCallSm + 11
31
32static inline u64 HvCallSm_get64BitsOfAccessMap(HvLpIndex lpIndex,
33 u64 indexIntoBitMap)
34{
35 return HvCall2(HvCallSmGet64BitsOfAccessMap, lpIndex, indexIntoBitMap);
36}
37
38#endif /* _HVCALLSM_H */
diff --git a/include/asm-ppc64/iSeries/HvReleaseData.h b/include/asm-ppc64/iSeries/HvReleaseData.h
deleted file mode 100644
index c8162e5ccb21..000000000000
--- a/include/asm-ppc64/iSeries/HvReleaseData.h
+++ /dev/null
@@ -1,64 +0,0 @@
1/*
2 * HvReleaseData.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _HVRELEASEDATA_H
20#define _HVRELEASEDATA_H
21
22/*
23 * This control block contains the critical information about the
24 * release so that it can be changed in the future (ie, the virtual
25 * address of the OS's NACA).
26 */
27#include <asm/types.h>
28#include <asm/naca.h>
29
30/*
31 * When we IPL a secondary partition, we will check if if the
32 * secondary xMinPlicVrmIndex > the primary xVrmIndex.
33 * If it is then this tells PLIC that this secondary is not
34 * supported running on this "old" of a level of PLIC.
35 *
36 * Likewise, we will compare the primary xMinSlicVrmIndex to
37 * the secondary xVrmIndex.
38 * If the primary xMinSlicVrmDelta > secondary xVrmDelta then we
39 * know that this PLIC does not support running an OS "that old".
40 */
41
42#define HVREL_TAGSINACTIVE 0x8000
43#define HVREL_32BIT 0x4000
44#define HVREL_NOSHAREDPROCS 0x2000
45#define HVREL_NOHMT 0x1000
46
47struct HvReleaseData {
48 u32 xDesc; /* Descriptor "HvRD" ebcdic x00-x03 */
49 u16 xSize; /* Size of this control block x04-x05 */
50 u16 xVpdAreasPtrOffset; /* Offset in NACA of ItVpdAreas x06-x07 */
51 struct naca_struct *xSlicNacaAddr; /* Virt addr of SLIC NACA x08-x0F */
52 u32 xMsNucDataOffset; /* Offset of Linux Mapping Data x10-x13 */
53 u32 xRsvd1; /* Reserved x14-x17 */
54 u16 xFlags;
55 u16 xVrmIndex; /* VRM Index of OS image x1A-x1B */
56 u16 xMinSupportedPlicVrmIndex; /* Min PLIC level (soft) x1C-x1D */
57 u16 xMinCompatablePlicVrmIndex; /* Min PLIC levelP (hard) x1E-x1F */
58 char xVrmName[12]; /* Displayable name x20-x2B */
59 char xRsvd3[20]; /* Reserved x2C-x3F */
60};
61
62extern struct HvReleaseData hvReleaseData;
63
64#endif /* _HVRELEASEDATA_H */
diff --git a/include/asm-ppc64/iSeries/IoHriMainStore.h b/include/asm-ppc64/iSeries/IoHriMainStore.h
deleted file mode 100644
index 45ed3ea67d06..000000000000
--- a/include/asm-ppc64/iSeries/IoHriMainStore.h
+++ /dev/null
@@ -1,166 +0,0 @@
1/*
2 * IoHriMainStore.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _IOHRIMAINSTORE_H
21#define _IOHRIMAINSTORE_H
22
23/* Main Store Vpd for Condor,iStar,sStar */
24struct IoHriMainStoreSegment4 {
25 u8 msArea0Exists:1;
26 u8 msArea1Exists:1;
27 u8 msArea2Exists:1;
28 u8 msArea3Exists:1;
29 u8 reserved1:4;
30 u8 reserved2;
31
32 u8 msArea0Functional:1;
33 u8 msArea1Functional:1;
34 u8 msArea2Functional:1;
35 u8 msArea3Functional:1;
36 u8 reserved3:4;
37 u8 reserved4;
38
39 u32 totalMainStore;
40
41 u64 msArea0Ptr;
42 u64 msArea1Ptr;
43 u64 msArea2Ptr;
44 u64 msArea3Ptr;
45
46 u32 cardProductionLevel;
47
48 u32 msAdrHole;
49
50 u8 msArea0HasRiserVpd:1;
51 u8 msArea1HasRiserVpd:1;
52 u8 msArea2HasRiserVpd:1;
53 u8 msArea3HasRiserVpd:1;
54 u8 reserved5:4;
55 u8 reserved6;
56 u16 reserved7;
57
58 u8 reserved8[28];
59
60 u64 nonInterleavedBlocksStartAdr;
61 u64 nonInterleavedBlocksEndAdr;
62};
63
64/* Main Store VPD for Power4 */
65struct IoHriMainStoreChipInfo1 {
66 u32 chipMfgID __attribute((packed));
67 char chipECLevel[4] __attribute((packed));
68};
69
70struct IoHriMainStoreVpdIdData {
71 char typeNumber[4];
72 char modelNumber[4];
73 char partNumber[12];
74 char serialNumber[12];
75};
76
77struct IoHriMainStoreVpdFruData {
78 char fruLabel[8] __attribute((packed));
79 u8 numberOfSlots __attribute((packed));
80 u8 pluggingType __attribute((packed));
81 u16 slotMapIndex __attribute((packed));
82};
83
84struct IoHriMainStoreAdrRangeBlock {
85 void *blockStart __attribute((packed));
86 void *blockEnd __attribute((packed));
87 u32 blockProcChipId __attribute((packed));
88};
89
90#define MaxAreaAdrRangeBlocks 4
91
92struct IoHriMainStoreArea4 {
93 u32 msVpdFormat __attribute((packed));
94 u8 containedVpdType __attribute((packed));
95 u8 reserved1 __attribute((packed));
96 u16 reserved2 __attribute((packed));
97
98 u64 msExists __attribute((packed));
99 u64 msFunctional __attribute((packed));
100
101 u32 memorySize __attribute((packed));
102 u32 procNodeId __attribute((packed));
103
104 u32 numAdrRangeBlocks __attribute((packed));
105 struct IoHriMainStoreAdrRangeBlock xAdrRangeBlock[MaxAreaAdrRangeBlocks] __attribute((packed));
106
107 struct IoHriMainStoreChipInfo1 chipInfo0 __attribute((packed));
108 struct IoHriMainStoreChipInfo1 chipInfo1 __attribute((packed));
109 struct IoHriMainStoreChipInfo1 chipInfo2 __attribute((packed));
110 struct IoHriMainStoreChipInfo1 chipInfo3 __attribute((packed));
111 struct IoHriMainStoreChipInfo1 chipInfo4 __attribute((packed));
112 struct IoHriMainStoreChipInfo1 chipInfo5 __attribute((packed));
113 struct IoHriMainStoreChipInfo1 chipInfo6 __attribute((packed));
114 struct IoHriMainStoreChipInfo1 chipInfo7 __attribute((packed));
115
116 void *msRamAreaArray __attribute((packed));
117 u32 msRamAreaArrayNumEntries __attribute((packed));
118 u32 msRamAreaArrayEntrySize __attribute((packed));
119
120 u32 numaDimmExists __attribute((packed));
121 u32 numaDimmFunctional __attribute((packed));
122 void *numaDimmArray __attribute((packed));
123 u32 numaDimmArrayNumEntries __attribute((packed));
124 u32 numaDimmArrayEntrySize __attribute((packed));
125
126 struct IoHriMainStoreVpdIdData idData __attribute((packed));
127
128 u64 powerData __attribute((packed));
129 u64 cardAssemblyPartNum __attribute((packed));
130 u64 chipSerialNum __attribute((packed));
131
132 u64 reserved3 __attribute((packed));
133 char reserved4[16] __attribute((packed));
134
135 struct IoHriMainStoreVpdFruData fruData __attribute((packed));
136
137 u8 vpdPortNum __attribute((packed));
138 u8 reserved5 __attribute((packed));
139 u8 frameId __attribute((packed));
140 u8 rackUnit __attribute((packed));
141 char asciiKeywordVpd[256] __attribute((packed));
142 u32 reserved6 __attribute((packed));
143};
144
145
146struct IoHriMainStoreSegment5 {
147 u16 reserved1;
148 u8 reserved2;
149 u8 msVpdFormat;
150
151 u32 totalMainStore;
152 u64 maxConfiguredMsAdr;
153
154 struct IoHriMainStoreArea4 *msAreaArray;
155 u32 msAreaArrayNumEntries;
156 u32 msAreaArrayEntrySize;
157
158 u32 msAreaExists;
159 u32 msAreaFunctional;
160
161 u64 reserved3;
162};
163
164extern u64 xMsVpd[];
165
166#endif /* _IOHRIMAINSTORE_H */
diff --git a/include/asm-ppc64/iSeries/IoHriProcessorVpd.h b/include/asm-ppc64/iSeries/IoHriProcessorVpd.h
deleted file mode 100644
index 73b73d80b8b1..000000000000
--- a/include/asm-ppc64/iSeries/IoHriProcessorVpd.h
+++ /dev/null
@@ -1,86 +0,0 @@
1/*
2 * IoHriProcessorVpd.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _IOHRIPROCESSORVPD_H
20#define _IOHRIPROCESSORVPD_H
21
22#include <asm/types.h>
23
24/*
25 * This struct maps Processor Vpd that is DMAd to SLIC by CSP
26 */
27struct IoHriProcessorVpd {
28 u8 xFormat; // VPD format indicator x00-x00
29 u8 xProcStatus:8; // Processor State x01-x01
30 u8 xSecondaryThreadCount; // Secondary thread cnt x02-x02
31 u8 xSrcType:1; // Src Type x03-x03
32 u8 xSrcSoft:1; // Src stay soft ...
33 u8 xSrcParable:1; // Src parable ...
34 u8 xRsvd1:5; // Reserved ...
35 u16 xHvPhysicalProcIndex; // Hypervisor physical proc index04-x05
36 u16 xRsvd2; // Reserved x06-x07
37 u32 xHwNodeId; // Hardware node id x08-x0B
38 u32 xHwProcId; // Hardware processor id x0C-x0F
39
40 u32 xTypeNum; // Card Type/CCIN number x10-x13
41 u32 xModelNum; // Model/Feature number x14-x17
42 u64 xSerialNum; // Serial number x18-x1F
43 char xPartNum[12]; // Book Part or FPU number x20-x2B
44 char xMfgID[4]; // Manufacturing ID x2C-x2F
45
46 u32 xProcFreq; // Processor Frequency x30-x33
47 u32 xTimeBaseFreq; // Time Base Frequency x34-x37
48
49 u32 xChipEcLevel; // Chip EC Levels x38-x3B
50 u32 xProcIdReg; // PIR SPR value x3C-x3F
51 u32 xPVR; // PVR value x40-x43
52 u8 xRsvd3[12]; // Reserved x44-x4F
53
54 u32 xInstCacheSize; // Instruction cache size in KB x50-x53
55 u32 xInstBlockSize; // Instruction cache block size x54-x57
56 u32 xDataCacheOperandSize; // Data cache operand size x58-x5B
57 u32 xInstCacheOperandSize; // Inst cache operand size x5C-x5F
58
59 u32 xDataL1CacheSizeKB; // L1 data cache size in KB x60-x63
60 u32 xDataL1CacheLineSize; // L1 data cache block size x64-x67
61 u64 xRsvd4; // Reserved x68-x6F
62
63 u32 xDataL2CacheSizeKB; // L2 data cache size in KB x70-x73
64 u32 xDataL2CacheLineSize; // L2 data cache block size x74-x77
65 u64 xRsvd5; // Reserved x78-x7F
66
67 u32 xDataL3CacheSizeKB; // L3 data cache size in KB x80-x83
68 u32 xDataL3CacheLineSize; // L3 data cache block size x84-x87
69 u64 xRsvd6; // Reserved x88-x8F
70
71 u64 xFruLabel; // Card Location Label x90-x97
72 u8 xSlotsOnCard; // Slots on card (0=no slots) x98-x98
73 u8 xPartLocFlag; // Location flag (0-pluggable 1-imbedded) x99-x99
74 u16 xSlotMapIndex; // Index in slot map table x9A-x9B
75 u8 xSmartCardPortNo; // Smart card port number x9C-x9C
76 u8 xRsvd7; // Reserved x9D-x9D
77 u16 xFrameIdAndRackUnit; // Frame ID and rack unit adr x9E-x9F
78
79 u8 xRsvd8[24]; // Reserved xA0-xB7
80
81 char xProcSrc[72]; // CSP format SRC xB8-xFF
82};
83
84extern struct IoHriProcessorVpd xIoHriProcessorVpd[];
85
86#endif /* _IOHRIPROCESSORVPD_H */
diff --git a/include/asm-ppc64/iSeries/ItIplParmsReal.h b/include/asm-ppc64/iSeries/ItIplParmsReal.h
deleted file mode 100644
index ae3417dc599e..000000000000
--- a/include/asm-ppc64/iSeries/ItIplParmsReal.h
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * ItIplParmsReal.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _ITIPLPARMSREAL_H
20#define _ITIPLPARMSREAL_H
21
22/*
23 * This struct maps the IPL Parameters DMA'd from the SP.
24 *
25 * Warning:
26 * This data must map in exactly 64 bytes and match the architecture for
27 * the IPL parms
28 */
29
30#include <asm/types.h>
31
32struct ItIplParmsReal {
33 u8 xFormat; // Defines format of IplParms x00-x00
34 u8 xRsvd01:6; // Reserved x01-x01
35 u8 xAlternateSearch:1; // Alternate search indicator ...
36 u8 xUaSupplied:1; // UA Supplied on programmed IPL...
37 u8 xLsUaFormat; // Format byte for UA x02-x02
38 u8 xRsvd02; // Reserved x03-x03
39 u32 xLsUa; // LS UA x04-x07
40 u32 xUnusedLsLid; // First OS LID to load x08-x0B
41 u16 xLsBusNumber; // LS Bus Number x0C-x0D
42 u8 xLsCardAdr; // LS Card Address x0E-x0E
43 u8 xLsBoardAdr; // LS Board Address x0F-x0F
44 u32 xRsvd03; // Reserved x10-x13
45 u8 xSpcnPresent:1; // SPCN present x14-x14
46 u8 xCpmPresent:1; // CPM present ...
47 u8 xRsvd04:6; // Reserved ...
48 u8 xRsvd05:4; // Reserved x15-x15
49 u8 xKeyLock:4; // Keylock setting ...
50 u8 xRsvd06:6; // Reserved x16-x16
51 u8 xIplMode:2; // Ipl mode (A|B|C|D) ...
52 u8 xHwIplType; // Fast v slow v slow EC HW IPL x17-x17
53 u16 xCpmEnabledIpl:1; // CPM in effect when IPL initiatedx18-x19
54 u16 xPowerOnResetIpl:1; // Indicate POR condition ...
55 u16 xMainStorePreserved:1; // Main Storage is preserved ...
56 u16 xRsvd07:13; // Reserved ...
57 u16 xIplSource:16; // Ipl source x1A-x1B
58 u8 xIplReason:8; // Reason for this IPL x1C-x1C
59 u8 xRsvd08; // Reserved x1D-x1D
60 u16 xRsvd09; // Reserved x1E-x1F
61 u16 xSysBoxType; // System Box Type x20-x21
62 u16 xSysProcType; // System Processor Type x22-x23
63 u32 xRsvd10; // Reserved x24-x27
64 u64 xRsvd11; // Reserved x28-x2F
65 u64 xRsvd12; // Reserved x30-x37
66 u64 xRsvd13; // Reserved x38-x3F
67};
68
69extern struct ItIplParmsReal xItIplParmsReal;
70
71#endif /* _ITIPLPARMSREAL_H */
diff --git a/include/asm-ppc64/iSeries/ItSpCommArea.h b/include/asm-ppc64/iSeries/ItSpCommArea.h
deleted file mode 100644
index 5535f8271c9f..000000000000
--- a/include/asm-ppc64/iSeries/ItSpCommArea.h
+++ /dev/null
@@ -1,37 +0,0 @@
1/*
2 * ItSpCommArea.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef _ITSPCOMMAREA_H
21#define _ITSPCOMMAREA_H
22
23
24struct SpCommArea {
25 u32 xDesc; // Descriptor (only in new formats) 000-003
26 u8 xFormat; // Format (only in new formats) 004-004
27 u8 xRsvd1[11]; // Reserved 005-00F
28 u64 xRawTbAtIplStart; // Raw HW TB value when IPL is started 010-017
29 u64 xRawTodAtIplStart; // Raw HW TOD value when IPL is started 018-01F
30 u64 xBcdTimeAtIplStart; // BCD time when IPL is started 020-027
31 u64 xBcdTimeAtOsStart; // BCD time when OS passed control 028-02F
32 u8 xRsvd2[80]; // Reserved 030-07F
33};
34
35extern struct SpCommArea xSpCommArea;
36
37#endif /* _ITSPCOMMAREA_H */
diff --git a/include/asm-ppc64/iSeries/ItVpdAreas.h b/include/asm-ppc64/iSeries/ItVpdAreas.h
deleted file mode 100644
index 71b3ad24f95a..000000000000
--- a/include/asm-ppc64/iSeries/ItVpdAreas.h
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * ItVpdAreas.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _ITVPDAREAS_H
20#define _ITVPDAREAS_H
21
22/*
23 * This file defines the address and length of all of the VPD area passed to
24 * the OS from PLIC (most of which start from the SP).
25 */
26
27#include <asm/types.h>
28
29/* VPD Entry index is carved in stone - cannot be changed (easily). */
30#define ItVpdCecVpd 0
31#define ItVpdDynamicSpace 1
32#define ItVpdExtVpd 2
33#define ItVpdExtVpdOnPanel 3
34#define ItVpdFirstPaca 4
35#define ItVpdIoVpd 5
36#define ItVpdIplParms 6
37#define ItVpdMsVpd 7
38#define ItVpdPanelVpd 8
39#define ItVpdLpNaca 9
40#define ItVpdBackplaneAndMaybeClockCardVpd 10
41#define ItVpdRecoveryLogBuffer 11
42#define ItVpdSpCommArea 12
43#define ItVpdSpLogBuffer 13
44#define ItVpdSpLogBufferSave 14
45#define ItVpdSpCardVpd 15
46#define ItVpdFirstProcVpd 16
47#define ItVpdApModelVpd 17
48#define ItVpdClockCardVpd 18
49#define ItVpdBusExtCardVpd 19
50#define ItVpdProcCapacityVpd 20
51#define ItVpdInteractiveCapacityVpd 21
52#define ItVpdFirstSlotLabel 22
53#define ItVpdFirstLpQueue 23
54#define ItVpdFirstL3CacheVpd 24
55#define ItVpdFirstProcFruVpd 25
56
57#define ItVpdMaxEntries 26
58
59#define ItDmaMaxEntries 10
60
61#define ItVpdAreasMaxSlotLabels 192
62
63
64struct ItVpdAreas {
65 u32 xSlicDesc; // Descriptor 000-003
66 u16 xSlicSize; // Size of this control block 004-005
67 u16 xPlicAdjustVpdLens:1; // Flag to indicate new interface006-007
68 u16 xRsvd1:15; // Reserved bits ...
69 u16 xSlicVpdEntries; // Number of VPD entries 008-009
70 u16 xSlicDmaEntries; // Number of DMA entries 00A-00B
71 u16 xSlicMaxLogicalProcs; // Maximum logical processors 00C-00D
72 u16 xSlicMaxPhysicalProcs; // Maximum physical processors 00E-00F
73 u16 xSlicDmaToksOffset; // Offset into this of array 010-011
74 u16 xSlicVpdAdrsOffset; // Offset into this of array 012-013
75 u16 xSlicDmaLensOffset; // Offset into this of array 014-015
76 u16 xSlicVpdLensOffset; // Offset into this of array 016-017
77 u16 xSlicMaxSlotLabels; // Maximum number of slot labels018-019
78 u16 xSlicMaxLpQueues; // Maximum number of LP Queues 01A-01B
79 u8 xRsvd2[4]; // Reserved 01C-01F
80 u64 xRsvd3[12]; // Reserved 020-07F
81 u32 xPlicDmaLens[ItDmaMaxEntries];// Array of DMA lengths 080-0A7
82 u32 xPlicDmaToks[ItDmaMaxEntries];// Array of DMA tokens 0A8-0CF
83 u32 xSlicVpdLens[ItVpdMaxEntries];// Array of VPD lengths 0D0-12F
84 void *xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers 130-1EF
85};
86
87extern struct ItVpdAreas itVpdAreas;
88
89#endif /* _ITVPDAREAS_H */
diff --git a/include/asm-ppc64/iSeries/iSeries_irq.h b/include/asm-ppc64/iSeries/iSeries_irq.h
deleted file mode 100644
index 6c9767ac1302..000000000000
--- a/include/asm-ppc64/iSeries/iSeries_irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
1#ifndef __ISERIES_IRQ_H__
2#define __ISERIES_IRQ_H__
3
4extern void iSeries_init_IRQ(void);
5extern int iSeries_allocate_IRQ(HvBusNumber, HvSubBusNumber, HvAgentId);
6extern void iSeries_activate_IRQs(void);
7
8#endif /* __ISERIES_IRQ_H__ */
diff --git a/include/asm-ppc64/iSeries/iSeries_pci.h b/include/asm-ppc64/iSeries/iSeries_pci.h
index 575f611f8b33..a4d88b49fd9f 100644
--- a/include/asm-ppc64/iSeries/iSeries_pci.h
+++ b/include/asm-ppc64/iSeries/iSeries_pci.h
@@ -30,21 +30,19 @@
30 * End Change Activity 30 * End Change Activity
31 */ 31 */
32 32
33#include <asm/iSeries/HvCallPci.h>
34#include <asm/abs_addr.h> 33#include <asm/abs_addr.h>
34#include <asm/prom.h>
35#include <asm/pci-bridge.h>
35 36
36struct pci_dev; /* For Forward Reference */ 37struct pci_dev; /* For Forward Reference */
37struct iSeries_Device_Node;
38 38
39/* 39/*
40 * Gets iSeries Bus, SubBus, DevFn using iSeries_Device_Node structure 40 * Gets iSeries Bus, SubBus, DevFn using device_node structure
41 */ 41 */
42 42
43#define ISERIES_BUS(DevPtr) DevPtr->DsaAddr.Dsa.busNumber 43#define ISERIES_BUS(DevPtr) PCI_DN(DevPtr)->DsaAddr.Dsa.busNumber
44#define ISERIES_SUBBUS(DevPtr) DevPtr->DsaAddr.Dsa.subBusNumber 44#define ISERIES_SUBBUS(DevPtr) PCI_DN(DevPtr)->DsaAddr.Dsa.subBusNumber
45#define ISERIES_DEVICE(DevPtr) DevPtr->DsaAddr.Dsa.deviceId 45#define ISERIES_DEVNODE(PciDev) ((struct device_node *)PciDev->sysdata)
46#define ISERIES_DSA(DevPtr) DevPtr->DsaAddr.DsaAddr
47#define ISERIES_DEVNODE(PciDev) ((struct iSeries_Device_Node *)PciDev->sysdata)
48 46
49#define EADsMaxAgents 7 47#define EADsMaxAgents 7
50 48
@@ -67,22 +65,6 @@ struct iSeries_Device_Node;
67#define ISERIES_HV_ADDR(virtaddr) \ 65#define ISERIES_HV_ADDR(virtaddr) \
68 (0x8000000000000000 | virt_to_abs(virtaddr)) 66 (0x8000000000000000 | virt_to_abs(virtaddr))
69 67
70/*
71 * iSeries Device Information
72 */
73struct iSeries_Device_Node {
74 struct list_head Device_List;
75 struct pci_dev *PciDev;
76 union HvDsaMap DsaAddr; /* Direct Select Address */
77 /* busNumber, subBusNumber, */
78 /* deviceId, barNumber */
79 int DevFn; /* Linux devfn */
80 int Irq; /* Assigned IRQ */
81 int Flags; /* Possible flags(disable/bist)*/
82 u8 LogicalSlot; /* Hv Slot Index for Tces */
83 struct iommu_table *iommu_table;/* Device TCE Table */
84};
85
86extern void iSeries_Device_Information(struct pci_dev*, int); 68extern void iSeries_Device_Information(struct pci_dev*, int);
87 69
88#endif /* _ISERIES_64_PCI_H */ 70#endif /* _ISERIES_64_PCI_H */
diff --git a/include/asm-ppc64/io.h b/include/asm-ppc64/io.h
index 59c958aea4db..bd7c9532d77b 100644
--- a/include/asm-ppc64/io.h
+++ b/include/asm-ppc64/io.h
@@ -15,7 +15,7 @@
15#ifdef CONFIG_PPC_ISERIES 15#ifdef CONFIG_PPC_ISERIES
16#include <asm/iSeries/iSeries_io.h> 16#include <asm/iSeries/iSeries_io.h>
17#endif 17#endif
18#include <asm/memory.h> 18#include <asm/synch.h>
19#include <asm/delay.h> 19#include <asm/delay.h>
20 20
21#include <asm-generic/iomap.h> 21#include <asm-generic/iomap.h>
diff --git a/include/asm-ppc64/iommu.h b/include/asm-ppc64/iommu.h
index c2f3b6e8a42f..f80ec8daf122 100644
--- a/include/asm-ppc64/iommu.h
+++ b/include/asm-ppc64/iommu.h
@@ -1,5 +1,4 @@
1/* 1/*
2 * iommu.h
3 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation 2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
4 * Rewrite, cleanup: 3 * Rewrite, cleanup:
5 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation 4 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
@@ -29,44 +28,11 @@
29 28
30/* 29/*
31 * IOMAP_MAX_ORDER defines the largest contiguous block 30 * IOMAP_MAX_ORDER defines the largest contiguous block
32 * of dma (tce) space we can get. IOMAP_MAX_ORDER = 13 31 * of dma space we can get. IOMAP_MAX_ORDER = 13
33 * allows up to 2**12 pages (4096 * 4096) = 16 MB 32 * allows up to 2**12 pages (4096 * 4096) = 16 MB
34 */ 33 */
35#define IOMAP_MAX_ORDER 13 34#define IOMAP_MAX_ORDER 13
36 35
37/*
38 * Tces come in two formats, one for the virtual bus and a different
39 * format for PCI
40 */
41#define TCE_VB 0
42#define TCE_PCI 1
43
44/* tce_entry
45 * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
46 * abstracted so layout is irrelevant.
47 */
48union tce_entry {
49 unsigned long te_word;
50 struct {
51 unsigned int tb_cacheBits :6; /* Cache hash bits - not used */
52 unsigned int tb_rsvd :6;
53 unsigned long tb_rpn :40; /* Real page number */
54 unsigned int tb_valid :1; /* Tce is valid (vb only) */
55 unsigned int tb_allio :1; /* Tce is valid for all lps (vb only) */
56 unsigned int tb_lpindex :8; /* LpIndex for user of TCE (vb only) */
57 unsigned int tb_pciwr :1; /* Write allowed (pci only) */
58 unsigned int tb_rdwr :1; /* Read allowed (pci), Write allowed (vb) */
59 } te_bits;
60#define te_cacheBits te_bits.tb_cacheBits
61#define te_rpn te_bits.tb_rpn
62#define te_valid te_bits.tb_valid
63#define te_allio te_bits.tb_allio
64#define te_lpindex te_bits.tb_lpindex
65#define te_pciwr te_bits.tb_pciwr
66#define te_rdwr te_bits.tb_rdwr
67};
68
69
70struct iommu_table { 36struct iommu_table {
71 unsigned long it_busno; /* Bus number this table belongs to */ 37 unsigned long it_busno; /* Bus number this table belongs to */
72 unsigned long it_size; /* Size of iommu table in entries */ 38 unsigned long it_size; /* Size of iommu table in entries */
@@ -83,6 +49,7 @@ struct iommu_table {
83}; 49};
84 50
85struct scatterlist; 51struct scatterlist;
52struct device_node;
86 53
87#ifdef CONFIG_PPC_MULTIPLATFORM 54#ifdef CONFIG_PPC_MULTIPLATFORM
88 55
@@ -104,9 +71,8 @@ extern void iommu_devnode_init_pSeries(struct device_node *dn);
104 71
105#ifdef CONFIG_PPC_ISERIES 72#ifdef CONFIG_PPC_ISERIES
106 73
107struct iSeries_Device_Node;
108/* Creates table for an individual device node */ 74/* Creates table for an individual device node */
109extern void iommu_devnode_init_iSeries(struct iSeries_Device_Node *dn); 75extern void iommu_devnode_init_iSeries(struct device_node *dn);
110 76
111#endif /* CONFIG_PPC_ISERIES */ 77#endif /* CONFIG_PPC_ISERIES */
112 78
diff --git a/include/asm-ppc64/irq.h b/include/asm-ppc64/irq.h
deleted file mode 100644
index 99782afb4cde..000000000000
--- a/include/asm-ppc64/irq.h
+++ /dev/null
@@ -1,120 +0,0 @@
1#ifdef __KERNEL__
2#ifndef _ASM_IRQ_H
3#define _ASM_IRQ_H
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/config.h>
13#include <linux/threads.h>
14
15/*
16 * Maximum number of interrupt sources that we can handle.
17 */
18#define NR_IRQS 512
19
20/* this number is used when no interrupt has been assigned */
21#define NO_IRQ (-1)
22
23/*
24 * These constants are used for passing information about interrupt
25 * signal polarity and level/edge sensing to the low-level PIC chip
26 * drivers.
27 */
28#define IRQ_SENSE_MASK 0x1
29#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
30#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
31
32#define IRQ_POLARITY_MASK 0x2
33#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
34#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
35
36/*
37 * IRQ line status macro IRQ_PER_CPU is used
38 */
39#define ARCH_HAS_IRQ_PER_CPU
40
41#define get_irq_desc(irq) (&irq_desc[(irq)])
42
43/* Define a way to iterate across irqs. */
44#define for_each_irq(i) \
45 for ((i) = 0; (i) < NR_IRQS; ++(i))
46
47/* Interrupt numbers are virtual in case they are sparsely
48 * distributed by the hardware.
49 */
50extern unsigned int virt_irq_to_real_map[NR_IRQS];
51
52/* Create a mapping for a real_irq if it doesn't already exist.
53 * Return the virtual irq as a convenience.
54 */
55int virt_irq_create_mapping(unsigned int real_irq);
56void virt_irq_init(void);
57
58static inline unsigned int virt_irq_to_real(unsigned int virt_irq)
59{
60 return virt_irq_to_real_map[virt_irq];
61}
62
63extern unsigned int real_irq_to_virt_slowpath(unsigned int real_irq);
64
65/*
66 * Because many systems have two overlapping names spaces for
67 * interrupts (ISA and XICS for example), and the ISA interrupts
68 * have historically not been easy to renumber, we allow ISA
69 * interrupts to take values 0 - 15, and shift up the remaining
70 * interrupts by 0x10.
71 */
72#define NUM_ISA_INTERRUPTS 0x10
73extern int __irq_offset_value;
74
75static inline int irq_offset_up(int irq)
76{
77 return(irq + __irq_offset_value);
78}
79
80static inline int irq_offset_down(int irq)
81{
82 return(irq - __irq_offset_value);
83}
84
85static inline int irq_offset_value(void)
86{
87 return __irq_offset_value;
88}
89
90static __inline__ int irq_canonicalize(int irq)
91{
92 return irq;
93}
94
95extern int distribute_irqs;
96
97struct irqaction;
98struct pt_regs;
99
100#ifdef CONFIG_IRQSTACKS
101/*
102 * Per-cpu stacks for handling hard and soft interrupts.
103 */
104extern struct thread_info *hardirq_ctx[NR_CPUS];
105extern struct thread_info *softirq_ctx[NR_CPUS];
106
107extern void irq_ctx_init(void);
108extern void call_do_softirq(struct thread_info *tp);
109extern int call_handle_IRQ_event(int irq, struct pt_regs *regs,
110 struct irqaction *action, struct thread_info *tp);
111
112#define __ARCH_HAS_DO_SOFTIRQ
113
114#else
115#define irq_ctx_init()
116
117#endif /* CONFIG_IRQSTACKS */
118
119#endif /* _ASM_IRQ_H */
120#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/kdebug.h b/include/asm-ppc64/kdebug.h
deleted file mode 100644
index d383d161cf8d..000000000000
--- a/include/asm-ppc64/kdebug.h
+++ /dev/null
@@ -1,43 +0,0 @@
1#ifndef _PPC64_KDEBUG_H
2#define _PPC64_KDEBUG_H 1
3
4/* nearly identical to x86_64/i386 code */
5
6#include <linux/notifier.h>
7
8struct pt_regs;
9
10struct die_args {
11 struct pt_regs *regs;
12 const char *str;
13 long err;
14 int trapnr;
15 int signr;
16};
17
18/*
19 Note - you should never unregister because that can race with NMIs.
20 If you really want to do it first unregister - then synchronize_sched -
21 then free.
22 */
23int register_die_notifier(struct notifier_block *nb);
24extern struct notifier_block *ppc64_die_chain;
25
26/* Grossly misnamed. */
27enum die_val {
28 DIE_OOPS = 1,
29 DIE_IABR_MATCH,
30 DIE_DABR_MATCH,
31 DIE_BPT,
32 DIE_SSTEP,
33 DIE_GPF,
34 DIE_PAGE_FAULT,
35};
36
37static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,long err,int trap, int sig)
38{
39 struct die_args args = { .regs=regs, .str=str, .err=err, .trapnr=trap,.signr=sig };
40 return notifier_call_chain(&ppc64_die_chain, val, &args);
41}
42
43#endif
diff --git a/include/asm-ppc64/kmap_types.h b/include/asm-ppc64/kmap_types.h
deleted file mode 100644
index fd1574648223..000000000000
--- a/include/asm-ppc64/kmap_types.h
+++ /dev/null
@@ -1,23 +0,0 @@
1#ifdef __KERNEL__
2#ifndef _ASM_KMAP_TYPES_H
3#define _ASM_KMAP_TYPES_H
4
5enum km_type {
6 KM_BOUNCE_READ,
7 KM_SKB_SUNRPC_DATA,
8 KM_SKB_DATA_SOFTIRQ,
9 KM_USER0,
10 KM_USER1,
11 KM_BIO_SRC_IRQ,
12 KM_BIO_DST_IRQ,
13 KM_PTE0,
14 KM_PTE1,
15 KM_IRQ0,
16 KM_IRQ1,
17 KM_SOFTIRQ0,
18 KM_SOFTIRQ1,
19 KM_TYPE_NR
20};
21
22#endif
23#endif /* __KERNEL__ */
diff --git a/include/asm-ppc64/kprobes.h b/include/asm-ppc64/kprobes.h
deleted file mode 100644
index d9129d2b038e..000000000000
--- a/include/asm-ppc64/kprobes.h
+++ /dev/null
@@ -1,67 +0,0 @@
1#ifndef _ASM_KPROBES_H
2#define _ASM_KPROBES_H
3/*
4 * Kernel Probes (KProbes)
5 * include/asm-ppc64/kprobes.h
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 *
21 * Copyright (C) IBM Corporation, 2002, 2004
22 *
23 * 2002-Oct Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
24 * Probes initial implementation ( includes suggestions from
25 * Rusty Russell).
26 * 2004-Nov Modified for PPC64 by Ananth N Mavinakayanahalli
27 * <ananth@in.ibm.com>
28 */
29#include <linux/types.h>
30#include <linux/ptrace.h>
31
32struct pt_regs;
33
34typedef unsigned int kprobe_opcode_t;
35#define BREAKPOINT_INSTRUCTION 0x7fe00008 /* trap */
36#define MAX_INSN_SIZE 1
37
38#define IS_TW(instr) (((instr) & 0xfc0007fe) == 0x7c000008)
39#define IS_TD(instr) (((instr) & 0xfc0007fe) == 0x7c000088)
40#define IS_TDI(instr) (((instr) & 0xfc000000) == 0x08000000)
41#define IS_TWI(instr) (((instr) & 0xfc000000) == 0x0c000000)
42
43#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)((func_descr_t *)pentry)
44
45#define is_trap(instr) (IS_TW(instr) || IS_TD(instr) || \
46 IS_TWI(instr) || IS_TDI(instr))
47
48#define ARCH_SUPPORTS_KRETPROBES
49void kretprobe_trampoline(void);
50
51/* Architecture specific copy of original instruction */
52struct arch_specific_insn {
53 /* copy of original instruction */
54 kprobe_opcode_t *insn;
55};
56
57#ifdef CONFIG_KPROBES
58extern int kprobe_exceptions_notify(struct notifier_block *self,
59 unsigned long val, void *data);
60#else /* !CONFIG_KPROBES */
61static inline int kprobe_exceptions_notify(struct notifier_block *self,
62 unsigned long val, void *data)
63{
64 return 0;
65}
66#endif
67#endif /* _ASM_KPROBES_H */
diff --git a/include/asm-ppc64/lmb.h b/include/asm-ppc64/lmb.h
deleted file mode 100644
index de91e034bd98..000000000000
--- a/include/asm-ppc64/lmb.h
+++ /dev/null
@@ -1,81 +0,0 @@
1#ifndef _PPC64_LMB_H
2#define _PPC64_LMB_H
3
4/*
5 * Definitions for talking to the Open Firmware PROM on
6 * Power Macintosh computers.
7 *
8 * Copyright (C) 2001 Peter Bergner, IBM Corp.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/init.h>
17#include <asm/prom.h>
18
19#define MAX_LMB_REGIONS 128
20
21#define LMB_ALLOC_ANYWHERE 0
22
23struct lmb_property {
24 unsigned long base;
25 unsigned long size;
26};
27
28struct lmb_region {
29 unsigned long cnt;
30 unsigned long size;
31 struct lmb_property region[MAX_LMB_REGIONS+1];
32};
33
34struct lmb {
35 unsigned long debug;
36 unsigned long rmo_size;
37 struct lmb_region memory;
38 struct lmb_region reserved;
39};
40
41extern struct lmb lmb;
42
43extern void __init lmb_init(void);
44extern void __init lmb_analyze(void);
45extern long __init lmb_add(unsigned long, unsigned long);
46extern long __init lmb_reserve(unsigned long, unsigned long);
47extern unsigned long __init lmb_alloc(unsigned long, unsigned long);
48extern unsigned long __init lmb_alloc_base(unsigned long, unsigned long,
49 unsigned long);
50extern unsigned long __init lmb_phys_mem_size(void);
51extern unsigned long __init lmb_end_of_DRAM(void);
52extern unsigned long __init lmb_abs_to_phys(unsigned long);
53extern void __init lmb_enforce_memory_limit(void);
54
55extern void lmb_dump_all(void);
56
57extern unsigned long io_hole_start;
58
59static inline unsigned long
60lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
61{
62 return type->region[region_nr].size;
63}
64static inline unsigned long
65lmb_size_pages(struct lmb_region *type, unsigned long region_nr)
66{
67 return lmb_size_bytes(type, region_nr) >> PAGE_SHIFT;
68}
69static inline unsigned long
70lmb_start_pfn(struct lmb_region *type, unsigned long region_nr)
71{
72 return type->region[region_nr].base >> PAGE_SHIFT;
73}
74static inline unsigned long
75lmb_end_pfn(struct lmb_region *type, unsigned long region_nr)
76{
77 return lmb_start_pfn(type, region_nr) +
78 lmb_size_pages(type, region_nr);
79}
80
81#endif /* _PPC64_LMB_H */
diff --git a/include/asm-ppc64/machdep.h b/include/asm-ppc64/machdep.h
index 8027160ec96d..d35d9d3e44cf 100644
--- a/include/asm-ppc64/machdep.h
+++ b/include/asm-ppc64/machdep.h
@@ -56,9 +56,8 @@ struct machdep_calls {
56 unsigned long vflags, 56 unsigned long vflags,
57 unsigned long rflags); 57 unsigned long rflags);
58 long (*hpte_remove)(unsigned long hpte_group); 58 long (*hpte_remove)(unsigned long hpte_group);
59 void (*flush_hash_range)(unsigned long context, 59 void (*flush_hash_range)(unsigned long number, int local);
60 unsigned long number, 60
61 int local);
62 /* special for kexec, to be called in real mode, linar mapping is 61 /* special for kexec, to be called in real mode, linar mapping is
63 * destroyed as well */ 62 * destroyed as well */
64 void (*hpte_clear_all)(void); 63 void (*hpte_clear_all)(void);
diff --git a/include/asm-ppc64/memory.h b/include/asm-ppc64/memory.h
deleted file mode 100644
index af53ffb55726..000000000000
--- a/include/asm-ppc64/memory.h
+++ /dev/null
@@ -1,61 +0,0 @@
1#ifndef _ASM_PPC64_MEMORY_H_
2#define _ASM_PPC64_MEMORY_H_
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <linux/config.h>
12
13/*
14 * Arguably the bitops and *xchg operations don't imply any memory barrier
15 * or SMP ordering, but in fact a lot of drivers expect them to imply
16 * both, since they do on x86 cpus.
17 */
18#ifdef CONFIG_SMP
19#define EIEIO_ON_SMP "eieio\n"
20#define ISYNC_ON_SMP "\n\tisync"
21#define SYNC_ON_SMP "lwsync\n\t"
22#else
23#define EIEIO_ON_SMP
24#define ISYNC_ON_SMP
25#define SYNC_ON_SMP
26#endif
27
28static inline void eieio(void)
29{
30 __asm__ __volatile__ ("eieio" : : : "memory");
31}
32
33static inline void isync(void)
34{
35 __asm__ __volatile__ ("isync" : : : "memory");
36}
37
38#ifdef CONFIG_SMP
39#define eieio_on_smp() eieio()
40#define isync_on_smp() isync()
41#else
42#define eieio_on_smp() __asm__ __volatile__("": : :"memory")
43#define isync_on_smp() __asm__ __volatile__("": : :"memory")
44#endif
45
46/* Macros for adjusting thread priority (hardware multi-threading) */
47#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
48#define HMT_low() asm volatile("or 1,1,1 # low priority")
49#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
50#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
51#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
52#define HMT_high() asm volatile("or 3,3,3 # high priority")
53
54#define HMT_VERY_LOW "\tor 31,31,31 # very low priority\n"
55#define HMT_LOW "\tor 1,1,1 # low priority\n"
56#define HMT_MEDIUM_LOW "\tor 6,6,6 # medium low priority\n"
57#define HMT_MEDIUM "\tor 2,2,2 # medium priority\n"
58#define HMT_MEDIUM_HIGH "\tor 5,5,5 # medium high priority\n"
59#define HMT_HIGH "\tor 3,3,3 # high priority\n"
60
61#endif
diff --git a/include/asm-ppc64/mmu.h b/include/asm-ppc64/mmu.h
index 7bc42eb087ad..e0505acb77d9 100644
--- a/include/asm-ppc64/mmu.h
+++ b/include/asm-ppc64/mmu.h
@@ -14,6 +14,7 @@
14#define _PPC64_MMU_H_ 14#define _PPC64_MMU_H_
15 15
16#include <linux/config.h> 16#include <linux/config.h>
17#include <asm/ppc_asm.h> /* for ASM_CONST */
17#include <asm/page.h> 18#include <asm/page.h>
18 19
19/* 20/*
@@ -29,7 +30,7 @@
29 30
30/* Location of cpu0's segment table */ 31/* Location of cpu0's segment table */
31#define STAB0_PAGE 0x6 32#define STAB0_PAGE 0x6
32#define STAB0_PHYS_ADDR (STAB0_PAGE<<PAGE_SHIFT) 33#define STAB0_PHYS_ADDR (STAB0_PAGE<<12)
33 34
34#ifndef __ASSEMBLY__ 35#ifndef __ASSEMBLY__
35extern char initial_stab[]; 36extern char initial_stab[];
@@ -205,6 +206,10 @@ extern long native_hpte_insert(unsigned long hpte_group, unsigned long va,
205 unsigned long prpn, 206 unsigned long prpn,
206 unsigned long vflags, unsigned long rflags); 207 unsigned long vflags, unsigned long rflags);
207 208
209extern long iSeries_hpte_bolt_or_insert(unsigned long hpte_group,
210 unsigned long va, unsigned long prpn,
211 unsigned long vflags, unsigned long rflags);
212
208extern void stabs_alloc(void); 213extern void stabs_alloc(void);
209 214
210#endif /* __ASSEMBLY__ */ 215#endif /* __ASSEMBLY__ */
diff --git a/include/asm-ppc64/of_device.h b/include/asm-ppc64/of_device.h
deleted file mode 100644
index 7bc136e22590..000000000000
--- a/include/asm-ppc64/of_device.h
+++ /dev/null
@@ -1,2 +0,0 @@
1#include <asm-ppc/of_device.h>
2
diff --git a/include/asm-ppc64/oprofile_impl.h b/include/asm-ppc64/oprofile_impl.h
deleted file mode 100644
index b04f1dfb1421..000000000000
--- a/include/asm-ppc64/oprofile_impl.h
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
3 *
4 * Based on alpha version.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef OP_IMPL_H
13#define OP_IMPL_H 1
14
15#define OP_MAX_COUNTER 8
16
17/* Per-counter configuration as set via oprofilefs. */
18struct op_counter_config {
19 unsigned long valid;
20 unsigned long enabled;
21 unsigned long event;
22 unsigned long count;
23 unsigned long kernel;
24 /* We dont support per counter user/kernel selection */
25 unsigned long user;
26 unsigned long unit_mask;
27};
28
29/* System-wide configuration as set via oprofilefs. */
30struct op_system_config {
31 unsigned long mmcr0;
32 unsigned long mmcr1;
33 unsigned long mmcra;
34 unsigned long enable_kernel;
35 unsigned long enable_user;
36 unsigned long backtrace_spinlocks;
37};
38
39/* Per-arch configuration */
40struct op_ppc64_model {
41 void (*reg_setup) (struct op_counter_config *,
42 struct op_system_config *,
43 int num_counters);
44 void (*cpu_setup) (void *);
45 void (*start) (struct op_counter_config *);
46 void (*stop) (void);
47 void (*handle_interrupt) (struct pt_regs *,
48 struct op_counter_config *);
49 int num_counters;
50};
51
52extern struct op_ppc64_model op_model_rs64;
53extern struct op_ppc64_model op_model_power4;
54
55static inline unsigned int ctr_read(unsigned int i)
56{
57 switch(i) {
58 case 0:
59 return mfspr(SPRN_PMC1);
60 case 1:
61 return mfspr(SPRN_PMC2);
62 case 2:
63 return mfspr(SPRN_PMC3);
64 case 3:
65 return mfspr(SPRN_PMC4);
66 case 4:
67 return mfspr(SPRN_PMC5);
68 case 5:
69 return mfspr(SPRN_PMC6);
70 case 6:
71 return mfspr(SPRN_PMC7);
72 case 7:
73 return mfspr(SPRN_PMC8);
74 default:
75 return 0;
76 }
77}
78
79static inline void ctr_write(unsigned int i, unsigned int val)
80{
81 switch(i) {
82 case 0:
83 mtspr(SPRN_PMC1, val);
84 break;
85 case 1:
86 mtspr(SPRN_PMC2, val);
87 break;
88 case 2:
89 mtspr(SPRN_PMC3, val);
90 break;
91 case 3:
92 mtspr(SPRN_PMC4, val);
93 break;
94 case 4:
95 mtspr(SPRN_PMC5, val);
96 break;
97 case 5:
98 mtspr(SPRN_PMC6, val);
99 break;
100 case 6:
101 mtspr(SPRN_PMC7, val);
102 break;
103 case 7:
104 mtspr(SPRN_PMC8, val);
105 break;
106 default:
107 break;
108 }
109}
110
111#endif
diff --git a/include/asm-ppc64/page.h b/include/asm-ppc64/page.h
index a15422bcf30d..d404431f0a9a 100644
--- a/include/asm-ppc64/page.h
+++ b/include/asm-ppc64/page.h
@@ -11,13 +11,7 @@
11 */ 11 */
12 12
13#include <linux/config.h> 13#include <linux/config.h>
14 14#include <asm/ppc_asm.h> /* for ASM_CONST */
15#ifdef __ASSEMBLY__
16 #define ASM_CONST(x) x
17#else
18 #define __ASM_CONST(x) x##UL
19 #define ASM_CONST(x) __ASM_CONST(x)
20#endif
21 15
22/* PAGE_SHIFT determines the page size */ 16/* PAGE_SHIFT determines the page size */
23#define PAGE_SHIFT 12 17#define PAGE_SHIFT 12
diff --git a/include/asm-ppc64/pci-bridge.h b/include/asm-ppc64/pci-bridge.h
index d8991389ab39..56863df18232 100644
--- a/include/asm-ppc64/pci-bridge.h
+++ b/include/asm-ppc64/pci-bridge.h
@@ -3,6 +3,9 @@
3#define _ASM_PCI_BRIDGE_H 3#define _ASM_PCI_BRIDGE_H
4 4
5#include <linux/pci.h> 5#include <linux/pci.h>
6#include <linux/list.h>
7
8#include <asm/iSeries/HvCallPci.h>
6 9
7/* 10/*
8 * This program is free software; you can redistribute it and/or 11 * This program is free software; you can redistribute it and/or
@@ -71,6 +74,15 @@ struct pci_dn {
71 struct iommu_table *iommu_table; /* for phb's or bridges */ 74 struct iommu_table *iommu_table; /* for phb's or bridges */
72 struct pci_dev *pcidev; /* back-pointer to the pci device */ 75 struct pci_dev *pcidev; /* back-pointer to the pci device */
73 struct device_node *node; /* back-pointer to the device_node */ 76 struct device_node *node; /* back-pointer to the device_node */
77#ifdef CONFIG_PPC_ISERIES
78 struct list_head Device_List;
79 union HvDsaMap DsaAddr; /* Direct Select Address */
80 /* busNumber, subBusNumber, */
81 /* deviceId, barNumber */
82 int Irq; /* Assigned IRQ */
83 int Flags; /* Possible flags(disable/bist)*/
84 u8 LogicalSlot; /* Hv Slot Index for Tces */
85#endif
74 u32 config_space[16]; /* saved PCI config space */ 86 u32 config_space[16]; /* saved PCI config space */
75}; 87};
76 88
@@ -96,6 +108,16 @@ static inline struct device_node *pci_device_to_OF_node(struct pci_dev *dev)
96 return fetch_dev_dn(dev); 108 return fetch_dev_dn(dev);
97} 109}
98 110
111static inline int pci_device_from_OF_node(struct device_node *np,
112 u8 *bus, u8 *devfn)
113{
114 if (!PCI_DN(np))
115 return -ENODEV;
116 *bus = PCI_DN(np)->busno;
117 *devfn = PCI_DN(np)->devfn;
118 return 0;
119}
120
99static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus) 121static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
100{ 122{
101 if (bus->self) 123 if (bus->self)
diff --git a/include/asm-ppc64/posix_types.h b/include/asm-ppc64/posix_types.h
deleted file mode 100644
index 516de7201b5d..000000000000
--- a/include/asm-ppc64/posix_types.h
+++ /dev/null
@@ -1,119 +0,0 @@
1#ifndef _PPC64_POSIX_TYPES_H
2#define _PPC64_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15typedef unsigned long __kernel_ino_t;
16typedef unsigned long __kernel_nlink_t;
17typedef unsigned int __kernel_mode_t;
18typedef long __kernel_off_t;
19typedef long long __kernel_loff_t;
20typedef int __kernel_pid_t;
21typedef int __kernel_ipc_pid_t;
22typedef unsigned int __kernel_uid_t;
23typedef unsigned int __kernel_gid_t;
24typedef unsigned long __kernel_size_t;
25typedef long __kernel_ssize_t;
26typedef long __kernel_ptrdiff_t;
27typedef long __kernel_time_t;
28typedef int __kernel_timer_t;
29typedef int __kernel_clockid_t;
30typedef long __kernel_suseconds_t;
31typedef long __kernel_clock_t;
32typedef int __kernel_daddr_t;
33typedef char * __kernel_caddr_t;
34typedef unsigned short __kernel_uid16_t;
35typedef unsigned short __kernel_gid16_t;
36typedef unsigned int __kernel_uid32_t;
37typedef unsigned int __kernel_gid32_t;
38
39typedef unsigned int __kernel_old_uid_t;
40typedef unsigned int __kernel_old_gid_t;
41typedef unsigned long __kernel_old_dev_t;
42
43typedef struct {
44 int val[2];
45} __kernel_fsid_t;
46
47#ifndef __GNUC__
48
49#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
50#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
51#define __FD_ISSET(d, set) (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
52#define __FD_ZERO(set) \
53 ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
54
55#else /* __GNUC__ */
56
57#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
58 || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
59/* With GNU C, use inline functions instead so args are evaluated only once: */
60
61#undef __FD_SET
62static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
63{
64 unsigned long _tmp = fd / __NFDBITS;
65 unsigned long _rem = fd % __NFDBITS;
66 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
67}
68
69#undef __FD_CLR
70static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
71{
72 unsigned long _tmp = fd / __NFDBITS;
73 unsigned long _rem = fd % __NFDBITS;
74 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
75}
76
77#undef __FD_ISSET
78static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
79{
80 unsigned long _tmp = fd / __NFDBITS;
81 unsigned long _rem = fd % __NFDBITS;
82 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
83}
84
85/*
86 * This will unroll the loop for the normal constant case (8 ints,
87 * for a 256-bit fd_set)
88 */
89#undef __FD_ZERO
90static __inline__ void __FD_ZERO(__kernel_fd_set *p)
91{
92 unsigned long *tmp = (unsigned long *)p->fds_bits;
93 int i;
94
95 if (__builtin_constant_p(__FDSET_LONGS)) {
96 switch (__FDSET_LONGS) {
97 case 16:
98 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
99 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
100
101 case 8:
102 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
103
104 case 4:
105 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
106 return;
107 }
108 }
109 i = __FDSET_LONGS;
110 while (i) {
111 i--;
112 *tmp = 0;
113 tmp++;
114 }
115}
116
117#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
118#endif /* __GNUC__ */
119#endif /* _PPC64_POSIX_TYPES_H */
diff --git a/include/asm-ppc64/ppc_asm.h b/include/asm-ppc64/ppc_asm.h
deleted file mode 100644
index 9031d8a29aca..000000000000
--- a/include/asm-ppc64/ppc_asm.h
+++ /dev/null
@@ -1,242 +0,0 @@
1/*
2 * arch/ppc64/kernel/ppc_asm.h
3 *
4 * Definitions used by various bits of low-level assembly code on PowerPC.
5 *
6 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
12 */
13
14#ifndef _PPC64_PPC_ASM_H
15#define _PPC64_PPC_ASM_H
16/*
17 * Macros for storing registers into and loading registers from
18 * exception frames.
19 */
20#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
21#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
22#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
23#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
24#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
25#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
26#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
27#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
28#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
29#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
30
31#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
32#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
33
34#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
35#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
36#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
37#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
38#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
39#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
40#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
41#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
42#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
43#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
44#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
45#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
46
47#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
48#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
49#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
50#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
51#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
52#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
53#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
54#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
55#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
56#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
57#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
58#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
59
60/* Macros to adjust thread priority for Iseries hardware multithreading */
61#define HMT_LOW or 1,1,1
62#define HMT_MEDIUM or 2,2,2
63#define HMT_HIGH or 3,3,3
64
65/* Insert the high 32 bits of the MSR into what will be the new
66 MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
67 bits. */
68
69#define FIX_SRR1(ra, rb) \
70 mr rb,ra; \
71 mfmsr ra; \
72 rldimi ra,rb,0,32
73
74#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
75
76/*
77 * LOADADDR( rn, name )
78 * loads the address of 'name' into 'rn'
79 *
80 * LOADBASE( rn, name )
81 * loads the address (less the low 16 bits) of 'name' into 'rn'
82 * suitable for base+disp addressing
83 */
84#define LOADADDR(rn,name) \
85 lis rn,name##@highest; \
86 ori rn,rn,name##@higher; \
87 rldicr rn,rn,32,31; \
88 oris rn,rn,name##@h; \
89 ori rn,rn,name##@l
90
91#define LOADBASE(rn,name) \
92 lis rn,name@highest; \
93 ori rn,rn,name@higher; \
94 rldicr rn,rn,32,31; \
95 oris rn,rn,name@ha
96
97
98#define SET_REG_TO_CONST(reg, value) \
99 lis reg,(((value)>>48)&0xFFFF); \
100 ori reg,reg,(((value)>>32)&0xFFFF); \
101 rldicr reg,reg,32,31; \
102 oris reg,reg,(((value)>>16)&0xFFFF); \
103 ori reg,reg,((value)&0xFFFF);
104
105#define SET_REG_TO_LABEL(reg, label) \
106 lis reg,(label)@highest; \
107 ori reg,reg,(label)@higher; \
108 rldicr reg,reg,32,31; \
109 oris reg,reg,(label)@h; \
110 ori reg,reg,(label)@l;
111
112
113/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
114 * Then we can easily do this with one asm insn. -Peter
115 */
116#define tophys(rd,rs) \
117 lis rd,((KERNELBASE>>48)&0xFFFF); \
118 rldicr rd,rd,32,31; \
119 sub rd,rs,rd
120
121#define tovirt(rd,rs) \
122 lis rd,((KERNELBASE>>48)&0xFFFF); \
123 rldicr rd,rd,32,31; \
124 add rd,rs,rd
125
126/* Condition Register Bit Fields */
127
128#define cr0 0
129#define cr1 1
130#define cr2 2
131#define cr3 3
132#define cr4 4
133#define cr5 5
134#define cr6 6
135#define cr7 7
136
137
138/* General Purpose Registers (GPRs) */
139
140#define r0 0
141#define r1 1
142#define r2 2
143#define r3 3
144#define r4 4
145#define r5 5
146#define r6 6
147#define r7 7
148#define r8 8
149#define r9 9
150#define r10 10
151#define r11 11
152#define r12 12
153#define r13 13
154#define r14 14
155#define r15 15
156#define r16 16
157#define r17 17
158#define r18 18
159#define r19 19
160#define r20 20
161#define r21 21
162#define r22 22
163#define r23 23
164#define r24 24
165#define r25 25
166#define r26 26
167#define r27 27
168#define r28 28
169#define r29 29
170#define r30 30
171#define r31 31
172
173
174/* Floating Point Registers (FPRs) */
175
176#define fr0 0
177#define fr1 1
178#define fr2 2
179#define fr3 3
180#define fr4 4
181#define fr5 5
182#define fr6 6
183#define fr7 7
184#define fr8 8
185#define fr9 9
186#define fr10 10
187#define fr11 11
188#define fr12 12
189#define fr13 13
190#define fr14 14
191#define fr15 15
192#define fr16 16
193#define fr17 17
194#define fr18 18
195#define fr19 19
196#define fr20 20
197#define fr21 21
198#define fr22 22
199#define fr23 23
200#define fr24 24
201#define fr25 25
202#define fr26 26
203#define fr27 27
204#define fr28 28
205#define fr29 29
206#define fr30 30
207#define fr31 31
208
209#define vr0 0
210#define vr1 1
211#define vr2 2
212#define vr3 3
213#define vr4 4
214#define vr5 5
215#define vr6 6
216#define vr7 7
217#define vr8 8
218#define vr9 9
219#define vr10 10
220#define vr11 11
221#define vr12 12
222#define vr13 13
223#define vr14 14
224#define vr15 15
225#define vr16 16
226#define vr17 17
227#define vr18 18
228#define vr19 19
229#define vr20 20
230#define vr21 21
231#define vr22 22
232#define vr23 23
233#define vr24 24
234#define vr25 25
235#define vr26 26
236#define vr27 27
237#define vr28 28
238#define vr29 29
239#define vr30 30
240#define vr31 31
241
242#endif /* _PPC64_PPC_ASM_H */
diff --git a/include/asm-ppc64/processor.h b/include/asm-ppc64/processor.h
deleted file mode 100644
index 4146189006e3..000000000000
--- a/include/asm-ppc64/processor.h
+++ /dev/null
@@ -1,558 +0,0 @@
1#ifndef __ASM_PPC64_PROCESSOR_H
2#define __ASM_PPC64_PROCESSOR_H
3
4/*
5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/stringify.h>
14#ifndef __ASSEMBLY__
15#include <linux/config.h>
16#include <asm/atomic.h>
17#include <asm/ppcdebug.h>
18#include <asm/a.out.h>
19#endif
20#include <asm/ptrace.h>
21#include <asm/types.h>
22#include <asm/systemcfg.h>
23#include <asm/cputable.h>
24
25/* Machine State Register (MSR) Fields */
26#define MSR_SF_LG 63 /* Enable 64 bit mode */
27#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
28#define MSR_HV_LG 60 /* Hypervisor state */
29#define MSR_VEC_LG 25 /* Enable AltiVec */
30#define MSR_POW_LG 18 /* Enable Power Management */
31#define MSR_WE_LG 18 /* Wait State Enable */
32#define MSR_TGPR_LG 17 /* TLB Update registers in use */
33#define MSR_CE_LG 17 /* Critical Interrupt Enable */
34#define MSR_ILE_LG 16 /* Interrupt Little Endian */
35#define MSR_EE_LG 15 /* External Interrupt Enable */
36#define MSR_PR_LG 14 /* Problem State / Privilege Level */
37#define MSR_FP_LG 13 /* Floating Point enable */
38#define MSR_ME_LG 12 /* Machine Check Enable */
39#define MSR_FE0_LG 11 /* Floating Exception mode 0 */
40#define MSR_SE_LG 10 /* Single Step */
41#define MSR_BE_LG 9 /* Branch Trace */
42#define MSR_DE_LG 9 /* Debug Exception Enable */
43#define MSR_FE1_LG 8 /* Floating Exception mode 1 */
44#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
45#define MSR_IR_LG 5 /* Instruction Relocate */
46#define MSR_DR_LG 4 /* Data Relocate */
47#define MSR_PE_LG 3 /* Protection Enable */
48#define MSR_PX_LG 2 /* Protection Exclusive Mode */
49#define MSR_PMM_LG 2 /* Performance monitor */
50#define MSR_RI_LG 1 /* Recoverable Exception */
51#define MSR_LE_LG 0 /* Little Endian */
52
53#ifdef __ASSEMBLY__
54#define __MASK(X) (1<<(X))
55#else
56#define __MASK(X) (1UL<<(X))
57#endif
58
59#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
60#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
61#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
62#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
63#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
64#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
65#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
66#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
67#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
68#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
69#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
70#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
71#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
72#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
73#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
74#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
75#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
76#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
77#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
78#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
79#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
80#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
81#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
82#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
83#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
84#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
85
86#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
87#define MSR_KERNEL MSR_ | MSR_SF | MSR_HV
88
89#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
90#define MSR_USER64 MSR_USER32 | MSR_SF
91
92/* Floating Point Status and Control Register (FPSCR) Fields */
93
94#define FPSCR_FX 0x80000000 /* FPU exception summary */
95#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
96#define FPSCR_VX 0x20000000 /* Invalid operation summary */
97#define FPSCR_OX 0x10000000 /* Overflow exception summary */
98#define FPSCR_UX 0x08000000 /* Underflow exception summary */
99#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
100#define FPSCR_XX 0x02000000 /* Inexact exception summary */
101#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
102#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
103#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
104#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
105#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
106#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
107#define FPSCR_FR 0x00040000 /* Fraction rounded */
108#define FPSCR_FI 0x00020000 /* Fraction inexact */
109#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
110#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
111#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
112#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
113#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
114#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
115#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
116#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
117#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
118#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
119#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
120#define FPSCR_RN 0x00000003 /* FPU rounding control */
121
122/* Special Purpose Registers (SPRNs)*/
123
124#define SPRN_CTR 0x009 /* Count Register */
125#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
126#define DABR_TRANSLATION (1UL << 2)
127#define SPRN_DAR 0x013 /* Data Address Register */
128#define SPRN_DEC 0x016 /* Decrement Register */
129#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
130#define DSISR_NOHPTE 0x40000000 /* no translation found */
131#define DSISR_PROTFAULT 0x08000000 /* protection fault */
132#define DSISR_ISSTORE 0x02000000 /* access was a store */
133#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
134#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
135#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
136#define SPRN_MSRDORM 0x3F1 /* Hardware Implementation Register 1 */
137#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
138#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
139#define SPRN_NIADORM 0x3F3 /* Hardware Implementation Register 2 */
140#define SPRN_HID4 0x3F4 /* 970 HID4 */
141#define SPRN_HID5 0x3F6 /* 970 HID5 */
142#define SPRN_HID6 0x3F9 /* BE HID 6 */
143#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
144#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
145#define SPRN_TSCR 0x399 /* Thread switch control on BE */
146#define SPRN_TTR 0x39A /* Thread switch timeout on BE */
147#define TSCR_DEC_ENABLE 0x200000 /* Decrementer Interrupt */
148#define TSCR_EE_ENABLE 0x100000 /* External Interrupt */
149#define TSCR_EE_BOOST 0x080000 /* External Interrupt Boost */
150#define SPRN_TSC 0x3FD /* Thread switch control on others */
151#define SPRN_TST 0x3FC /* Thread switch timeout on others */
152#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
153#define SPRN_LR 0x008 /* Link Register */
154#define SPRN_PIR 0x3FF /* Processor Identification Register */
155#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
156#define SPRN_PURR 0x135 /* Processor Utilization of Resources Register */
157#define SPRN_PVR 0x11F /* Processor Version Register */
158#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
159#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
160#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
161#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
162#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
163#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
164#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
165#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
166#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
167#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
168#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
169#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
170#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, W/O) */
171#define SPRN_TBWU 0x11D /* Time Base Write Upper Register (super, W/O) */
172#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
173#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
174#define SPRN_XER 0x001 /* Fixed Point Exception Register */
175#define SPRN_VRSAVE 0x100 /* Vector save */
176#define SPRN_CTRLF 0x088
177#define SPRN_CTRLT 0x098
178#define CTRL_RUNLATCH 0x1
179
180/* Performance monitor SPRs */
181#define SPRN_SIAR 780
182#define SPRN_SDAR 781
183#define SPRN_MMCRA 786
184#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
185#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
186#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
187#define SPRN_PMC1 787
188#define SPRN_PMC2 788
189#define SPRN_PMC3 789
190#define SPRN_PMC4 790
191#define SPRN_PMC5 791
192#define SPRN_PMC6 792
193#define SPRN_PMC7 793
194#define SPRN_PMC8 794
195#define SPRN_MMCR0 795
196#define MMCR0_FC 0x80000000UL /* freeze counters. set to 1 on a perfmon exception */
197#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
198#define MMCR0_KERNEL_DISABLE MMCR0_FCS
199#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
200#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
201#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
202#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
203#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
204#define MMCR0_FCECE 0x02000000UL /* freeze counters on enabled condition or event */
205/* time base exception enable */
206#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
207#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
208#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
209#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
210#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
211#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
212#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
213#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
214#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
215#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
216#define SPRN_MMCR1 798
217
218/* Short-hand versions for a number of the above SPRNs */
219
220#define CTR SPRN_CTR /* Counter Register */
221#define DAR SPRN_DAR /* Data Address Register */
222#define DABR SPRN_DABR /* Data Address Breakpoint Register */
223#define DEC SPRN_DEC /* Decrement Register */
224#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
225#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
226#define MSRDORM SPRN_MSRDORM /* MSR Dormant Register */
227#define NIADORM SPRN_NIADORM /* NIA Dormant Register */
228#define TSC SPRN_TSC /* Thread switch control */
229#define TST SPRN_TST /* Thread switch timeout */
230#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
231#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
232#define __LR SPRN_LR
233#define PVR SPRN_PVR /* Processor Version */
234#define PIR SPRN_PIR /* Processor ID */
235#define PURR SPRN_PURR /* Processor Utilization of Resource Register */
236#define SDR1 SPRN_SDR1 /* MMU hash base register */
237#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
238#define SPR1 SPRN_SPRG1
239#define SPR2 SPRN_SPRG2
240#define SPR3 SPRN_SPRG3
241#define SPRG0 SPRN_SPRG0
242#define SPRG1 SPRN_SPRG1
243#define SPRG2 SPRN_SPRG2
244#define SPRG3 SPRN_SPRG3
245#define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
246#define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
247#define TBRL SPRN_TBRL /* Time Base Read Lower Register */
248#define TBRU SPRN_TBRU /* Time Base Read Upper Register */
249#define TBWL SPRN_TBWL /* Time Base Write Lower Register */
250#define TBWU SPRN_TBWU /* Time Base Write Upper Register */
251#define XER SPRN_XER
252
253/* Processor Version Register (PVR) field extraction */
254
255#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
256#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
257
258/* Processor Version Numbers */
259#define PV_NORTHSTAR 0x0033
260#define PV_PULSAR 0x0034
261#define PV_POWER4 0x0035
262#define PV_ICESTAR 0x0036
263#define PV_SSTAR 0x0037
264#define PV_POWER4p 0x0038
265#define PV_970 0x0039
266#define PV_POWER5 0x003A
267#define PV_POWER5p 0x003B
268#define PV_970FX 0x003C
269#define PV_630 0x0040
270#define PV_630p 0x0041
271#define PV_970MP 0x0044
272#define PV_BE 0x0070
273
274/* Platforms supported by PPC64 */
275#define PLATFORM_PSERIES 0x0100
276#define PLATFORM_PSERIES_LPAR 0x0101
277#define PLATFORM_ISERIES_LPAR 0x0201
278#define PLATFORM_LPAR 0x0001
279#define PLATFORM_POWERMAC 0x0400
280#define PLATFORM_MAPLE 0x0500
281#define PLATFORM_BPA 0x1000
282
283/* Compatibility with drivers coming from PPC32 world */
284#define _machine (systemcfg->platform)
285#define _MACH_Pmac PLATFORM_POWERMAC
286
287/*
288 * List of interrupt controllers.
289 */
290#define IC_INVALID 0
291#define IC_OPEN_PIC 1
292#define IC_PPC_XIC 2
293#define IC_BPA_IIC 3
294
295#define XGLUE(a,b) a##b
296#define GLUE(a,b) XGLUE(a,b)
297
298#ifdef __ASSEMBLY__
299
300#define _GLOBAL(name) \
301 .section ".text"; \
302 .align 2 ; \
303 .globl name; \
304 .globl GLUE(.,name); \
305 .section ".opd","aw"; \
306name: \
307 .quad GLUE(.,name); \
308 .quad .TOC.@tocbase; \
309 .quad 0; \
310 .previous; \
311 .type GLUE(.,name),@function; \
312GLUE(.,name):
313
314#define _KPROBE(name) \
315 .section ".kprobes.text","a"; \
316 .align 2 ; \
317 .globl name; \
318 .globl GLUE(.,name); \
319 .section ".opd","aw"; \
320name: \
321 .quad GLUE(.,name); \
322 .quad .TOC.@tocbase; \
323 .quad 0; \
324 .previous; \
325 .type GLUE(.,name),@function; \
326GLUE(.,name):
327
328#define _STATIC(name) \
329 .section ".text"; \
330 .align 2 ; \
331 .section ".opd","aw"; \
332name: \
333 .quad GLUE(.,name); \
334 .quad .TOC.@tocbase; \
335 .quad 0; \
336 .previous; \
337 .type GLUE(.,name),@function; \
338GLUE(.,name):
339
340#else /* __ASSEMBLY__ */
341
342/*
343 * Default implementation of macro that returns current
344 * instruction pointer ("program counter").
345 */
346#define current_text_addr() ({ __label__ _l; _l: &&_l;})
347
348/* Macros for setting and retrieving special purpose registers */
349
350#define mfmsr() ({unsigned long rval; \
351 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
352
353#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
354 : : "r" (v))
355#define mtmsrd(v) __mtmsrd((v), 0)
356
357#define mfspr(rn) ({unsigned long rval; \
358 asm volatile("mfspr %0," __stringify(rn) \
359 : "=r" (rval)); rval;})
360#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
361
362#define mftb() ({unsigned long rval; \
363 asm volatile("mftb %0" : "=r" (rval)); rval;})
364
365#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
366#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
367
368#define mfasr() ({unsigned long rval; \
369 asm volatile("mfasr %0" : "=r" (rval)); rval;})
370
371static inline void set_tb(unsigned int upper, unsigned int lower)
372{
373 mttbl(0);
374 mttbu(upper);
375 mttbl(lower);
376}
377
378#define __get_SP() ({unsigned long sp; \
379 asm volatile("mr %0,1": "=r" (sp)); sp;})
380
381#ifdef __KERNEL__
382
383extern int have_of;
384extern u64 ppc64_interrupt_controller;
385
386struct task_struct;
387void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
388void release_thread(struct task_struct *);
389
390/* Prepare to copy thread state - unlazy all lazy status */
391extern void prepare_to_copy(struct task_struct *tsk);
392
393/* Create a new kernel thread. */
394extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
395
396/* Lazy FPU handling on uni-processor */
397extern struct task_struct *last_task_used_math;
398extern struct task_struct *last_task_used_altivec;
399
400/* 64-bit user address space is 44-bits (16TB user VM) */
401#define TASK_SIZE_USER64 (0x0000100000000000UL)
402
403/*
404 * 32-bit user address space is 4GB - 1 page
405 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
406 */
407#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
408
409#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
410 TASK_SIZE_USER32 : TASK_SIZE_USER64)
411
412/* This decides where the kernel will search for a free chunk of vm
413 * space during mmap's.
414 */
415#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
416#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
417
418#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)||(ppcdebugset(PPCDBG_BINFMT_32ADDR))) ? \
419 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
420
421typedef struct {
422 unsigned long seg;
423} mm_segment_t;
424
425struct thread_struct {
426 unsigned long ksp; /* Kernel stack pointer */
427 unsigned long ksp_vsid;
428 struct pt_regs *regs; /* Pointer to saved register state */
429 mm_segment_t fs; /* for get_fs() validation */
430 double fpr[32]; /* Complete floating point set */
431 unsigned long fpscr; /* Floating point status (plus pad) */
432 unsigned long fpexc_mode; /* Floating-point exception mode */
433 unsigned long start_tb; /* Start purr when proc switched in */
434 unsigned long accum_tb; /* Total accumilated purr for process */
435 unsigned long vdso_base; /* base of the vDSO library */
436 unsigned long dabr; /* Data address breakpoint register */
437#ifdef CONFIG_ALTIVEC
438 /* Complete AltiVec register set */
439 vector128 vr[32] __attribute((aligned(16)));
440 /* AltiVec status */
441 vector128 vscr __attribute((aligned(16)));
442 unsigned long vrsave;
443 int used_vr; /* set if process has used altivec */
444#endif /* CONFIG_ALTIVEC */
445};
446
447#define ARCH_MIN_TASKALIGN 16
448
449#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
450
451#define INIT_THREAD { \
452 .ksp = INIT_SP, \
453 .regs = (struct pt_regs *)INIT_SP - 1, \
454 .fs = KERNEL_DS, \
455 .fpr = {0}, \
456 .fpscr = 0, \
457 .fpexc_mode = MSR_FE0|MSR_FE1, \
458}
459
460/*
461 * Return saved PC of a blocked thread. For now, this is the "user" PC
462 */
463#define thread_saved_pc(tsk) \
464 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
465
466unsigned long get_wchan(struct task_struct *p);
467
468#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
469#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
470
471/* Get/set floating-point exception mode */
472#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
473#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
474
475extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
476extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
477
478static inline unsigned int __unpack_fe01(unsigned long msr_bits)
479{
480 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
481}
482
483static inline unsigned long __pack_fe01(unsigned int fpmode)
484{
485 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
486}
487
488#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
489
490/*
491 * Prefetch macros.
492 */
493#define ARCH_HAS_PREFETCH
494#define ARCH_HAS_PREFETCHW
495#define ARCH_HAS_SPINLOCK_PREFETCH
496
497static inline void prefetch(const void *x)
498{
499 if (unlikely(!x))
500 return;
501
502 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
503}
504
505static inline void prefetchw(const void *x)
506{
507 if (unlikely(!x))
508 return;
509
510 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
511}
512
513#define spin_lock_prefetch(x) prefetchw(x)
514
515#define HAVE_ARCH_PICK_MMAP_LAYOUT
516
517static inline void ppc64_runlatch_on(void)
518{
519 unsigned long ctrl;
520
521 if (cpu_has_feature(CPU_FTR_CTRL)) {
522 ctrl = mfspr(SPRN_CTRLF);
523 ctrl |= CTRL_RUNLATCH;
524 mtspr(SPRN_CTRLT, ctrl);
525 }
526}
527
528static inline void ppc64_runlatch_off(void)
529{
530 unsigned long ctrl;
531
532 if (cpu_has_feature(CPU_FTR_CTRL)) {
533 ctrl = mfspr(SPRN_CTRLF);
534 ctrl &= ~CTRL_RUNLATCH;
535 mtspr(SPRN_CTRLT, ctrl);
536 }
537}
538
539#endif /* __KERNEL__ */
540
541#endif /* __ASSEMBLY__ */
542
543#ifdef __KERNEL__
544#define RUNLATCH_ON(REG) \
545BEGIN_FTR_SECTION \
546 mfspr (REG),SPRN_CTRLF; \
547 ori (REG),(REG),CTRL_RUNLATCH; \
548 mtspr SPRN_CTRLT,(REG); \
549END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
550#endif
551
552/*
553 * Number of entries in the SLB. If this ever changes we should handle
554 * it with a use a cpu feature fixup.
555 */
556#define SLB_NUM_ENTRIES 64
557
558#endif /* __ASM_PPC64_PROCESSOR_H */
diff --git a/include/asm-ppc64/prom.h b/include/asm-ppc64/prom.h
index c02ec1d6b909..cf0284e081ea 100644
--- a/include/asm-ppc64/prom.h
+++ b/include/asm-ppc64/prom.h
@@ -137,6 +137,9 @@ struct device_node {
137 struct kref kref; 137 struct kref kref;
138 unsigned long _flags; 138 unsigned long _flags;
139 void *data; 139 void *data;
140#ifdef CONFIG_PPC_ISERIES
141 struct list_head Device_List;
142#endif
140}; 143};
141 144
142extern struct device_node *of_chosen; 145extern struct device_node *of_chosen;
diff --git a/include/asm-ppc64/rwsem.h b/include/asm-ppc64/rwsem.h
deleted file mode 100644
index bd5c2f093575..000000000000
--- a/include/asm-ppc64/rwsem.h
+++ /dev/null
@@ -1,167 +0,0 @@
1/*
2 * include/asm-ppc64/rwsem.h: R/W semaphores for PPC using the stuff
3 * in lib/rwsem.c. Adapted largely from include/asm-i386/rwsem.h
4 * by Paul Mackerras <paulus@samba.org>.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef _PPC64_RWSEM_H
13#define _PPC64_RWSEM_H
14
15#ifdef __KERNEL__
16#include <linux/list.h>
17#include <linux/spinlock.h>
18#include <asm/atomic.h>
19#include <asm/system.h>
20
21/*
22 * the semaphore definition
23 */
24struct rw_semaphore {
25 /* XXX this should be able to be an atomic_t -- paulus */
26 signed int count;
27#define RWSEM_UNLOCKED_VALUE 0x00000000
28#define RWSEM_ACTIVE_BIAS 0x00000001
29#define RWSEM_ACTIVE_MASK 0x0000ffff
30#define RWSEM_WAITING_BIAS (-0x00010000)
31#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
32#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
33 spinlock_t wait_lock;
34 struct list_head wait_list;
35#if RWSEM_DEBUG
36 int debug;
37#endif
38};
39
40/*
41 * initialisation
42 */
43#if RWSEM_DEBUG
44#define __RWSEM_DEBUG_INIT , 0
45#else
46#define __RWSEM_DEBUG_INIT /* */
47#endif
48
49#define __RWSEM_INITIALIZER(name) \
50 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
51 LIST_HEAD_INIT((name).wait_list) \
52 __RWSEM_DEBUG_INIT }
53
54#define DECLARE_RWSEM(name) \
55 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
56
57extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
58extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
59extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
60extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
61
62static inline void init_rwsem(struct rw_semaphore *sem)
63{
64 sem->count = RWSEM_UNLOCKED_VALUE;
65 spin_lock_init(&sem->wait_lock);
66 INIT_LIST_HEAD(&sem->wait_list);
67#if RWSEM_DEBUG
68 sem->debug = 0;
69#endif
70}
71
72/*
73 * lock for reading
74 */
75static inline void __down_read(struct rw_semaphore *sem)
76{
77 if (unlikely(atomic_inc_return((atomic_t *)(&sem->count)) <= 0))
78 rwsem_down_read_failed(sem);
79}
80
81static inline int __down_read_trylock(struct rw_semaphore *sem)
82{
83 int tmp;
84
85 while ((tmp = sem->count) >= 0) {
86 if (tmp == cmpxchg(&sem->count, tmp,
87 tmp + RWSEM_ACTIVE_READ_BIAS)) {
88 return 1;
89 }
90 }
91 return 0;
92}
93
94/*
95 * lock for writing
96 */
97static inline void __down_write(struct rw_semaphore *sem)
98{
99 int tmp;
100
101 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
102 (atomic_t *)(&sem->count));
103 if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
104 rwsem_down_write_failed(sem);
105}
106
107static inline int __down_write_trylock(struct rw_semaphore *sem)
108{
109 int tmp;
110
111 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
112 RWSEM_ACTIVE_WRITE_BIAS);
113 return tmp == RWSEM_UNLOCKED_VALUE;
114}
115
116/*
117 * unlock after reading
118 */
119static inline void __up_read(struct rw_semaphore *sem)
120{
121 int tmp;
122
123 tmp = atomic_dec_return((atomic_t *)(&sem->count));
124 if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
125 rwsem_wake(sem);
126}
127
128/*
129 * unlock after writing
130 */
131static inline void __up_write(struct rw_semaphore *sem)
132{
133 if (unlikely(atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
134 (atomic_t *)(&sem->count)) < 0))
135 rwsem_wake(sem);
136}
137
138/*
139 * implement atomic add functionality
140 */
141static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
142{
143 atomic_add(delta, (atomic_t *)(&sem->count));
144}
145
146/*
147 * downgrade write lock to read lock
148 */
149static inline void __downgrade_write(struct rw_semaphore *sem)
150{
151 int tmp;
152
153 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
154 if (tmp < 0)
155 rwsem_downgrade_wake(sem);
156}
157
158/*
159 * implement exchange and add functionality
160 */
161static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
162{
163 return atomic_add_return(delta, (atomic_t *)(&sem->count));
164}
165
166#endif /* __KERNEL__ */
167#endif /* _PPC_RWSEM_XADD_H */
diff --git a/include/asm-ppc64/seccomp.h b/include/asm-ppc64/seccomp.h
deleted file mode 100644
index c130c334bda1..000000000000
--- a/include/asm-ppc64/seccomp.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef _ASM_SECCOMP_H
2
3#include <linux/thread_info.h> /* already defines TIF_32BIT */
4
5#ifndef TIF_32BIT
6#error "unexpected TIF_32BIT on ppc64"
7#endif
8
9#include <linux/unistd.h>
10
11#define __NR_seccomp_read __NR_read
12#define __NR_seccomp_write __NR_write
13#define __NR_seccomp_exit __NR_exit
14#define __NR_seccomp_sigreturn __NR_rt_sigreturn
15
16#define __NR_seccomp_read_32 __NR_read
17#define __NR_seccomp_write_32 __NR_write
18#define __NR_seccomp_exit_32 __NR_exit
19#define __NR_seccomp_sigreturn_32 __NR_sigreturn
20
21#endif /* _ASM_SECCOMP_H */
diff --git a/include/asm-ppc64/sections.h b/include/asm-ppc64/sections.h
deleted file mode 100644
index 308ca6f5ced2..000000000000
--- a/include/asm-ppc64/sections.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifndef _PPC64_SECTIONS_H
2#define _PPC64_SECTIONS_H
3
4extern char _end[];
5
6#include <asm-generic/sections.h>
7
8#define __pmac
9#define __pmacdata
10
11#define __prep
12#define __prepdata
13
14#define __chrp
15#define __chrpdata
16
17#define __openfirmware
18#define __openfirmwaredata
19
20
21static inline int in_kernel_text(unsigned long addr)
22{
23 if (addr >= (unsigned long)_stext && addr < (unsigned long)__init_end)
24 return 1;
25
26 return 0;
27}
28
29#endif
diff --git a/include/asm-ppc64/semaphore.h b/include/asm-ppc64/semaphore.h
deleted file mode 100644
index aefe7753ea41..000000000000
--- a/include/asm-ppc64/semaphore.h
+++ /dev/null
@@ -1,98 +0,0 @@
1#ifndef _PPC64_SEMAPHORE_H
2#define _PPC64_SEMAPHORE_H
3
4/*
5 * Remove spinlock-based RW semaphores; RW semaphore definitions are
6 * now in rwsem.h and we use the generic lib/rwsem.c implementation.
7 * Rework semaphores to use atomic_dec_if_positive.
8 * -- Paul Mackerras (paulus@samba.org)
9 */
10
11#ifdef __KERNEL__
12
13#include <asm/atomic.h>
14#include <asm/system.h>
15#include <linux/wait.h>
16#include <linux/rwsem.h>
17
18struct semaphore {
19 /*
20 * Note that any negative value of count is equivalent to 0,
21 * but additionally indicates that some process(es) might be
22 * sleeping on `wait'.
23 */
24 atomic_t count;
25 wait_queue_head_t wait;
26};
27
28#define __SEMAPHORE_INITIALIZER(name, n) \
29{ \
30 .count = ATOMIC_INIT(n), \
31 .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
32}
33
34#define __MUTEX_INITIALIZER(name) \
35 __SEMAPHORE_INITIALIZER(name, 1)
36
37#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
38 struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
39
40#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1)
41#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0)
42
43static inline void sema_init (struct semaphore *sem, int val)
44{
45 atomic_set(&sem->count, val);
46 init_waitqueue_head(&sem->wait);
47}
48
49static inline void init_MUTEX (struct semaphore *sem)
50{
51 sema_init(sem, 1);
52}
53
54static inline void init_MUTEX_LOCKED (struct semaphore *sem)
55{
56 sema_init(sem, 0);
57}
58
59extern void __down(struct semaphore * sem);
60extern int __down_interruptible(struct semaphore * sem);
61extern void __up(struct semaphore * sem);
62
63static inline void down(struct semaphore * sem)
64{
65 might_sleep();
66
67 /*
68 * Try to get the semaphore, take the slow path if we fail.
69 */
70 if (unlikely(atomic_dec_return(&sem->count) < 0))
71 __down(sem);
72}
73
74static inline int down_interruptible(struct semaphore * sem)
75{
76 int ret = 0;
77
78 might_sleep();
79
80 if (unlikely(atomic_dec_return(&sem->count) < 0))
81 ret = __down_interruptible(sem);
82 return ret;
83}
84
85static inline int down_trylock(struct semaphore * sem)
86{
87 return atomic_dec_if_positive(&sem->count) < 0;
88}
89
90static inline void up(struct semaphore * sem)
91{
92 if (unlikely(atomic_inc_return(&sem->count) <= 0))
93 __up(sem);
94}
95
96#endif /* __KERNEL__ */
97
98#endif /* !(_PPC64_SEMAPHORE_H) */
diff --git a/include/asm-ppc64/spinlock_types.h b/include/asm-ppc64/spinlock_types.h
deleted file mode 100644
index a37c8eabb9f2..000000000000
--- a/include/asm-ppc64/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
1#ifndef __ASM_SPINLOCK_TYPES_H
2#define __ASM_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned int slock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile signed int lock;
16} raw_rwlock_t;
17
18#define __RAW_RW_LOCK_UNLOCKED { 0 }
19
20#endif
diff --git a/include/asm-ppc64/statfs.h b/include/asm-ppc64/statfs.h
deleted file mode 100644
index 3c985e5246a7..000000000000
--- a/include/asm-ppc64/statfs.h
+++ /dev/null
@@ -1,61 +0,0 @@
1#ifndef _PPC64_STATFS_H
2#define _PPC64_STATFS_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#ifndef __KERNEL_STRICT_NAMES
12#include <linux/types.h>
13typedef __kernel_fsid_t fsid_t;
14#endif
15
16/*
17 * We're already 64-bit, so duplicate the definition
18 */
19struct statfs {
20 long f_type;
21 long f_bsize;
22 long f_blocks;
23 long f_bfree;
24 long f_bavail;
25 long f_files;
26 long f_ffree;
27 __kernel_fsid_t f_fsid;
28 long f_namelen;
29 long f_frsize;
30 long f_spare[5];
31};
32
33struct statfs64 {
34 long f_type;
35 long f_bsize;
36 long f_blocks;
37 long f_bfree;
38 long f_bavail;
39 long f_files;
40 long f_ffree;
41 __kernel_fsid_t f_fsid;
42 long f_namelen;
43 long f_frsize;
44 long f_spare[5];
45};
46
47struct compat_statfs64 {
48 __u32 f_type;
49 __u32 f_bsize;
50 __u64 f_blocks;
51 __u64 f_bfree;
52 __u64 f_bavail;
53 __u64 f_files;
54 __u64 f_ffree;
55 __kernel_fsid_t f_fsid;
56 __u32 f_namelen;
57 __u32 f_frsize;
58 __u32 f_spare[5];
59};
60
61#endif /* _PPC64_STATFS_H */
diff --git a/include/asm-ppc64/system.h b/include/asm-ppc64/system.h
index 375015c62f20..d1e00933354c 100644
--- a/include/asm-ppc64/system.h
+++ b/include/asm-ppc64/system.h
@@ -13,7 +13,7 @@
13#include <asm/page.h> 13#include <asm/page.h>
14#include <asm/processor.h> 14#include <asm/processor.h>
15#include <asm/hw_irq.h> 15#include <asm/hw_irq.h>
16#include <asm/memory.h> 16#include <asm/synch.h>
17 17
18/* 18/*
19 * Memory barrier. 19 * Memory barrier.
@@ -48,7 +48,7 @@
48#ifdef CONFIG_SMP 48#ifdef CONFIG_SMP
49#define smp_mb() mb() 49#define smp_mb() mb()
50#define smp_rmb() rmb() 50#define smp_rmb() rmb()
51#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory") 51#define smp_wmb() eieio()
52#define smp_read_barrier_depends() read_barrier_depends() 52#define smp_read_barrier_depends() read_barrier_depends()
53#else 53#else
54#define smp_mb() __asm__ __volatile__("": : :"memory") 54#define smp_mb() __asm__ __volatile__("": : :"memory")
@@ -131,6 +131,10 @@ static inline void flush_altivec_to_thread(struct task_struct *t)
131} 131}
132#endif 132#endif
133 133
134static inline void flush_spe_to_thread(struct task_struct *t)
135{
136}
137
134extern int mem_init_done; /* set on boot once kmalloc can be called */ 138extern int mem_init_done; /* set on boot once kmalloc can be called */
135 139
136/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */ 140/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
@@ -144,13 +148,6 @@ struct thread_struct;
144extern struct task_struct * _switch(struct thread_struct *prev, 148extern struct task_struct * _switch(struct thread_struct *prev,
145 struct thread_struct *next); 149 struct thread_struct *next);
146 150
147static inline int __is_processor(unsigned long pv)
148{
149 unsigned long pvr;
150 asm("mfspr %0, 0x11F" : "=r" (pvr));
151 return(PVR_VER(pvr) == pv);
152}
153
154/* 151/*
155 * Atomic exchange 152 * Atomic exchange
156 * 153 *
diff --git a/include/asm-ppc64/tce.h b/include/asm-ppc64/tce.h
new file mode 100644
index 000000000000..d40b6b42ab35
--- /dev/null
+++ b/include/asm-ppc64/tce.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 * Rewrite, cleanup:
4 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_TCE_H
22#define _ASM_TCE_H
23
24/*
25 * Tces come in two formats, one for the virtual bus and a different
26 * format for PCI
27 */
28#define TCE_VB 0
29#define TCE_PCI 1
30
31/* TCE page size is 4096 bytes (1 << 12) */
32
33#define TCE_SHIFT 12
34#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
35#define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
36
37
38/* tce_entry
39 * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
40 * abstracted so layout is irrelevant.
41 */
42union tce_entry {
43 unsigned long te_word;
44 struct {
45 unsigned int tb_cacheBits :6; /* Cache hash bits - not used */
46 unsigned int tb_rsvd :6;
47 unsigned long tb_rpn :40; /* Real page number */
48 unsigned int tb_valid :1; /* Tce is valid (vb only) */
49 unsigned int tb_allio :1; /* Tce is valid for all lps (vb only) */
50 unsigned int tb_lpindex :8; /* LpIndex for user of TCE (vb only) */
51 unsigned int tb_pciwr :1; /* Write allowed (pci only) */
52 unsigned int tb_rdwr :1; /* Read allowed (pci), Write allowed (vb) */
53 } te_bits;
54#define te_cacheBits te_bits.tb_cacheBits
55#define te_rpn te_bits.tb_rpn
56#define te_valid te_bits.tb_valid
57#define te_allio te_bits.tb_allio
58#define te_lpindex te_bits.tb_lpindex
59#define te_pciwr te_bits.tb_pciwr
60#define te_rdwr te_bits.tb_rdwr
61};
62
63
64#endif
diff --git a/include/asm-ppc64/thread_info.h b/include/asm-ppc64/thread_info.h
index 0494df6fca74..71244d8a427d 100644
--- a/include/asm-ppc64/thread_info.h
+++ b/include/asm-ppc64/thread_info.h
@@ -54,9 +54,9 @@ struct thread_info {
54 54
55/* thread information allocation */ 55/* thread information allocation */
56 56
57#define THREAD_ORDER 2 57#define THREAD_SHIFT 14
58#define THREAD_SIZE (PAGE_SIZE << THREAD_ORDER) 58#define THREAD_ORDER (THREAD_SHIFT - PAGE_SHIFT)
59#define THREAD_SHIFT (PAGE_SHIFT + THREAD_ORDER) 59#define THREAD_SIZE (1 << THREAD_SHIFT)
60#ifdef CONFIG_DEBUG_STACK_USAGE 60#ifdef CONFIG_DEBUG_STACK_USAGE
61#define alloc_thread_info(tsk) \ 61#define alloc_thread_info(tsk) \
62 ({ \ 62 ({ \
diff --git a/include/asm-ppc64/tlbflush.h b/include/asm-ppc64/tlbflush.h
index 74271d7c1d16..626f505c6ee3 100644
--- a/include/asm-ppc64/tlbflush.h
+++ b/include/asm-ppc64/tlbflush.h
@@ -20,10 +20,8 @@
20struct mm_struct; 20struct mm_struct;
21struct ppc64_tlb_batch { 21struct ppc64_tlb_batch {
22 unsigned long index; 22 unsigned long index;
23 unsigned long context;
24 struct mm_struct *mm; 23 struct mm_struct *mm;
25 pte_t pte[PPC64_TLB_BATCH_NR]; 24 pte_t pte[PPC64_TLB_BATCH_NR];
26 unsigned long addr[PPC64_TLB_BATCH_NR];
27 unsigned long vaddr[PPC64_TLB_BATCH_NR]; 25 unsigned long vaddr[PPC64_TLB_BATCH_NR];
28 unsigned int large; 26 unsigned int large;
29}; 27};
@@ -48,8 +46,7 @@ static inline void flush_tlb_pending(void)
48#define flush_tlb_kernel_range(start, end) flush_tlb_pending() 46#define flush_tlb_kernel_range(start, end) flush_tlb_pending()
49#define flush_tlb_pgtables(mm, start, end) do { } while (0) 47#define flush_tlb_pgtables(mm, start, end) do { } while (0)
50 48
51extern void flush_hash_page(unsigned long context, unsigned long ea, pte_t pte, 49extern void flush_hash_page(unsigned long va, pte_t pte, int local);
52 int local); 50void flush_hash_range(unsigned long number, int local);
53void flush_hash_range(unsigned long context, unsigned long number, int local);
54 51
55#endif /* _PPC64_TLBFLUSH_H */ 52#endif /* _PPC64_TLBFLUSH_H */
diff --git a/include/asm-ppc64/unistd.h b/include/asm-ppc64/unistd.h
deleted file mode 100644
index 977bc980c1af..000000000000
--- a/include/asm-ppc64/unistd.h
+++ /dev/null
@@ -1,487 +0,0 @@
1#ifndef _ASM_PPC_UNISTD_H_
2#define _ASM_PPC_UNISTD_H_
3
4/*
5 * This file contains the system call numbers.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#define __NR_restart_syscall 0
14#define __NR_exit 1
15#define __NR_fork 2
16#define __NR_read 3
17#define __NR_write 4
18#define __NR_open 5
19#define __NR_close 6
20#define __NR_waitpid 7
21#define __NR_creat 8
22#define __NR_link 9
23#define __NR_unlink 10
24#define __NR_execve 11
25#define __NR_chdir 12
26#define __NR_time 13
27#define __NR_mknod 14
28#define __NR_chmod 15
29#define __NR_lchown 16
30#define __NR_break 17
31#define __NR_oldstat 18
32#define __NR_lseek 19
33#define __NR_getpid 20
34#define __NR_mount 21
35#define __NR_umount 22
36#define __NR_setuid 23
37#define __NR_getuid 24
38#define __NR_stime 25
39#define __NR_ptrace 26
40#define __NR_alarm 27
41#define __NR_oldfstat 28
42#define __NR_pause 29
43#define __NR_utime 30
44#define __NR_stty 31
45#define __NR_gtty 32
46#define __NR_access 33
47#define __NR_nice 34
48#define __NR_ftime 35
49#define __NR_sync 36
50#define __NR_kill 37
51#define __NR_rename 38
52#define __NR_mkdir 39
53#define __NR_rmdir 40
54#define __NR_dup 41
55#define __NR_pipe 42
56#define __NR_times 43
57#define __NR_prof 44
58#define __NR_brk 45
59#define __NR_setgid 46
60#define __NR_getgid 47
61#define __NR_signal 48
62#define __NR_geteuid 49
63#define __NR_getegid 50
64#define __NR_acct 51
65#define __NR_umount2 52
66#define __NR_lock 53
67#define __NR_ioctl 54
68#define __NR_fcntl 55
69#define __NR_mpx 56
70#define __NR_setpgid 57
71#define __NR_ulimit 58
72#define __NR_oldolduname 59
73#define __NR_umask 60
74#define __NR_chroot 61
75#define __NR_ustat 62
76#define __NR_dup2 63
77#define __NR_getppid 64
78#define __NR_getpgrp 65
79#define __NR_setsid 66
80#define __NR_sigaction 67
81#define __NR_sgetmask 68
82#define __NR_ssetmask 69
83#define __NR_setreuid 70
84#define __NR_setregid 71
85#define __NR_sigsuspend 72
86#define __NR_sigpending 73
87#define __NR_sethostname 74
88#define __NR_setrlimit 75
89#define __NR_getrlimit 76
90#define __NR_getrusage 77
91#define __NR_gettimeofday 78
92#define __NR_settimeofday 79
93#define __NR_getgroups 80
94#define __NR_setgroups 81
95#define __NR_select 82
96#define __NR_symlink 83
97#define __NR_oldlstat 84
98#define __NR_readlink 85
99#define __NR_uselib 86
100#define __NR_swapon 87
101#define __NR_reboot 88
102#define __NR_readdir 89
103#define __NR_mmap 90
104#define __NR_munmap 91
105#define __NR_truncate 92
106#define __NR_ftruncate 93
107#define __NR_fchmod 94
108#define __NR_fchown 95
109#define __NR_getpriority 96
110#define __NR_setpriority 97
111#define __NR_profil 98
112#define __NR_statfs 99
113#define __NR_fstatfs 100
114#define __NR_ioperm 101
115#define __NR_socketcall 102
116#define __NR_syslog 103
117#define __NR_setitimer 104
118#define __NR_getitimer 105
119#define __NR_stat 106
120#define __NR_lstat 107
121#define __NR_fstat 108
122#define __NR_olduname 109
123#define __NR_iopl 110
124#define __NR_vhangup 111
125#define __NR_idle 112
126#define __NR_vm86 113
127#define __NR_wait4 114
128#define __NR_swapoff 115
129#define __NR_sysinfo 116
130#define __NR_ipc 117
131#define __NR_fsync 118
132#define __NR_sigreturn 119
133#define __NR_clone 120
134#define __NR_setdomainname 121
135#define __NR_uname 122
136#define __NR_modify_ldt 123
137#define __NR_adjtimex 124
138#define __NR_mprotect 125
139#define __NR_sigprocmask 126
140#define __NR_create_module 127
141#define __NR_init_module 128
142#define __NR_delete_module 129
143#define __NR_get_kernel_syms 130
144#define __NR_quotactl 131
145#define __NR_getpgid 132
146#define __NR_fchdir 133
147#define __NR_bdflush 134
148#define __NR_sysfs 135
149#define __NR_personality 136
150#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
151#define __NR_setfsuid 138
152#define __NR_setfsgid 139
153#define __NR__llseek 140
154#define __NR_getdents 141
155#define __NR__newselect 142
156#define __NR_flock 143
157#define __NR_msync 144
158#define __NR_readv 145
159#define __NR_writev 146
160#define __NR_getsid 147
161#define __NR_fdatasync 148
162#define __NR__sysctl 149
163#define __NR_mlock 150
164#define __NR_munlock 151
165#define __NR_mlockall 152
166#define __NR_munlockall 153
167#define __NR_sched_setparam 154
168#define __NR_sched_getparam 155
169#define __NR_sched_setscheduler 156
170#define __NR_sched_getscheduler 157
171#define __NR_sched_yield 158
172#define __NR_sched_get_priority_max 159
173#define __NR_sched_get_priority_min 160
174#define __NR_sched_rr_get_interval 161
175#define __NR_nanosleep 162
176#define __NR_mremap 163
177#define __NR_setresuid 164
178#define __NR_getresuid 165
179#define __NR_query_module 166
180#define __NR_poll 167
181#define __NR_nfsservctl 168
182#define __NR_setresgid 169
183#define __NR_getresgid 170
184#define __NR_prctl 171
185#define __NR_rt_sigreturn 172
186#define __NR_rt_sigaction 173
187#define __NR_rt_sigprocmask 174
188#define __NR_rt_sigpending 175
189#define __NR_rt_sigtimedwait 176
190#define __NR_rt_sigqueueinfo 177
191#define __NR_rt_sigsuspend 178
192#define __NR_pread64 179
193#define __NR_pwrite64 180
194#define __NR_chown 181
195#define __NR_getcwd 182
196#define __NR_capget 183
197#define __NR_capset 184
198#define __NR_sigaltstack 185
199#define __NR_sendfile 186
200#define __NR_getpmsg 187 /* some people actually want streams */
201#define __NR_putpmsg 188 /* some people actually want streams */
202#define __NR_vfork 189
203#define __NR_ugetrlimit 190 /* SuS compliant getrlimit */
204#define __NR_readahead 191
205/* #define __NR_mmap2 192 32bit only */
206/* #define __NR_truncate64 193 32bit only */
207/* #define __NR_ftruncate64 194 32bit only */
208/* #define __NR_stat64 195 32bit only */
209/* #define __NR_lstat64 196 32bit only */
210/* #define __NR_fstat64 197 32bit only */
211#define __NR_pciconfig_read 198
212#define __NR_pciconfig_write 199
213#define __NR_pciconfig_iobase 200
214#define __NR_multiplexer 201
215#define __NR_getdents64 202
216#define __NR_pivot_root 203
217/* #define __NR_fcntl64 204 32bit only */
218#define __NR_madvise 205
219#define __NR_mincore 206
220#define __NR_gettid 207
221#define __NR_tkill 208
222#define __NR_setxattr 209
223#define __NR_lsetxattr 210
224#define __NR_fsetxattr 211
225#define __NR_getxattr 212
226#define __NR_lgetxattr 213
227#define __NR_fgetxattr 214
228#define __NR_listxattr 215
229#define __NR_llistxattr 216
230#define __NR_flistxattr 217
231#define __NR_removexattr 218
232#define __NR_lremovexattr 219
233#define __NR_fremovexattr 220
234#define __NR_futex 221
235#define __NR_sched_setaffinity 222
236#define __NR_sched_getaffinity 223
237/* 224 currently unused */
238#define __NR_tuxcall 225
239/* #define __NR_sendfile64 226 32bit only */
240#define __NR_io_setup 227
241#define __NR_io_destroy 228
242#define __NR_io_getevents 229
243#define __NR_io_submit 230
244#define __NR_io_cancel 231
245#define __NR_set_tid_address 232
246#define __NR_fadvise64 233
247#define __NR_exit_group 234
248#define __NR_lookup_dcookie 235
249#define __NR_epoll_create 236
250#define __NR_epoll_ctl 237
251#define __NR_epoll_wait 238
252#define __NR_remap_file_pages 239
253#define __NR_timer_create 240
254#define __NR_timer_settime 241
255#define __NR_timer_gettime 242
256#define __NR_timer_getoverrun 243
257#define __NR_timer_delete 244
258#define __NR_clock_settime 245
259#define __NR_clock_gettime 246
260#define __NR_clock_getres 247
261#define __NR_clock_nanosleep 248
262#define __NR_swapcontext 249
263#define __NR_tgkill 250
264#define __NR_utimes 251
265#define __NR_statfs64 252
266#define __NR_fstatfs64 253
267/* #define __NR_fadvise64_64 254 32bit only */
268#define __NR_rtas 255
269/* Number 256 is reserved for sys_debug_setcontext */
270/* Number 257 is reserved for vserver */
271/* 258 currently unused */
272#define __NR_mbind 259
273#define __NR_get_mempolicy 260
274#define __NR_set_mempolicy 261
275#define __NR_mq_open 262
276#define __NR_mq_unlink 263
277#define __NR_mq_timedsend 264
278#define __NR_mq_timedreceive 265
279#define __NR_mq_notify 266
280#define __NR_mq_getsetattr 267
281#define __NR_kexec_load 268
282#define __NR_add_key 269
283#define __NR_request_key 270
284#define __NR_keyctl 271
285#define __NR_waitid 272
286#define __NR_ioprio_set 273
287#define __NR_ioprio_get 274
288#define __NR_inotify_init 275
289#define __NR_inotify_add_watch 276
290#define __NR_inotify_rm_watch 277
291
292#define __NR_syscalls 278
293#ifdef __KERNEL__
294#define NR_syscalls __NR_syscalls
295#endif
296
297#ifndef __ASSEMBLY__
298
299/* On powerpc a system call basically clobbers the same registers like a
300 * function call, with the exception of LR (which is needed for the
301 * "sc; bnslr" sequence) and CR (where only CR0.SO is clobbered to signal
302 * an error return status).
303 */
304
305#define __syscall_nr(nr, type, name, args...) \
306 unsigned long __sc_ret, __sc_err; \
307 { \
308 register unsigned long __sc_0 __asm__ ("r0"); \
309 register unsigned long __sc_3 __asm__ ("r3"); \
310 register unsigned long __sc_4 __asm__ ("r4"); \
311 register unsigned long __sc_5 __asm__ ("r5"); \
312 register unsigned long __sc_6 __asm__ ("r6"); \
313 register unsigned long __sc_7 __asm__ ("r7"); \
314 register unsigned long __sc_8 __asm__ ("r8"); \
315 \
316 __sc_loadargs_##nr(name, args); \
317 __asm__ __volatile__ \
318 ("sc \n\t" \
319 "mfcr %0 " \
320 : "=&r" (__sc_0), \
321 "=&r" (__sc_3), "=&r" (__sc_4), \
322 "=&r" (__sc_5), "=&r" (__sc_6), \
323 "=&r" (__sc_7), "=&r" (__sc_8) \
324 : __sc_asm_input_##nr \
325 : "cr0", "ctr", "memory", \
326 "r9", "r10","r11", "r12"); \
327 __sc_ret = __sc_3; \
328 __sc_err = __sc_0; \
329 } \
330 if (__sc_err & 0x10000000) \
331 { \
332 errno = __sc_ret; \
333 __sc_ret = -1; \
334 } \
335 return (type) __sc_ret
336
337#define __sc_loadargs_0(name, dummy...) \
338 __sc_0 = __NR_##name
339#define __sc_loadargs_1(name, arg1) \
340 __sc_loadargs_0(name); \
341 __sc_3 = (unsigned long) (arg1)
342#define __sc_loadargs_2(name, arg1, arg2) \
343 __sc_loadargs_1(name, arg1); \
344 __sc_4 = (unsigned long) (arg2)
345#define __sc_loadargs_3(name, arg1, arg2, arg3) \
346 __sc_loadargs_2(name, arg1, arg2); \
347 __sc_5 = (unsigned long) (arg3)
348#define __sc_loadargs_4(name, arg1, arg2, arg3, arg4) \
349 __sc_loadargs_3(name, arg1, arg2, arg3); \
350 __sc_6 = (unsigned long) (arg4)
351#define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5) \
352 __sc_loadargs_4(name, arg1, arg2, arg3, arg4); \
353 __sc_7 = (unsigned long) (arg5)
354#define __sc_loadargs_6(name, arg1, arg2, arg3, arg4, arg5, arg6) \
355 __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5); \
356 __sc_8 = (unsigned long) (arg6)
357
358#define __sc_asm_input_0 "0" (__sc_0)
359#define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3)
360#define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4)
361#define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5)
362#define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6)
363#define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7)
364#define __sc_asm_input_6 __sc_asm_input_5, "6" (__sc_8)
365
366#define _syscall0(type,name) \
367type name(void) \
368{ \
369 __syscall_nr(0, type, name); \
370}
371
372#define _syscall1(type,name,type1,arg1) \
373type name(type1 arg1) \
374{ \
375 __syscall_nr(1, type, name, arg1); \
376}
377
378#define _syscall2(type,name,type1,arg1,type2,arg2) \
379type name(type1 arg1, type2 arg2) \
380{ \
381 __syscall_nr(2, type, name, arg1, arg2); \
382}
383
384#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
385type name(type1 arg1, type2 arg2, type3 arg3) \
386{ \
387 __syscall_nr(3, type, name, arg1, arg2, arg3); \
388}
389
390#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
391type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
392{ \
393 __syscall_nr(4, type, name, arg1, arg2, arg3, arg4); \
394}
395
396#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
397type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \
398{ \
399 __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5); \
400}
401#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \
402type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \
403{ \
404 __syscall_nr(6, type, name, arg1, arg2, arg3, arg4, arg5, arg6); \
405}
406
407#ifdef __KERNEL_SYSCALLS__
408
409/*
410 * Forking from kernel space will result in the child getting a new,
411 * empty kernel stack area. Thus the child cannot access automatic
412 * variables set in the parent unless they are in registers, and the
413 * procedure where the fork was done cannot return to its caller in
414 * the child.
415 */
416
417/*
418 * System call prototypes.
419 */
420static inline _syscall3(int, execve, __const__ char *, file, char **, argv,
421 char **,envp)
422
423#endif /* __KERNEL_SYSCALLS__ */
424
425#ifdef __KERNEL__
426
427#include <linux/types.h>
428#include <linux/compiler.h>
429#include <linux/linkage.h>
430
431#define __ARCH_WANT_IPC_PARSE_VERSION
432#define __ARCH_WANT_OLD_READDIR
433#define __ARCH_WANT_STAT64
434#define __ARCH_WANT_SYS_ALARM
435#define __ARCH_WANT_SYS_GETHOSTNAME
436#define __ARCH_WANT_SYS_PAUSE
437#define __ARCH_WANT_SYS_SGETMASK
438#define __ARCH_WANT_SYS_SIGNAL
439#define __ARCH_WANT_SYS_TIME
440#define __ARCH_WANT_COMPAT_SYS_TIME
441#define __ARCH_WANT_SYS_UTIME
442#define __ARCH_WANT_SYS_WAITPID
443#define __ARCH_WANT_SYS_SOCKETCALL
444#define __ARCH_WANT_SYS_FADVISE64
445#define __ARCH_WANT_SYS_GETPGRP
446#define __ARCH_WANT_SYS_LLSEEK
447#define __ARCH_WANT_SYS_NICE
448#define __ARCH_WANT_SYS_OLD_GETRLIMIT
449#define __ARCH_WANT_SYS_OLDUMOUNT
450#define __ARCH_WANT_SYS_SIGPENDING
451#define __ARCH_WANT_SYS_SIGPROCMASK
452#define __ARCH_WANT_SYS_RT_SIGACTION
453
454unsigned long sys_mmap(unsigned long addr, size_t len, unsigned long prot,
455 unsigned long flags, unsigned long fd, off_t offset);
456struct pt_regs;
457int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
458 unsigned long a3, unsigned long a4, unsigned long a5,
459 struct pt_regs *regs);
460int sys_clone(unsigned long clone_flags, unsigned long p2, unsigned long p3,
461 unsigned long p4, unsigned long p5, unsigned long p6,
462 struct pt_regs *regs);
463int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
464 unsigned long p4, unsigned long p5, unsigned long p6,
465 struct pt_regs *regs);
466int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
467 unsigned long p4, unsigned long p5, unsigned long p6,
468 struct pt_regs *regs);
469int sys_pipe(int __user *fildes);
470int sys_ptrace(long request, long pid, long addr, long data);
471struct sigaction;
472long sys_rt_sigaction(int sig, const struct sigaction __user *act,
473 struct sigaction __user *oact, size_t sigsetsize);
474
475/*
476 * "Conditional" syscalls
477 *
478 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
479 * but it doesn't work on all toolchains, so we just do it by hand
480 */
481#define cond_syscall(x) asm(".weak\t." #x "\n\t.set\t." #x ",.sys_ni_syscall")
482
483#endif /* __KERNEL__ */
484
485#endif /* __ASSEMBLY__ */
486
487#endif /* _ASM_PPC_UNISTD_H_ */
diff --git a/include/asm-ppc64/vga.h b/include/asm-ppc64/vga.h
deleted file mode 100644
index c09849743f45..000000000000
--- a/include/asm-ppc64/vga.h
+++ /dev/null
@@ -1,50 +0,0 @@
1/*
2 * Access to VGA videoram
3 *
4 * (c) 1998 Martin Mares <mj@ucw.cz>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef _LINUX_ASM_VGA_H_
13#define _LINUX_ASM_VGA_H_
14
15#include <asm/io.h>
16
17#include <linux/config.h>
18
19#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
20
21#define VT_BUF_HAVE_RW
22/*
23 * These are only needed for supporting VGA or MDA text mode, which use little
24 * endian byte ordering.
25 * In other cases, we can optimize by using native byte ordering and
26 * <linux/vt_buffer.h> has already done the right job for us.
27 */
28
29static inline void scr_writew(u16 val, volatile u16 *addr)
30{
31 st_le16(addr, val);
32}
33
34static inline u16 scr_readw(volatile const u16 *addr)
35{
36 return ld_le16(addr);
37}
38
39#define VT_BUF_HAVE_MEMCPYW
40#define scr_memcpyw memcpy
41
42#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
43
44extern unsigned long vgacon_remap_base;
45#define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0))
46
47#define vga_readb(x) (*(x))
48#define vga_writeb(x,y) (*(y) = (x))
49
50#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-30 12:50:20 -0500