diff options
Diffstat (limited to 'include/asm-ppc/reg_booke.h')
| -rw-r--r-- | include/asm-ppc/reg_booke.h | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/include/asm-ppc/reg_booke.h b/include/asm-ppc/reg_booke.h index 45c5e6f2b7ab..00ad9c754c78 100644 --- a/include/asm-ppc/reg_booke.h +++ b/include/asm-ppc/reg_booke.h | |||
| @@ -165,6 +165,8 @@ do { \ | |||
| 165 | #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ | 165 | #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ |
| 166 | #define SPRN_MCSR 0x23C /* Machine Check Status Register */ | 166 | #define SPRN_MCSR 0x23C /* Machine Check Status Register */ |
| 167 | #define SPRN_MCAR 0x23D /* Machine Check Address Register */ | 167 | #define SPRN_MCAR 0x23D /* Machine Check Address Register */ |
| 168 | #define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ | ||
| 169 | #define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ | ||
| 168 | #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ | 170 | #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ |
| 169 | #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ | 171 | #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ |
| 170 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ | 172 | #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ |
| @@ -264,6 +266,17 @@ do { \ | |||
| 264 | #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ | 266 | #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */ |
| 265 | #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ | 267 | #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */ |
| 266 | #endif | 268 | #endif |
| 269 | #ifdef CONFIG_E200 | ||
| 270 | #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */ | ||
| 271 | #define MCSR_CP_PERR 0x20000000UL /* Cache Push Parity Error */ | ||
| 272 | #define MCSR_CPERR 0x10000000UL /* Cache Parity Error */ | ||
| 273 | #define MCSR_EXCP_ERR 0x08000000UL /* ISI, ITLB, or Bus Error on 1st insn | ||
| 274 | fetch for an exception handler */ | ||
| 275 | #define MCSR_BUS_IRERR 0x00000010UL /* Read Bus Error on instruction fetch*/ | ||
| 276 | #define MCSR_BUS_DRERR 0x00000008UL /* Read Bus Error on data load */ | ||
| 277 | #define MCSR_BUS_WRERR 0x00000004UL /* Write Bus Error on buffered | ||
| 278 | store or cache line push */ | ||
| 279 | #endif | ||
| 267 | 280 | ||
| 268 | /* Bit definitions for the DBSR. */ | 281 | /* Bit definitions for the DBSR. */ |
| 269 | /* | 282 | /* |
| @@ -311,6 +324,7 @@ do { \ | |||
| 311 | #define ESR_ST 0x00800000 /* Store Operation */ | 324 | #define ESR_ST 0x00800000 /* Store Operation */ |
| 312 | #define ESR_DLK 0x00200000 /* Data Cache Locking */ | 325 | #define ESR_DLK 0x00200000 /* Data Cache Locking */ |
| 313 | #define ESR_ILK 0x00100000 /* Instr. Cache Locking */ | 326 | #define ESR_ILK 0x00100000 /* Instr. Cache Locking */ |
| 327 | #define ESR_PUO 0x00040000 /* Unimplemented Operation exception */ | ||
| 314 | #define ESR_BO 0x00020000 /* Byte Ordering */ | 328 | #define ESR_BO 0x00020000 /* Byte Ordering */ |
| 315 | 329 | ||
| 316 | /* Bit definitions related to the DBCR0. */ | 330 | /* Bit definitions related to the DBCR0. */ |
| @@ -387,10 +401,12 @@ do { \ | |||
| 387 | #define ICCR_CACHE 1 /* Cacheable */ | 401 | #define ICCR_CACHE 1 /* Cacheable */ |
| 388 | 402 | ||
| 389 | /* Bit definitions for L1CSR0. */ | 403 | /* Bit definitions for L1CSR0. */ |
| 404 | #define L1CSR0_CLFC 0x00000100 /* Cache Lock Bits Flash Clear */ | ||
| 390 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ | 405 | #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ |
| 406 | #define L1CSR0_CFI 0x00000002 /* Cache Flash Invalidate */ | ||
| 391 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ | 407 | #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ |
| 392 | 408 | ||
| 393 | /* Bit definitions for L1CSR0. */ | 409 | /* Bit definitions for L1CSR1. */ |
| 394 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ | 410 | #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */ |
| 395 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ | 411 | #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */ |
| 396 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ | 412 | #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */ |