diff options
Diffstat (limited to 'include/asm-ppc/pgtable.h')
-rw-r--r-- | include/asm-ppc/pgtable.h | 46 |
1 files changed, 0 insertions, 46 deletions
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 063ad91cbbcc..69347bdbb401 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h | |||
@@ -271,48 +271,6 @@ extern unsigned long ioremap_bot, ioremap_base; | |||
271 | /* ERPN in a PTE never gets cleared, ignore it */ | 271 | /* ERPN in a PTE never gets cleared, ignore it */ |
272 | #define _PTE_NONE_MASK 0xffffffff00000000ULL | 272 | #define _PTE_NONE_MASK 0xffffffff00000000ULL |
273 | 273 | ||
274 | #elif defined(CONFIG_FSL_BOOKE) | ||
275 | /* | ||
276 | MMU Assist Register 3: | ||
277 | |||
278 | 32 33 34 35 36 ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63 | ||
279 | RPN...................... 0 0 U0 U1 U2 U3 UX SX UW SW UR SR | ||
280 | |||
281 | - PRESENT *must* be in the bottom three bits because swap cache | ||
282 | entries use the top 29 bits. | ||
283 | |||
284 | - FILE *must* be in the bottom three bits because swap cache | ||
285 | entries use the top 29 bits. | ||
286 | */ | ||
287 | |||
288 | /* Definitions for FSL Book-E Cores */ | ||
289 | #define _PAGE_PRESENT 0x00001 /* S: PTE contains a translation */ | ||
290 | #define _PAGE_USER 0x00002 /* S: User page (maps to UR) */ | ||
291 | #define _PAGE_FILE 0x00002 /* S: when !present: nonlinear file mapping */ | ||
292 | #define _PAGE_ACCESSED 0x00004 /* S: Page referenced */ | ||
293 | #define _PAGE_HWWRITE 0x00008 /* H: Dirty & RW, set in exception */ | ||
294 | #define _PAGE_RW 0x00010 /* S: Write permission */ | ||
295 | #define _PAGE_HWEXEC 0x00020 /* H: UX permission */ | ||
296 | |||
297 | #define _PAGE_ENDIAN 0x00040 /* H: E bit */ | ||
298 | #define _PAGE_GUARDED 0x00080 /* H: G bit */ | ||
299 | #define _PAGE_COHERENT 0x00100 /* H: M bit */ | ||
300 | #define _PAGE_NO_CACHE 0x00200 /* H: I bit */ | ||
301 | #define _PAGE_WRITETHRU 0x00400 /* H: W bit */ | ||
302 | |||
303 | #ifdef CONFIG_PTE_64BIT | ||
304 | #define _PAGE_DIRTY 0x08000 /* S: Page dirty */ | ||
305 | |||
306 | /* ERPN in a PTE never gets cleared, ignore it */ | ||
307 | #define _PTE_NONE_MASK 0xffffffffffff0000ULL | ||
308 | #else | ||
309 | #define _PAGE_DIRTY 0x00800 /* S: Page dirty */ | ||
310 | #endif | ||
311 | |||
312 | #define _PMD_PRESENT 0 | ||
313 | #define _PMD_PRESENT_MASK (PAGE_MASK) | ||
314 | #define _PMD_BAD (~PAGE_MASK) | ||
315 | |||
316 | #elif defined(CONFIG_8xx) | 274 | #elif defined(CONFIG_8xx) |
317 | /* Definitions for 8xx embedded chips. */ | 275 | /* Definitions for 8xx embedded chips. */ |
318 | #define _PAGE_PRESENT 0x0001 /* Page is valid */ | 276 | #define _PAGE_PRESENT 0x0001 /* Page is valid */ |
@@ -484,11 +442,7 @@ extern unsigned long bad_call_to_PMD_PAGE_SIZE(void); | |||
484 | 442 | ||
485 | /* in some case we want to additionaly adjust where the pfn is in the pte to | 443 | /* in some case we want to additionaly adjust where the pfn is in the pte to |
486 | * allow room for more flags */ | 444 | * allow room for more flags */ |
487 | #if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT) | ||
488 | #define PFN_SHIFT_OFFSET (PAGE_SHIFT + 8) | ||
489 | #else | ||
490 | #define PFN_SHIFT_OFFSET (PAGE_SHIFT) | 445 | #define PFN_SHIFT_OFFSET (PAGE_SHIFT) |
491 | #endif | ||
492 | 446 | ||
493 | #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) | 447 | #define pte_pfn(x) (pte_val(x) >> PFN_SHIFT_OFFSET) |
494 | #define pte_page(x) pfn_to_page(pte_pfn(x)) | 448 | #define pte_page(x) pfn_to_page(pte_pfn(x)) |