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diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h
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1/*
2 * PowerPC memory management structures
3 */
4
5#ifdef __KERNEL__
6#ifndef _PPC_MMU_H_
7#define _PPC_MMU_H_
8
9
10#ifndef __ASSEMBLY__
11
12/*
13 * Define physical address type. Machines using split size
14 * virtual/physical addressing like 32-bit virtual / 36-bit
15 * physical need a larger than native word size type. -Matt
16 */
17#ifndef CONFIG_PHYS_64BIT
18#define PHYS_FMT "%.8lx"
19#else
20extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
21#define PHYS_FMT "%16Lx"
22#endif
23
24typedef struct {
25 unsigned long id;
26 unsigned long vdso_base;
27} mm_context_t;
28
29/* Hardware Page Table Entry */
30typedef struct _PTE {
31 unsigned long v:1; /* Entry is valid */
32 unsigned long vsid:24; /* Virtual segment identifier */
33 unsigned long h:1; /* Hash algorithm indicator */
34 unsigned long api:6; /* Abbreviated page index */
35 unsigned long rpn:20; /* Real (physical) page number */
36 unsigned long :3; /* Unused */
37 unsigned long r:1; /* Referenced */
38 unsigned long c:1; /* Changed */
39 unsigned long w:1; /* Write-thru cache mode */
40 unsigned long i:1; /* Cache inhibited */
41 unsigned long m:1; /* Memory coherence */
42 unsigned long g:1; /* Guarded */
43 unsigned long :1; /* Unused */
44 unsigned long pp:2; /* Page protection */
45} PTE;
46
47/* Values for PP (assumes Ks=0, Kp=1) */
48#define PP_RWXX 0 /* Supervisor read/write, User none */
49#define PP_RWRX 1 /* Supervisor read/write, User read */
50#define PP_RWRW 2 /* Supervisor read/write, User read/write */
51#define PP_RXRX 3 /* Supervisor read, User read */
52
53/* Segment Register */
54typedef struct _SEGREG {
55 unsigned long t:1; /* Normal or I/O type */
56 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
57 unsigned long kp:1; /* User 'key' (normally 1) */
58 unsigned long n:1; /* No-execute */
59 unsigned long :4; /* Unused */
60 unsigned long vsid:24; /* Virtual Segment Identifier */
61} SEGREG;
62
63/* Block Address Translation (BAT) Registers */
64typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
65 unsigned long bepi:15; /* Effective page index (virtual address) */
66 unsigned long :8; /* unused */
67 unsigned long w:1;
68 unsigned long i:1; /* Cache inhibit */
69 unsigned long m:1; /* Memory coherence */
70 unsigned long ks:1; /* Supervisor key (normally 0) */
71 unsigned long kp:1; /* User key (normally 1) */
72 unsigned long pp:2; /* Page access protections */
73} P601_BATU;
74
75typedef struct _BATU { /* Upper part of BAT (all except 601) */
76 unsigned long bepi:15; /* Effective page index (virtual address) */
77 unsigned long :4; /* Unused */
78 unsigned long bl:11; /* Block size mask */
79 unsigned long vs:1; /* Supervisor valid */
80 unsigned long vp:1; /* User valid */
81} BATU;
82
83typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
84 unsigned long brpn:15; /* Real page index (physical address) */
85 unsigned long :10; /* Unused */
86 unsigned long v:1; /* Valid bit */
87 unsigned long bl:6; /* Block size mask */
88} P601_BATL;
89
90typedef struct _BATL { /* Lower part of BAT (all except 601) */
91 unsigned long brpn:15; /* Real page index (physical address) */
92 unsigned long :10; /* Unused */
93 unsigned long w:1; /* Write-thru cache */
94 unsigned long i:1; /* Cache inhibit */
95 unsigned long m:1; /* Memory coherence */
96 unsigned long g:1; /* Guarded (MBZ in IBAT) */
97 unsigned long :1; /* Unused */
98 unsigned long pp:2; /* Page access protections */
99} BATL;
100
101typedef struct _BAT {
102 BATU batu; /* Upper register */
103 BATL batl; /* Lower register */
104} BAT;
105
106typedef struct _P601_BAT {
107 P601_BATU batu; /* Upper register */
108 P601_BATL batl; /* Lower register */
109} P601_BAT;
110
111#endif /* __ASSEMBLY__ */
112
113/* Block size masks */
114#define BL_128K 0x000
115#define BL_256K 0x001
116#define BL_512K 0x003
117#define BL_1M 0x007
118#define BL_2M 0x00F
119#define BL_4M 0x01F
120#define BL_8M 0x03F
121#define BL_16M 0x07F
122#define BL_32M 0x0FF
123#define BL_64M 0x1FF
124#define BL_128M 0x3FF
125#define BL_256M 0x7FF
126
127/* BAT Access Protection */
128#define BPP_XX 0x00 /* No access */
129#define BPP_RX 0x01 /* Read only */
130#define BPP_RW 0x02 /* Read/write */
131
132/* Control/status registers for the MPC8xx.
133 * A write operation to these registers causes serialized access.
134 * During software tablewalk, the registers used perform mask/shift-add
135 * operations when written/read. A TLB entry is created when the Mx_RPN
136 * is written, and the contents of several registers are used to
137 * create the entry.
138 */
139#define SPRN_MI_CTR 784 /* Instruction TLB control register */
140#define MI_GPM 0x80000000 /* Set domain manager mode */
141#define MI_PPM 0x40000000 /* Set subpage protection */
142#define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
143#define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
144#define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
145#define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
146#define MI_RESETVAL 0x00000000 /* Value of register at reset */
147
148/* These are the Ks and Kp from the PowerPC books. For proper operation,
149 * Ks = 0, Kp = 1.
150 */
151#define SPRN_MI_AP 786
152#define MI_Ks 0x80000000 /* Should not be set */
153#define MI_Kp 0x40000000 /* Should always be set */
154
155/* The effective page number register. When read, contains the information
156 * about the last instruction TLB miss. When MI_RPN is written, bits in
157 * this register are used to create the TLB entry.
158 */
159#define SPRN_MI_EPN 787
160#define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
161#define MI_EVALID 0x00000200 /* Entry is valid */
162#define MI_ASIDMASK 0x0000000f /* ASID match value */
163 /* Reset value is undefined */
164
165/* A "level 1" or "segment" or whatever you want to call it register.
166 * For the instruction TLB, it contains bits that get loaded into the
167 * TLB entry when the MI_RPN is written.
168 */
169#define SPRN_MI_TWC 789
170#define MI_APG 0x000001e0 /* Access protection group (0) */
171#define MI_GUARDED 0x00000010 /* Guarded storage */
172#define MI_PSMASK 0x0000000c /* Mask of page size bits */
173#define MI_PS8MEG 0x0000000c /* 8M page size */
174#define MI_PS512K 0x00000004 /* 512K page size */
175#define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
176#define MI_SVALID 0x00000001 /* Segment entry is valid */
177 /* Reset value is undefined */
178
179/* Real page number. Defined by the pte. Writing this register
180 * causes a TLB entry to be created for the instruction TLB, using
181 * additional information from the MI_EPN, and MI_TWC registers.
182 */
183#define SPRN_MI_RPN 790
184
185/* Define an RPN value for mapping kernel memory to large virtual
186 * pages for boot initialization. This has real page number of 0,
187 * large page size, shared page, cache enabled, and valid.
188 * Also mark all subpages valid and write access.
189 */
190#define MI_BOOTINIT 0x000001fd
191
192#define SPRN_MD_CTR 792 /* Data TLB control register */
193#define MD_GPM 0x80000000 /* Set domain manager mode */
194#define MD_PPM 0x40000000 /* Set subpage protection */
195#define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
196#define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
197#define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
198#define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
199#define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
200#define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
201#define MD_RESETVAL 0x04000000 /* Value of register at reset */
202
203#define SPRN_M_CASID 793 /* Address space ID (context) to match */
204#define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
205
206
207/* These are the Ks and Kp from the PowerPC books. For proper operation,
208 * Ks = 0, Kp = 1.
209 */
210#define SPRN_MD_AP 794
211#define MD_Ks 0x80000000 /* Should not be set */
212#define MD_Kp 0x40000000 /* Should always be set */
213
214/* The effective page number register. When read, contains the information
215 * about the last instruction TLB miss. When MD_RPN is written, bits in
216 * this register are used to create the TLB entry.
217 */
218#define SPRN_MD_EPN 795
219#define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
220#define MD_EVALID 0x00000200 /* Entry is valid */
221#define MD_ASIDMASK 0x0000000f /* ASID match value */
222 /* Reset value is undefined */
223
224/* The pointer to the base address of the first level page table.
225 * During a software tablewalk, reading this register provides the address
226 * of the entry associated with MD_EPN.
227 */
228#define SPRN_M_TWB 796
229#define M_L1TB 0xfffff000 /* Level 1 table base address */
230#define M_L1INDX 0x00000ffc /* Level 1 index, when read */
231 /* Reset value is undefined */
232
233/* A "level 1" or "segment" or whatever you want to call it register.
234 * For the data TLB, it contains bits that get loaded into the TLB entry
235 * when the MD_RPN is written. It is also provides the hardware assist
236 * for finding the PTE address during software tablewalk.
237 */
238#define SPRN_MD_TWC 797
239#define MD_L2TB 0xfffff000 /* Level 2 table base address */
240#define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
241#define MD_APG 0x000001e0 /* Access protection group (0) */
242#define MD_GUARDED 0x00000010 /* Guarded storage */
243#define MD_PSMASK 0x0000000c /* Mask of page size bits */
244#define MD_PS8MEG 0x0000000c /* 8M page size */
245#define MD_PS512K 0x00000004 /* 512K page size */
246#define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
247#define MD_WT 0x00000002 /* Use writethrough page attribute */
248#define MD_SVALID 0x00000001 /* Segment entry is valid */
249 /* Reset value is undefined */
250
251
252/* Real page number. Defined by the pte. Writing this register
253 * causes a TLB entry to be created for the data TLB, using
254 * additional information from the MD_EPN, and MD_TWC registers.
255 */
256#define SPRN_MD_RPN 798
257
258/* This is a temporary storage register that could be used to save
259 * a processor working register during a tablewalk.
260 */
261#define SPRN_M_TW 799
262
263/*
264 * At present, all PowerPC 400-class processors share a similar TLB
265 * architecture. The instruction and data sides share a unified,
266 * 64-entry, fully-associative TLB which is maintained totally under
267 * software control. In addition, the instruction side has a
268 * hardware-managed, 4-entry, fully- associative TLB which serves as a
269 * first level to the shared TLB. These two TLBs are known as the UTLB
270 * and ITLB, respectively.
271 */
272
273#define PPC4XX_TLB_SIZE 64
274
275/*
276 * TLB entries are defined by a "high" tag portion and a "low" data
277 * portion. On all architectures, the data portion is 32-bits.
278 *
279 * TLB entries are managed entirely under software control by reading,
280 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
281 * instructions.
282 */
283
284#define TLB_LO 1
285#define TLB_HI 0
286
287#define TLB_DATA TLB_LO
288#define TLB_TAG TLB_HI
289
290/* Tag portion */
291
292#define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
293#define TLB_PAGESZ_MASK 0x00000380
294#define TLB_PAGESZ(x) (((x) & 0x7) << 7)
295#define PAGESZ_1K 0
296#define PAGESZ_4K 1
297#define PAGESZ_16K 2
298#define PAGESZ_64K 3
299#define PAGESZ_256K 4
300#define PAGESZ_1M 5
301#define PAGESZ_4M 6
302#define PAGESZ_16M 7
303#define TLB_VALID 0x00000040 /* Entry is valid */
304
305/* Data portion */
306
307#define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
308#define TLB_PERM_MASK 0x00000300
309#define TLB_EX 0x00000200 /* Instruction execution allowed */
310#define TLB_WR 0x00000100 /* Writes permitted */
311#define TLB_ZSEL_MASK 0x000000F0
312#define TLB_ZSEL(x) (((x) & 0xF) << 4)
313#define TLB_ATTR_MASK 0x0000000F
314#define TLB_W 0x00000008 /* Caching is write-through */
315#define TLB_I 0x00000004 /* Caching is inhibited */
316#define TLB_M 0x00000002 /* Memory is coherent */
317#define TLB_G 0x00000001 /* Memory is guarded from prefetch */
318
319/*
320 * PPC440 support
321 */
322#define PPC44x_MMUCR_TID 0x000000ff
323#define PPC44x_MMUCR_STS 0x00010000
324
325#define PPC44x_TLB_PAGEID 0
326#define PPC44x_TLB_XLAT 1
327#define PPC44x_TLB_ATTRIB 2
328
329/* Page identification fields */
330#define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
331#define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
332#define PPC44x_TLB_TS 0x00000100 /* Translation address space */
333#define PPC44x_TLB_1K 0x00000000 /* Page sizes */
334#define PPC44x_TLB_4K 0x00000010
335#define PPC44x_TLB_16K 0x00000020
336#define PPC44x_TLB_64K 0x00000030
337#define PPC44x_TLB_256K 0x00000040
338#define PPC44x_TLB_1M 0x00000050
339#define PPC44x_TLB_16M 0x00000070
340#define PPC44x_TLB_256M 0x00000090
341
342/* Translation fields */
343#define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
344#define PPC44x_TLB_ERPN_MASK 0x0000000f
345
346/* Storage attribute and access control fields */
347#define PPC44x_TLB_ATTR_MASK 0x0000ff80
348#define PPC44x_TLB_U0 0x00008000 /* User 0 */
349#define PPC44x_TLB_U1 0x00004000 /* User 1 */
350#define PPC44x_TLB_U2 0x00002000 /* User 2 */
351#define PPC44x_TLB_U3 0x00001000 /* User 3 */
352#define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
353#define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
354#define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
355#define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
356#define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
357
358#define PPC44x_TLB_PERM_MASK 0x0000003f
359#define PPC44x_TLB_UX 0x00000020 /* User execution */
360#define PPC44x_TLB_UW 0x00000010 /* User write */
361#define PPC44x_TLB_UR 0x00000008 /* User read */
362#define PPC44x_TLB_SX 0x00000004 /* Super execution */
363#define PPC44x_TLB_SW 0x00000002 /* Super write */
364#define PPC44x_TLB_SR 0x00000001 /* Super read */
365
366/* Book-E defined page sizes */
367#define BOOKE_PAGESZ_1K 0
368#define BOOKE_PAGESZ_4K 1
369#define BOOKE_PAGESZ_16K 2
370#define BOOKE_PAGESZ_64K 3
371#define BOOKE_PAGESZ_256K 4
372#define BOOKE_PAGESZ_1M 5
373#define BOOKE_PAGESZ_4M 6
374#define BOOKE_PAGESZ_16M 7
375#define BOOKE_PAGESZ_64M 8
376#define BOOKE_PAGESZ_256M 9
377#define BOOKE_PAGESZ_1GB 10
378#define BOOKE_PAGESZ_4GB 11
379#define BOOKE_PAGESZ_16GB 12
380#define BOOKE_PAGESZ_64GB 13
381#define BOOKE_PAGESZ_256GB 14
382#define BOOKE_PAGESZ_1TB 15
383
384#ifndef CONFIG_SERIAL_TEXT_DEBUG
385#define PPC44x_EARLY_TLBS 1
386#else
387#define PPC44x_EARLY_TLBS 2
388#endif
389
390/*
391 * Freescale Book-E MMU support
392 */
393
394#define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
395#define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
396#define MAS0_NV(x) ((x) & 0x00000FFF)
397
398#define MAS1_VALID 0x80000000
399#define MAS1_IPROT 0x40000000
400#define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
401#define MAS1_TS 0x00001000
402#define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
403
404#define MAS2_EPN 0xFFFFF000
405#define MAS2_X0 0x00000040
406#define MAS2_X1 0x00000020
407#define MAS2_W 0x00000010
408#define MAS2_I 0x00000008
409#define MAS2_M 0x00000004
410#define MAS2_G 0x00000002
411#define MAS2_E 0x00000001
412
413#define MAS3_RPN 0xFFFFF000
414#define MAS3_U0 0x00000200
415#define MAS3_U1 0x00000100
416#define MAS3_U2 0x00000080
417#define MAS3_U3 0x00000040
418#define MAS3_UX 0x00000020
419#define MAS3_SX 0x00000010
420#define MAS3_UW 0x00000008
421#define MAS3_SW 0x00000004
422#define MAS3_UR 0x00000002
423#define MAS3_SR 0x00000001
424
425#define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
426#define MAS4_TIDDSEL 0x000F0000
427#define MAS4_TSIZED(x) MAS1_TSIZE(x)
428#define MAS4_X0D 0x00000040
429#define MAS4_X1D 0x00000020
430#define MAS4_WD 0x00000010
431#define MAS4_ID 0x00000008
432#define MAS4_MD 0x00000004
433#define MAS4_GD 0x00000002
434#define MAS4_ED 0x00000001
435
436#define MAS6_SPID0 0x3FFF0000
437#define MAS6_SPID1 0x00007FFE
438#define MAS6_SAS 0x00000001
439#define MAS6_SPID MAS6_SPID0
440
441#define MAS7_RPN 0xFFFFFFFF
442
443#endif /* _PPC_MMU_H_ */
444#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 08:11:38 -0500