diff options
Diffstat (limited to 'include/asm-ppc/ibm44x.h')
-rw-r--r-- | include/asm-ppc/ibm44x.h | 55 |
1 files changed, 42 insertions, 13 deletions
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h index 0c2ba03a1d49..f835066fb3ca 100644 --- a/include/asm-ppc/ibm44x.h +++ b/include/asm-ppc/ibm44x.h | |||
@@ -41,6 +41,9 @@ | |||
41 | #if defined(CONFIG_440SP) | 41 | #if defined(CONFIG_440SP) |
42 | #define UART0_PHYS_ERPN 1 | 42 | #define UART0_PHYS_ERPN 1 |
43 | #define UART0_PHYS_IO_BASE 0xf0000200 | 43 | #define UART0_PHYS_IO_BASE 0xf0000200 |
44 | #elif defined(CONFIG_440SPE) | ||
45 | #define UART0_PHYS_ERPN 4 | ||
46 | #define UART0_PHYS_IO_BASE 0xf0000200 | ||
44 | #elif defined(CONFIG_440EP) | 47 | #elif defined(CONFIG_440EP) |
45 | #define UART0_PHYS_IO_BASE 0xe0000000 | 48 | #define UART0_PHYS_IO_BASE 0xe0000000 |
46 | #else | 49 | #else |
@@ -61,6 +64,11 @@ | |||
61 | #define PPC44x_PCICFG_PAGE 0x0000000900000000ULL | 64 | #define PPC44x_PCICFG_PAGE 0x0000000900000000ULL |
62 | #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE | 65 | #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE |
63 | #define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL | 66 | #define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL |
67 | #elif defined(CONFIG_440SPE) | ||
68 | #define PPC44x_IO_PAGE 0x0000000400000000ULL | ||
69 | #define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL | ||
70 | #define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE | ||
71 | #define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL | ||
64 | #elif defined(CONFIG_440EP) | 72 | #elif defined(CONFIG_440EP) |
65 | #define PPC44x_IO_PAGE 0x0000000000000000ULL | 73 | #define PPC44x_IO_PAGE 0x0000000000000000ULL |
66 | #define PPC44x_PCICFG_PAGE 0x0000000000000000ULL | 74 | #define PPC44x_PCICFG_PAGE 0x0000000000000000ULL |
@@ -76,7 +84,7 @@ | |||
76 | /* | 84 | /* |
77 | * 36-bit trap ranges | 85 | * 36-bit trap ranges |
78 | */ | 86 | */ |
79 | #if defined(CONFIG_440SP) | 87 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
80 | #define PPC44x_IO_LO 0xf0000000UL | 88 | #define PPC44x_IO_LO 0xf0000000UL |
81 | #define PPC44x_IO_HI 0xf0000fffUL | 89 | #define PPC44x_IO_HI 0xf0000fffUL |
82 | #define PPC44x_PCI0CFG_LO 0x0ec00000UL | 90 | #define PPC44x_PCI0CFG_LO 0x0ec00000UL |
@@ -114,7 +122,7 @@ | |||
114 | */ | 122 | */ |
115 | 123 | ||
116 | 124 | ||
117 | /* CPRs (440GX and 440SP) */ | 125 | /* CPRs (440GX and 440SP/440SPe) */ |
118 | #define DCRN_CPR_CONFIG_ADDR 0xc | 126 | #define DCRN_CPR_CONFIG_ADDR 0xc |
119 | #define DCRN_CPR_CONFIG_DATA 0xd | 127 | #define DCRN_CPR_CONFIG_DATA 0xd |
120 | 128 | ||
@@ -135,7 +143,7 @@ | |||
135 | mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ | 143 | mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ |
136 | mtdcr(DCRN_CPR_CONFIG_DATA, data);}) | 144 | mtdcr(DCRN_CPR_CONFIG_DATA, data);}) |
137 | 145 | ||
138 | /* SDRs (440GX and 440SP) */ | 146 | /* SDRs (440GX and 440SP/440SPe) */ |
139 | #define DCRN_SDR_CONFIG_ADDR 0xe | 147 | #define DCRN_SDR_CONFIG_ADDR 0xe |
140 | #define DCRN_SDR_CONFIG_DATA 0xf | 148 | #define DCRN_SDR_CONFIG_DATA 0xf |
141 | #define DCRN_SDR_PFC0 0x4100 | 149 | #define DCRN_SDR_PFC0 0x4100 |
@@ -185,7 +193,7 @@ | |||
185 | mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ | 193 | mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ |
186 | mtdcr(DCRN_SDR_CONFIG_DATA,data);}) | 194 | mtdcr(DCRN_SDR_CONFIG_DATA,data);}) |
187 | 195 | ||
188 | /* DMA (excluding 440SP) */ | 196 | /* DMA (excluding 440SP/440SPe) */ |
189 | #define DCRN_DMA0_BASE 0x100 | 197 | #define DCRN_DMA0_BASE 0x100 |
190 | #define DCRN_DMA1_BASE 0x108 | 198 | #define DCRN_DMA1_BASE 0x108 |
191 | #define DCRN_DMA2_BASE 0x110 | 199 | #define DCRN_DMA2_BASE 0x110 |
@@ -205,12 +213,20 @@ | |||
205 | /* UIC */ | 213 | /* UIC */ |
206 | #define DCRN_UIC0_BASE 0xc0 | 214 | #define DCRN_UIC0_BASE 0xc0 |
207 | #define DCRN_UIC1_BASE 0xd0 | 215 | #define DCRN_UIC1_BASE 0xd0 |
208 | #define DCRN_UIC2_BASE 0x210 | ||
209 | #define DCRN_UICB_BASE 0x200 | ||
210 | #define UIC0 DCRN_UIC0_BASE | 216 | #define UIC0 DCRN_UIC0_BASE |
211 | #define UIC1 DCRN_UIC1_BASE | 217 | #define UIC1 DCRN_UIC1_BASE |
218 | |||
219 | #ifdef CONFIG_440SPE | ||
220 | #define DCRN_UIC2_BASE 0xe0 | ||
221 | #define DCRN_UIC3_BASE 0xf0 | ||
222 | #define UIC2 DCRN_UIC2_BASE | ||
223 | #define UIC3 DCRN_UIC3_BASE | ||
224 | #else | ||
225 | #define DCRN_UIC2_BASE 0x210 | ||
226 | #define DCRN_UICB_BASE 0x200 | ||
212 | #define UIC2 DCRN_UIC2_BASE | 227 | #define UIC2 DCRN_UIC2_BASE |
213 | #define UICB DCRN_UICB_BASE | 228 | #define UICB DCRN_UICB_BASE |
229 | #endif | ||
214 | 230 | ||
215 | #define DCRN_UIC_SR(base) (base + 0x0) | 231 | #define DCRN_UIC_SR(base) (base + 0x0) |
216 | #define DCRN_UIC_ER(base) (base + 0x2) | 232 | #define DCRN_UIC_ER(base) (base + 0x2) |
@@ -223,6 +239,12 @@ | |||
223 | 239 | ||
224 | #define UIC0_UIC1NC 0x00000002 | 240 | #define UIC0_UIC1NC 0x00000002 |
225 | 241 | ||
242 | #ifdef CONFIG_440SPE | ||
243 | #define UIC0_UIC1NC 0x00000002 | ||
244 | #define UIC0_UIC2NC 0x00200000 | ||
245 | #define UIC0_UIC3NC 0x00008000 | ||
246 | #endif | ||
247 | |||
226 | #define UICB_UIC0NC 0x40000000 | 248 | #define UICB_UIC0NC 0x40000000 |
227 | #define UICB_UIC1NC 0x10000000 | 249 | #define UICB_UIC1NC 0x10000000 |
228 | #define UICB_UIC2NC 0x04000000 | 250 | #define UICB_UIC2NC 0x04000000 |
@@ -302,8 +324,8 @@ | |||
302 | #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ | 324 | #define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ |
303 | #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ | 325 | #define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ |
304 | 326 | ||
305 | #if defined(CONFIG_440SP) | 327 | #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) |
306 | /* 440SP PLB Arbiter DCRs */ | 328 | /* 440SP/440SPe PLB Arbiter DCRs */ |
307 | #define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ | 329 | #define DCRN_PLB_REVID 0x080 /* PLB Revision ID */ |
308 | #define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ | 330 | #define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */ |
309 | 331 | ||
@@ -430,9 +452,13 @@ | |||
430 | #define PPC44x_MEM_SIZE_1G 0x40000000 | 452 | #define PPC44x_MEM_SIZE_1G 0x40000000 |
431 | #define PPC44x_MEM_SIZE_2G 0x80000000 | 453 | #define PPC44x_MEM_SIZE_2G 0x80000000 |
432 | 454 | ||
433 | /* 440SP memory controller DCRs */ | 455 | /* 440SP/440SPe memory controller DCRs */ |
434 | #define DCRN_MQ0_BS0BAS 0x40 | 456 | #define DCRN_MQ0_BS0BAS 0x40 |
435 | #define DCRN_MQ0_BS1BAS 0x41 | 457 | #if defined(CONFIG_440SP) |
458 | #define MQ0_NUM_BANKS 2 | ||
459 | #elif defined(CONFIG_440SPE) | ||
460 | #define MQ0_NUM_BANKS 4 | ||
461 | #endif | ||
436 | 462 | ||
437 | #define MQ0_CONFIG_SIZE_MASK 0x0000fff0 | 463 | #define MQ0_CONFIG_SIZE_MASK 0x0000fff0 |
438 | #define MQ0_CONFIG_SIZE_8M 0x0000ffc0 | 464 | #define MQ0_CONFIG_SIZE_8M 0x0000ffc0 |
@@ -444,8 +470,9 @@ | |||
444 | #define MQ0_CONFIG_SIZE_512M 0x0000f000 | 470 | #define MQ0_CONFIG_SIZE_512M 0x0000f000 |
445 | #define MQ0_CONFIG_SIZE_1G 0x0000e000 | 471 | #define MQ0_CONFIG_SIZE_1G 0x0000e000 |
446 | #define MQ0_CONFIG_SIZE_2G 0x0000c000 | 472 | #define MQ0_CONFIG_SIZE_2G 0x0000c000 |
473 | #define MQ0_CONFIG_SIZE_4G 0x00008000 | ||
447 | 474 | ||
448 | /* Internal SRAM Controller 440GX/440SP */ | 475 | /* Internal SRAM Controller 440GX/440SP/440SPe */ |
449 | #define DCRN_SRAM0_BASE 0x000 | 476 | #define DCRN_SRAM0_BASE 0x000 |
450 | 477 | ||
451 | #define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) | 478 | #define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) |
@@ -469,7 +496,7 @@ | |||
469 | #define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) | 496 | #define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) |
470 | #define SRAM_DPC_ENABLE 0x80000000 | 497 | #define SRAM_DPC_ENABLE 0x80000000 |
471 | 498 | ||
472 | /* L2 Cache Controller 440GX/440SP */ | 499 | /* L2 Cache Controller 440GX/440SP/440SPe */ |
473 | #define DCRN_L2C0_CFG 0x030 | 500 | #define DCRN_L2C0_CFG 0x030 |
474 | #define L2C_CFG_L2M 0x80000000 | 501 | #define L2C_CFG_L2M 0x80000000 |
475 | #define L2C_CFG_ICU 0x40000000 | 502 | #define L2C_CFG_ICU 0x40000000 |
@@ -633,8 +660,10 @@ | |||
633 | #define IIC_CLOCK 50 | 660 | #define IIC_CLOCK 50 |
634 | 661 | ||
635 | #undef NR_UICS | 662 | #undef NR_UICS |
636 | #ifdef CONFIG_440GX | 663 | #if defined(CONFIG_440GX) |
637 | #define NR_UICS 3 | 664 | #define NR_UICS 3 |
665 | #elif defined(CONFIG_440SPE) | ||
666 | #define NR_UICS 4 | ||
638 | #else | 667 | #else |
639 | #define NR_UICS 2 | 668 | #define NR_UICS 2 |
640 | #endif | 669 | #endif |