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diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
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1/*
2 * include/asm-ppc/ibm44x.h
3 *
4 * PPC44x definitions
5 *
6 * Matt Porter <mporter@kernel.crashing.org>
7 *
8 * Copyright 2002-2005 MontaVista Software Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16#ifdef __KERNEL__
17#ifndef __ASM_IBM44x_H__
18#define __ASM_IBM44x_H__
19
20
21#ifndef NR_BOARD_IRQS
22#define NR_BOARD_IRQS 0
23#endif
24
25#define _IO_BASE isa_io_base
26#define _ISA_MEM_BASE isa_mem_base
27#define PCI_DRAM_OFFSET pci_dram_offset
28
29/* TLB entry offset/size used for pinning kernel lowmem */
30#define PPC44x_PIN_SHIFT 28
31#define PPC_PIN_SIZE (1 << PPC44x_PIN_SHIFT)
32
33/* Lowest TLB slot consumed by the default pinned TLBs */
34#define PPC44x_LOW_SLOT 63
35
36/*
37 * Least significant 32-bits and extended real page number (ERPN) of
38 * UART0 physical address location for early serial text debug
39 */
40#if defined(CONFIG_440SP)
41#define UART0_PHYS_ERPN 1
42#define UART0_PHYS_IO_BASE 0xf0000200
43#elif defined(CONFIG_440SPE)
44#define UART0_PHYS_ERPN 4
45#define UART0_PHYS_IO_BASE 0xf0000200
46#elif defined(CONFIG_440EP)
47#define UART0_PHYS_IO_BASE 0xe0000000
48#else
49#define UART0_PHYS_ERPN 1
50#define UART0_PHYS_IO_BASE 0x40000200
51#endif
52
53/*
54 * XXX This 36-bit trap stuff will move somewhere in syslib/
55 * when we rework/abstract the PPC44x PCI-X handling -mdp
56 */
57
58/*
59 * Standard 4GB "page" definitions
60 */
61#if defined(CONFIG_440SP)
62#define PPC44x_IO_PAGE 0x0000000100000000ULL
63#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
64#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
65#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
66#elif defined(CONFIG_440SPE)
67#define PPC44x_IO_PAGE 0x0000000400000000ULL
68#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL
69#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
70#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL
71#elif defined(CONFIG_440EP)
72#define PPC44x_IO_PAGE 0x0000000000000000ULL
73#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
74#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
75#define PPC44x_PCIMEM_PAGE 0x0000000000000000ULL
76#else
77#define PPC44x_IO_PAGE 0x0000000100000000ULL
78#define PPC44x_PCICFG_PAGE 0x0000000200000000ULL
79#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
80#define PPC44x_PCIMEM_PAGE 0x0000000300000000ULL
81#endif
82
83/*
84 * 36-bit trap ranges
85 */
86#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
87#define PPC44x_IO_LO 0xf0000000UL
88#define PPC44x_IO_HI 0xf0000fffUL
89#define PPC44x_PCI0CFG_LO 0x0ec00000UL
90#define PPC44x_PCI0CFG_HI 0x0ec00007UL
91#define PPC44x_PCI1CFG_LO 0x1ec00000UL
92#define PPC44x_PCI1CFG_HI 0x1ec00007UL
93#define PPC44x_PCI2CFG_LO 0x2ec00000UL
94#define PPC44x_PCI2CFG_HI 0x2ec00007UL
95#define PPC44x_PCIMEM_LO 0x80000000UL
96#define PPC44x_PCIMEM_HI 0xdfffffffUL
97#elif defined(CONFIG_440EP)
98#define PPC44x_IO_LO 0xef500000UL
99#define PPC44x_IO_HI 0xefffffffUL
100#define PPC44x_PCI0CFG_LO 0xeec00000UL
101#define PPC44x_PCI0CFG_HI 0xeecfffffUL
102#define PPC44x_PCIMEM_LO 0xa0000000UL
103#define PPC44x_PCIMEM_HI 0xdfffffffUL
104#else
105#define PPC44x_IO_LO 0x40000000UL
106#define PPC44x_IO_HI 0x40000fffUL
107#define PPC44x_PCI0CFG_LO 0x0ec00000UL
108#define PPC44x_PCI0CFG_HI 0x0ec00007UL
109#define PPC44x_PCIMEM_LO 0x80002000UL
110#define PPC44x_PCIMEM_HI 0xffffffffUL
111#endif
112
113/*
114 * The "residual" board information structure the boot loader passes
115 * into the kernel.
116 */
117#ifndef __ASSEMBLY__
118
119/*
120 * DCRN definitions
121 */
122
123
124/* CPRs (440GX and 440SP/440SPe) */
125#define DCRN_CPR_CONFIG_ADDR 0xc
126#define DCRN_CPR_CONFIG_DATA 0xd
127
128#define DCRN_CPR_CLKUPD 0x0020
129#define DCRN_CPR_PLLC 0x0040
130#define DCRN_CPR_PLLD 0x0060
131#define DCRN_CPR_PRIMAD 0x0080
132#define DCRN_CPR_PRIMBD 0x00a0
133#define DCRN_CPR_OPBD 0x00c0
134#define DCRN_CPR_PERD 0x00e0
135#define DCRN_CPR_MALD 0x0100
136
137/* CPRs read/write helper macros */
138#define CPR_READ(offset) ({\
139 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
140 mfdcr(DCRN_CPR_CONFIG_DATA);})
141#define CPR_WRITE(offset, data) ({\
142 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
143 mtdcr(DCRN_CPR_CONFIG_DATA, data);})
144
145/* SDRs (440GX and 440SP/440SPe) */
146#define DCRN_SDR_CONFIG_ADDR 0xe
147#define DCRN_SDR_CONFIG_DATA 0xf
148#define DCRN_SDR_PFC0 0x4100
149#define DCRN_SDR_PFC1 0x4101
150#define DCRN_SDR_PFC1_EPS 0x1c00000
151#define DCRN_SDR_PFC1_EPS_SHIFT 22
152#define DCRN_SDR_PFC1_RMII 0x02000000
153#define DCRN_SDR_MFR 0x4300
154#define DCRN_SDR_MFR_TAH0 0x80000000 /* TAHOE0 Enable */
155#define DCRN_SDR_MFR_TAH1 0x40000000 /* TAHOE1 Enable */
156#define DCRN_SDR_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */
157#define DCRN_SDR_MFR_ECS 0x08000000 /* EMAC int clk */
158#define DCRN_SDR_MFR_T0TXFL 0x00080000
159#define DCRN_SDR_MFR_T0TXFH 0x00040000
160#define DCRN_SDR_MFR_T1TXFL 0x00020000
161#define DCRN_SDR_MFR_T1TXFH 0x00010000
162#define DCRN_SDR_MFR_E0TXFL 0x00008000
163#define DCRN_SDR_MFR_E0TXFH 0x00004000
164#define DCRN_SDR_MFR_E0RXFL 0x00002000
165#define DCRN_SDR_MFR_E0RXFH 0x00001000
166#define DCRN_SDR_MFR_E1TXFL 0x00000800
167#define DCRN_SDR_MFR_E1TXFH 0x00000400
168#define DCRN_SDR_MFR_E1RXFL 0x00000200
169#define DCRN_SDR_MFR_E1RXFH 0x00000100
170#define DCRN_SDR_MFR_E2TXFL 0x00000080
171#define DCRN_SDR_MFR_E2TXFH 0x00000040
172#define DCRN_SDR_MFR_E2RXFL 0x00000020
173#define DCRN_SDR_MFR_E2RXFH 0x00000010
174#define DCRN_SDR_MFR_E3TXFL 0x00000008
175#define DCRN_SDR_MFR_E3TXFH 0x00000004
176#define DCRN_SDR_MFR_E3RXFL 0x00000002
177#define DCRN_SDR_MFR_E3RXFH 0x00000001
178#define DCRN_SDR_UART0 0x0120
179#define DCRN_SDR_UART1 0x0121
180
181#ifdef CONFIG_440EP
182#define DCRN_SDR_UART2 0x0122
183#define DCRN_SDR_UART3 0x0123
184#define DCRN_SDR_CUST0 0x4000
185#endif
186
187/* SDR read/write helper macros */
188#define SDR_READ(offset) ({\
189 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
190 mfdcr(DCRN_SDR_CONFIG_DATA);})
191#define SDR_WRITE(offset, data) ({\
192 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
193 mtdcr(DCRN_SDR_CONFIG_DATA,data);})
194
195/* DMA (excluding 440SP/440SPe) */
196#define DCRN_DMA0_BASE 0x100
197#define DCRN_DMA1_BASE 0x108
198#define DCRN_DMA2_BASE 0x110
199#define DCRN_DMA3_BASE 0x118
200#define DCRN_DMASR_BASE 0x120
201#define DCRNCAP_DMA_SG 1 /* have DMA scatter/gather capability */
202#define DCRN_MAL_BASE 0x180
203
204#ifdef CONFIG_440EP
205#define DCRN_DMA2P40_BASE 0x300
206#define DCRN_DMA2P41_BASE 0x308
207#define DCRN_DMA2P42_BASE 0x310
208#define DCRN_DMA2P43_BASE 0x318
209#define DCRN_DMA2P4SR_BASE 0x320
210#endif
211
212/* UIC */
213#define DCRN_UIC0_BASE 0xc0
214#define DCRN_UIC1_BASE 0xd0
215#define UIC0 DCRN_UIC0_BASE
216#define UIC1 DCRN_UIC1_BASE
217
218#ifdef CONFIG_440SPE
219#define DCRN_UIC2_BASE 0xe0
220#define DCRN_UIC3_BASE 0xf0
221#define UIC2 DCRN_UIC2_BASE
222#define UIC3 DCRN_UIC3_BASE
223#else
224#define DCRN_UIC2_BASE 0x210
225#define DCRN_UICB_BASE 0x200
226#define UIC2 DCRN_UIC2_BASE
227#define UICB DCRN_UICB_BASE
228#endif
229
230#define DCRN_UIC_SR(base) (base + 0x0)
231#define DCRN_UIC_ER(base) (base + 0x2)
232#define DCRN_UIC_CR(base) (base + 0x3)
233#define DCRN_UIC_PR(base) (base + 0x4)
234#define DCRN_UIC_TR(base) (base + 0x5)
235#define DCRN_UIC_MSR(base) (base + 0x6)
236#define DCRN_UIC_VR(base) (base + 0x7)
237#define DCRN_UIC_VCR(base) (base + 0x8)
238
239#define UIC0_UIC1NC 0x00000002
240
241#ifdef CONFIG_440SPE
242#define UIC0_UIC1NC 0x00000002
243#define UIC0_UIC2NC 0x00200000
244#define UIC0_UIC3NC 0x00008000
245#endif
246
247#define UICB_UIC0NC 0x40000000
248#define UICB_UIC1NC 0x10000000
249#define UICB_UIC2NC 0x04000000
250
251/* 440 MAL DCRs */
252#define DCRN_MALCR(base) (base + 0x0) /* Configuration */
253#define DCRN_MALESR(base) (base + 0x1) /* Error Status */
254#define DCRN_MALIER(base) (base + 0x2) /* Interrupt Enable */
255#define DCRN_MALTXCASR(base) (base + 0x4) /* Tx Channel Active Set */
256#define DCRN_MALTXCARR(base) (base + 0x5) /* Tx Channel Active Reset */
257#define DCRN_MALTXEOBISR(base) (base + 0x6) /* Tx End of Buffer Interrupt Status */
258#define DCRN_MALTXDEIR(base) (base + 0x7) /* Tx Descriptor Error Interrupt */
259#define DCRN_MALRXCASR(base) (base + 0x10) /* Rx Channel Active Set */
260#define DCRN_MALRXCARR(base) (base + 0x11) /* Rx Channel Active Reset */
261#define DCRN_MALRXEOBISR(base) (base + 0x12) /* Rx End of Buffer Interrupt Status */
262#define DCRN_MALRXDEIR(base) (base + 0x13) /* Rx Descriptor Error Interrupt */
263#define DCRN_MALTXCTP0R(base) (base + 0x20) /* Channel Tx 0 Channel Table Pointer */
264#define DCRN_MALTXCTP1R(base) (base + 0x21) /* Channel Tx 1 Channel Table Pointer */
265#define DCRN_MALTXCTP2R(base) (base + 0x22) /* Channel Tx 2 Channel Table Pointer */
266#define DCRN_MALTXCTP3R(base) (base + 0x23) /* Channel Tx 3 Channel Table Pointer */
267#define DCRN_MALRXCTP0R(base) (base + 0x40) /* Channel Rx 0 Channel Table Pointer */
268#define DCRN_MALRXCTP1R(base) (base + 0x41) /* Channel Rx 1 Channel Table Pointer */
269#define DCRN_MALRCBS0(base) (base + 0x60) /* Channel Rx 0 Channel Buffer Size */
270#define DCRN_MALRCBS1(base) (base + 0x61) /* Channel Rx 1 Channel Buffer Size */
271
272/* Compatibility DCRN's */
273#define DCRN_MALRXCTP2R(base) ((base) + 0x42) /* Channel Rx 2 Channel Table Pointer */
274#define DCRN_MALRXCTP3R(base) ((base) + 0x43) /* Channel Rx 3 Channel Table Pointer */
275#define DCRN_MALTXCTP4R(base) ((base) + 0x24) /* Channel Tx 4 Channel Table Pointer */
276#define DCRN_MALTXCTP5R(base) ((base) + 0x25) /* Channel Tx 5 Channel Table Pointer */
277#define DCRN_MALTXCTP6R(base) ((base) + 0x26) /* Channel Tx 6 Channel Table Pointer */
278#define DCRN_MALTXCTP7R(base) ((base) + 0x27) /* Channel Tx 7 Channel Table Pointer */
279#define DCRN_MALRCBS2(base) ((base) + 0x62) /* Channel Rx 2 Channel Buffer Size */
280#define DCRN_MALRCBS3(base) ((base) + 0x63) /* Channel Rx 3 Channel Buffer Size */
281
282#define MALCR_MMSR 0x80000000 /* MAL Software reset */
283#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */
284#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */
285#define MALCR_PLBP_3 0x00C00000 /* highest */
286#define MALCR_GA 0x00200000 /* Guarded Active Bit */
287#define MALCR_OA 0x00100000 /* Ordered Active Bit */
288#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */
289#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */
290#define MALCR_PLBLT_2 0x00020000
291#define MALCR_PLBLT_3 0x00010000
292#define MALCR_PLBLT_4 0x00008000
293#ifdef CONFIG_440GP
294#define MALCR_PLBLT_DEFAULT 0x00330000 /* PLB Latency Timer default */
295#else
296#define MALCR_PLBLT_DEFAULT 0x00ff0000 /* PLB Latency Timer default */
297#endif
298#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */
299#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */
300#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */
301#define MALCR_LEA 0x00000002 /* Locked Error Active */
302#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */
303/* DCRN_MALESR */
304#define MALESR_EVB 0x80000000 /* Error Valid Bit */
305#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */
306#define MALESR_DE 0x00100000 /* Descriptor Error */
307#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */
308#define MALESR_OTE 0x00040000 /* OPB Timeout Error */
309#define MALESR_OSE 0x00020000 /* OPB Slave Error */
310#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */
311#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */
312#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */
313#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */
314#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */
315#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */
316/* DCRN_MALIER */
317#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */
318#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */
319#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */
320#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */
321#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */
322/* DCRN_MALTXEOBISR */
323#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
324#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
325
326#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
327/* 440SP/440SPe PLB Arbiter DCRs */
328#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */
329#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */
330
331#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */
332#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */
333#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */
334#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */
335#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */
336
337#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */
338#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */
339#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */
340#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */
341#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */
342#else
343/* 440GP/GX PLB Arbiter DCRs */
344#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
345#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
346#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */
347#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
348#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
349#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
350#endif
351
352/* 440GP/GX PLB to OPB bridge DCRs */
353#define DCRN_POB0_BESR0 0x090
354#define DCRN_POB0_BESR1 0x094
355#define DCRN_POB0_BEARL 0x092
356#define DCRN_POB0_BEARH 0x093
357
358/* 440GP/GX OPB to PLB bridge DCRs */
359#define DCRN_OPB0_BSTAT 0x0a9
360#define DCRN_OPB0_BEARL 0x0aa
361#define DCRN_OPB0_BEARH 0x0ab
362
363/* 440GP Clock, PM, chip control */
364#define DCRN_CPC0_SR 0x0b0
365#define DCRN_CPC0_ER 0x0b1
366#define DCRN_CPC0_FR 0x0b2
367#define DCRN_CPC0_SYS0 0x0e0
368#define DCRN_CPC0_SYS1 0x0e1
369#define DCRN_CPC0_CUST0 0x0e2
370#define DCRN_CPC0_CUST1 0x0e3
371#define DCRN_CPC0_STRP0 0x0e4
372#define DCRN_CPC0_STRP1 0x0e5
373#define DCRN_CPC0_STRP2 0x0e6
374#define DCRN_CPC0_STRP3 0x0e7
375#define DCRN_CPC0_GPIO 0x0e8
376#define DCRN_CPC0_PLB 0x0e9
377#define DCRN_CPC0_CR1 0x0ea
378#define DCRN_CPC0_CR0 0x0eb
379#define DCRN_CPC0_MIRQ0 0x0ec
380#define DCRN_CPC0_MIRQ1 0x0ed
381#define DCRN_CPC0_JTAGID 0x0ef
382
383/* 440GP DMA controller DCRs */
384#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control 0 */
385#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count 0 */
386#define DCRN_DMASAH0 (DCRN_DMA0_BASE + 0x2) /* DMA Src Addr High 0 */
387#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Src Addr Low 0 */
388#define DCRN_DMADAH0 (DCRN_DMA0_BASE + 0x4) /* DMA Dest Addr High 0 */
389#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x5) /* DMA Dest Addr Low 0 */
390#define DCRN_ASGH0 (DCRN_DMA0_BASE + 0x6) /* DMA SG Desc Addr High 0 */
391#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x7) /* DMA SG Desc Addr Low 0 */
392
393#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control 1 */
394#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count 1 */
395#define DCRN_DMASAH1 (DCRN_DMA1_BASE + 0x2) /* DMA Src Addr High 1 */
396#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Src Addr Low 1 */
397#define DCRN_DMADAH1 (DCRN_DMA1_BASE + 0x4) /* DMA Dest Addr High 1 */
398#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x5) /* DMA Dest Addr Low 1 */
399#define DCRN_ASGH1 (DCRN_DMA1_BASE + 0x6) /* DMA SG Desc Addr High 1 */
400#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x7) /* DMA SG Desc Addr Low 1 */
401
402#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control 2 */
403#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count 2 */
404#define DCRN_DMASAH2 (DCRN_DMA2_BASE + 0x2) /* DMA Src Addr High 2 */
405#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Src Addr Low 2 */
406#define DCRN_DMADAH2 (DCRN_DMA2_BASE + 0x4) /* DMA Dest Addr High 2 */
407#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x5) /* DMA Dest Addr Low 2 */
408#define DCRN_ASGH2 (DCRN_DMA2_BASE + 0x6) /* DMA SG Desc Addr High 2 */
409#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x7) /* DMA SG Desc Addr Low 2 */
410
411#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control 3 */
412#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count 3 */
413#define DCRN_DMASAH3 (DCRN_DMA3_BASE + 0x2) /* DMA Src Addr High 3 */
414#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Src Addr Low 3 */
415#define DCRN_DMADAH3 (DCRN_DMA3_BASE + 0x4) /* DMA Dest Addr High 3 */
416#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x5) /* DMA Dest Addr Low 3 */
417#define DCRN_ASGH3 (DCRN_DMA3_BASE + 0x6) /* DMA SG Desc Addr High 3 */
418#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x7) /* DMA SG Desc Addr Low 3 */
419
420#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */
421#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */
422#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */
423#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */
424
425/* 440GP/440GX SDRAM controller DCRs */
426#define DCRN_SDRAM0_CFGADDR 0x010
427#define DCRN_SDRAM0_CFGDATA 0x011
428
429#define SDRAM0_B0CR 0x40
430#define SDRAM0_B1CR 0x44
431#define SDRAM0_B2CR 0x48
432#define SDRAM0_B3CR 0x4c
433
434#define SDRAM_CONFIG_BANK_ENABLE 0x00000001
435#define SDRAM_CONFIG_SIZE_MASK 0x000e0000
436#define SDRAM_CONFIG_BANK_SIZE(reg) ((reg & SDRAM_CONFIG_SIZE_MASK) >> 17)
437#define SDRAM_CONFIG_SIZE_8M 0x00000001
438#define SDRAM_CONFIG_SIZE_16M 0x00000002
439#define SDRAM_CONFIG_SIZE_32M 0x00000003
440#define SDRAM_CONFIG_SIZE_64M 0x00000004
441#define SDRAM_CONFIG_SIZE_128M 0x00000005
442#define SDRAM_CONFIG_SIZE_256M 0x00000006
443#define SDRAM_CONFIG_SIZE_512M 0x00000007
444#define PPC44x_MEM_SIZE_8M 0x00800000
445#define PPC44x_MEM_SIZE_16M 0x01000000
446#define PPC44x_MEM_SIZE_32M 0x02000000
447#define PPC44x_MEM_SIZE_64M 0x04000000
448#define PPC44x_MEM_SIZE_128M 0x08000000
449#define PPC44x_MEM_SIZE_256M 0x10000000
450#define PPC44x_MEM_SIZE_512M 0x20000000
451#define PPC44x_MEM_SIZE_1G 0x40000000
452#define PPC44x_MEM_SIZE_2G 0x80000000
453
454/* 440SP/440SPe memory controller DCRs */
455#define DCRN_MQ0_BS0BAS 0x40
456#if defined(CONFIG_440SP)
457#define MQ0_NUM_BANKS 2
458#elif defined(CONFIG_440SPE)
459#define MQ0_NUM_BANKS 4
460#endif
461
462#define MQ0_CONFIG_SIZE_MASK 0x0000fff0
463#define MQ0_CONFIG_SIZE_8M 0x0000ffc0
464#define MQ0_CONFIG_SIZE_16M 0x0000ff80
465#define MQ0_CONFIG_SIZE_32M 0x0000ff00
466#define MQ0_CONFIG_SIZE_64M 0x0000fe00
467#define MQ0_CONFIG_SIZE_128M 0x0000fc00
468#define MQ0_CONFIG_SIZE_256M 0x0000f800
469#define MQ0_CONFIG_SIZE_512M 0x0000f000
470#define MQ0_CONFIG_SIZE_1G 0x0000e000
471#define MQ0_CONFIG_SIZE_2G 0x0000c000
472#define MQ0_CONFIG_SIZE_4G 0x00008000
473
474/* Internal SRAM Controller 440GX/440SP/440SPe */
475#define DCRN_SRAM0_BASE 0x000
476
477#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
478#define DCRN_SRAM0_SB1CR (DCRN_SRAM0_BASE + 0x021)
479#define DCRN_SRAM0_SB2CR (DCRN_SRAM0_BASE + 0x022)
480#define DCRN_SRAM0_SB3CR (DCRN_SRAM0_BASE + 0x023)
481#define SRAM_SBCR_BAS0 0x80000000
482#define SRAM_SBCR_BAS1 0x80010000
483#define SRAM_SBCR_BAS2 0x80020000
484#define SRAM_SBCR_BAS3 0x80030000
485#define SRAM_SBCR_BU_MASK 0x00000180
486#define SRAM_SBCR_BS_64KB 0x00000800
487#define SRAM_SBCR_BU_RO 0x00000080
488#define SRAM_SBCR_BU_RW 0x00000180
489#define DCRN_SRAM0_BEAR (DCRN_SRAM0_BASE + 0x024)
490#define DCRN_SRAM0_BESR0 (DCRN_SRAM0_BASE + 0x025)
491#define DCRN_SRAM0_BESR1 (DCRN_SRAM0_BASE + 0x026)
492#define DCRN_SRAM0_PMEG (DCRN_SRAM0_BASE + 0x027)
493#define DCRN_SRAM0_CID (DCRN_SRAM0_BASE + 0x028)
494#define DCRN_SRAM0_REVID (DCRN_SRAM0_BASE + 0x029)
495#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a)
496#define SRAM_DPC_ENABLE 0x80000000
497
498/* L2 Cache Controller 440GX/440SP/440SPe */
499#define DCRN_L2C0_CFG 0x030
500#define L2C_CFG_L2M 0x80000000
501#define L2C_CFG_ICU 0x40000000
502#define L2C_CFG_DCU 0x20000000
503#define L2C_CFG_DCW_MASK 0x1e000000
504#define L2C_CFG_TPC 0x01000000
505#define L2C_CFG_CPC 0x00800000
506#define L2C_CFG_FRAN 0x00200000
507#define L2C_CFG_SS_MASK 0x00180000
508#define L2C_CFG_SS_256 0x00000000
509#define L2C_CFG_CPIM 0x00040000
510#define L2C_CFG_TPIM 0x00020000
511#define L2C_CFG_LIM 0x00010000
512#define L2C_CFG_PMUX_MASK 0x00007000
513#define L2C_CFG_PMUX_SNP 0x00000000
514#define L2C_CFG_PMUX_IF 0x00001000
515#define L2C_CFG_PMUX_DF 0x00002000
516#define L2C_CFG_PMUX_DS 0x00003000
517#define L2C_CFG_PMIM 0x00000800
518#define L2C_CFG_TPEI 0x00000400
519#define L2C_CFG_CPEI 0x00000200
520#define L2C_CFG_NAM 0x00000100
521#define L2C_CFG_SMCM 0x00000080
522#define L2C_CFG_NBRM 0x00000040
523#define DCRN_L2C0_CMD 0x031
524#define L2C_CMD_CLR 0x80000000
525#define L2C_CMD_DIAG 0x40000000
526#define L2C_CMD_INV 0x20000000
527#define L2C_CMD_CCP 0x10000000
528#define L2C_CMD_CTE 0x08000000
529#define L2C_CMD_STRC 0x04000000
530#define L2C_CMD_STPC 0x02000000
531#define L2C_CMD_RPMC 0x01000000
532#define L2C_CMD_HCC 0x00800000
533#define DCRN_L2C0_ADDR 0x032
534#define DCRN_L2C0_DATA 0x033
535#define DCRN_L2C0_SR 0x034
536#define L2C_SR_CC 0x80000000
537#define L2C_SR_CPE 0x40000000
538#define L2C_SR_TPE 0x20000000
539#define L2C_SR_LRU 0x10000000
540#define L2C_SR_PCS 0x08000000
541#define DCRN_L2C0_REVID 0x035
542#define DCRN_L2C0_SNP0 0x036
543#define DCRN_L2C0_SNP1 0x037
544#define L2C_SNP_BA_MASK 0xffff0000
545#define L2C_SNP_SSR_MASK 0x0000f000
546#define L2C_SNP_SSR_32G 0x0000f000
547#define L2C_SNP_ESR 0x00000800
548
549/*
550 * PCI-X definitions
551 */
552#define PCIX0_CFGA 0x0ec00000UL
553#define PCIX1_CFGA 0x1ec00000UL
554#define PCIX2_CFGA 0x2ec00000UL
555#define PCIX0_CFGD 0x0ec00004UL
556#define PCIX1_CFGD 0x1ec00004UL
557#define PCIX2_CFGD 0x2ec00004UL
558
559#define PCIX0_IO_BASE 0x0000000908000000ULL
560#define PCIX1_IO_BASE 0x0000000908000000ULL
561#define PCIX2_IO_BASE 0x0000000908000000ULL
562#define PCIX_IO_SIZE 0x00010000
563
564#ifdef CONFIG_440SP
565#define PCIX0_REG_BASE 0x000000090ec80000ULL
566#else
567#define PCIX0_REG_BASE 0x000000020ec80000ULL
568#endif
569#define PCIX_REG_OFFSET 0x10000000
570#define PCIX_REG_SIZE 0x200
571
572#define PCIX0_VENDID 0x000
573#define PCIX0_DEVID 0x002
574#define PCIX0_COMMAND 0x004
575#define PCIX0_STATUS 0x006
576#define PCIX0_REVID 0x008
577#define PCIX0_CLS 0x009
578#define PCIX0_CACHELS 0x00c
579#define PCIX0_LATTIM 0x00d
580#define PCIX0_HDTYPE 0x00e
581#define PCIX0_BIST 0x00f
582#define PCIX0_BAR0L 0x010
583#define PCIX0_BAR0H 0x014
584#define PCIX0_BAR1 0x018
585#define PCIX0_BAR2L 0x01c
586#define PCIX0_BAR2H 0x020
587#define PCIX0_BAR3 0x024
588#define PCIX0_CISPTR 0x028
589#define PCIX0_SBSYSVID 0x02c
590#define PCIX0_SBSYSID 0x02e
591#define PCIX0_EROMBA 0x030
592#define PCIX0_CAP 0x034
593#define PCIX0_RES0 0x035
594#define PCIX0_RES1 0x036
595#define PCIX0_RES2 0x038
596#define PCIX0_INTLN 0x03c
597#define PCIX0_INTPN 0x03d
598#define PCIX0_MINGNT 0x03e
599#define PCIX0_MAXLTNCY 0x03f
600#define PCIX0_BRDGOPT1 0x040
601#define PCIX0_BRDGOPT2 0x044
602#define PCIX0_ERREN 0x050
603#define PCIX0_ERRSTS 0x054
604#define PCIX0_PLBBESR 0x058
605#define PCIX0_PLBBEARL 0x05c
606#define PCIX0_PLBBEARH 0x060
607#define PCIX0_POM0LAL 0x068
608#define PCIX0_POM0LAH 0x06c
609#define PCIX0_POM0SA 0x070
610#define PCIX0_POM0PCIAL 0x074
611#define PCIX0_POM0PCIAH 0x078
612#define PCIX0_POM1LAL 0x07c
613#define PCIX0_POM1LAH 0x080
614#define PCIX0_POM1SA 0x084
615#define PCIX0_POM1PCIAL 0x088
616#define PCIX0_POM1PCIAH 0x08c
617#define PCIX0_POM2SA 0x090
618#define PCIX0_PIM0SAL 0x098
619#define PCIX0_PIM0SA PCIX0_PIM0SAL
620#define PCIX0_PIM0LAL 0x09c
621#define PCIX0_PIM0LAH 0x0a0
622#define PCIX0_PIM1SA 0x0a4
623#define PCIX0_PIM1LAL 0x0a8
624#define PCIX0_PIM1LAH 0x0ac
625#define PCIX0_PIM2SAL 0x0b0
626#define PCIX0_PIM2SA PCIX0_PIM2SAL
627#define PCIX0_PIM2LAL 0x0b4
628#define PCIX0_PIM2LAH 0x0b8
629#define PCIX0_OMCAPID 0x0c0
630#define PCIX0_OMNIPTR 0x0c1
631#define PCIX0_OMMC 0x0c2
632#define PCIX0_OMMA 0x0c4
633#define PCIX0_OMMUA 0x0c8
634#define PCIX0_OMMDATA 0x0cc
635#define PCIX0_OMMEOI 0x0ce
636#define PCIX0_PMCAPID 0x0d0
637#define PCIX0_PMNIPTR 0x0d1
638#define PCIX0_PMC 0x0d2
639#define PCIX0_PMCSR 0x0d4
640#define PCIX0_PMCSRBSE 0x0d6
641#define PCIX0_PMDATA 0x0d7
642#define PCIX0_PMSCRR 0x0d8
643#define PCIX0_CAPID 0x0dc
644#define PCIX0_NIPTR 0x0dd
645#define PCIX0_CMD 0x0de
646#define PCIX0_STS 0x0e0
647#define PCIX0_IDR 0x0e4
648#define PCIX0_CID 0x0e8
649#define PCIX0_RID 0x0ec
650#define PCIX0_PIM0SAH 0x0f8
651#define PCIX0_PIM2SAH 0x0fc
652#define PCIX0_MSGIL 0x100
653#define PCIX0_MSGIH 0x104
654#define PCIX0_MSGOL 0x108
655#define PCIX0_MSGOH 0x10c
656#define PCIX0_IM 0x1f8
657
658#define IIC_OWN 0x55
659#define IIC_CLOCK 50
660
661#undef NR_UICS
662#if defined(CONFIG_440GX)
663#define NR_UICS 3
664#elif defined(CONFIG_440SPE)
665#define NR_UICS 4
666#else
667#define NR_UICS 2
668#endif
669
670#include <asm/ibm4xx.h>
671
672#endif /* __ASSEMBLY__ */
673#endif /* __ASM_IBM44x_H__ */
674#endif /* __KERNEL__ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-18 22:51:30 -0500