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-rw-r--r--include/asm-ppc/ibm44x.h76
1 files changed, 64 insertions, 12 deletions
diff --git a/include/asm-ppc/ibm44x.h b/include/asm-ppc/ibm44x.h
index e5374be86aef..f835066fb3ca 100644
--- a/include/asm-ppc/ibm44x.h
+++ b/include/asm-ppc/ibm44x.h
@@ -34,12 +34,20 @@
34/* Lowest TLB slot consumed by the default pinned TLBs */ 34/* Lowest TLB slot consumed by the default pinned TLBs */
35#define PPC44x_LOW_SLOT 63 35#define PPC44x_LOW_SLOT 63
36 36
37/* LS 32-bits of UART0 physical address location for early serial text debug */ 37/*
38 * Least significant 32-bits and extended real page number (ERPN) of
39 * UART0 physical address location for early serial text debug
40 */
38#if defined(CONFIG_440SP) 41#if defined(CONFIG_440SP)
42#define UART0_PHYS_ERPN 1
43#define UART0_PHYS_IO_BASE 0xf0000200
44#elif defined(CONFIG_440SPE)
45#define UART0_PHYS_ERPN 4
39#define UART0_PHYS_IO_BASE 0xf0000200 46#define UART0_PHYS_IO_BASE 0xf0000200
40#elif defined(CONFIG_440EP) 47#elif defined(CONFIG_440EP)
41#define UART0_PHYS_IO_BASE 0xe0000000 48#define UART0_PHYS_IO_BASE 0xe0000000
42#else 49#else
50#define UART0_PHYS_ERPN 1
43#define UART0_PHYS_IO_BASE 0x40000200 51#define UART0_PHYS_IO_BASE 0x40000200
44#endif 52#endif
45 53
@@ -56,6 +64,11 @@
56#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL 64#define PPC44x_PCICFG_PAGE 0x0000000900000000ULL
57#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE 65#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
58#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL 66#define PPC44x_PCIMEM_PAGE 0x0000000a00000000ULL
67#elif defined(CONFIG_440SPE)
68#define PPC44x_IO_PAGE 0x0000000400000000ULL
69#define PPC44x_PCICFG_PAGE 0x0000000c00000000ULL
70#define PPC44x_PCIIO_PAGE PPC44x_PCICFG_PAGE
71#define PPC44x_PCIMEM_PAGE 0x0000000d00000000ULL
59#elif defined(CONFIG_440EP) 72#elif defined(CONFIG_440EP)
60#define PPC44x_IO_PAGE 0x0000000000000000ULL 73#define PPC44x_IO_PAGE 0x0000000000000000ULL
61#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL 74#define PPC44x_PCICFG_PAGE 0x0000000000000000ULL
@@ -71,7 +84,7 @@
71/* 84/*
72 * 36-bit trap ranges 85 * 36-bit trap ranges
73 */ 86 */
74#if defined(CONFIG_440SP) 87#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
75#define PPC44x_IO_LO 0xf0000000UL 88#define PPC44x_IO_LO 0xf0000000UL
76#define PPC44x_IO_HI 0xf0000fffUL 89#define PPC44x_IO_HI 0xf0000fffUL
77#define PPC44x_PCI0CFG_LO 0x0ec00000UL 90#define PPC44x_PCI0CFG_LO 0x0ec00000UL
@@ -109,7 +122,7 @@
109 */ 122 */
110 123
111 124
112/* CPRs (440GX and 440SP) */ 125/* CPRs (440GX and 440SP/440SPe) */
113#define DCRN_CPR_CONFIG_ADDR 0xc 126#define DCRN_CPR_CONFIG_ADDR 0xc
114#define DCRN_CPR_CONFIG_DATA 0xd 127#define DCRN_CPR_CONFIG_DATA 0xd
115 128
@@ -130,7 +143,7 @@
130 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \ 143 mtdcr(DCRN_CPR_CONFIG_ADDR, offset); \
131 mtdcr(DCRN_CPR_CONFIG_DATA, data);}) 144 mtdcr(DCRN_CPR_CONFIG_DATA, data);})
132 145
133/* SDRs (440GX and 440SP) */ 146/* SDRs (440GX and 440SP/440SPe) */
134#define DCRN_SDR_CONFIG_ADDR 0xe 147#define DCRN_SDR_CONFIG_ADDR 0xe
135#define DCRN_SDR_CONFIG_DATA 0xf 148#define DCRN_SDR_CONFIG_DATA 0xf
136#define DCRN_SDR_PFC0 0x4100 149#define DCRN_SDR_PFC0 0x4100
@@ -180,7 +193,7 @@
180 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \ 193 mtdcr(DCRN_SDR_CONFIG_ADDR, offset); \
181 mtdcr(DCRN_SDR_CONFIG_DATA,data);}) 194 mtdcr(DCRN_SDR_CONFIG_DATA,data);})
182 195
183/* DMA (excluding 440SP) */ 196/* DMA (excluding 440SP/440SPe) */
184#define DCRN_DMA0_BASE 0x100 197#define DCRN_DMA0_BASE 0x100
185#define DCRN_DMA1_BASE 0x108 198#define DCRN_DMA1_BASE 0x108
186#define DCRN_DMA2_BASE 0x110 199#define DCRN_DMA2_BASE 0x110
@@ -200,12 +213,20 @@
200/* UIC */ 213/* UIC */
201#define DCRN_UIC0_BASE 0xc0 214#define DCRN_UIC0_BASE 0xc0
202#define DCRN_UIC1_BASE 0xd0 215#define DCRN_UIC1_BASE 0xd0
203#define DCRN_UIC2_BASE 0x210
204#define DCRN_UICB_BASE 0x200
205#define UIC0 DCRN_UIC0_BASE 216#define UIC0 DCRN_UIC0_BASE
206#define UIC1 DCRN_UIC1_BASE 217#define UIC1 DCRN_UIC1_BASE
218
219#ifdef CONFIG_440SPE
220#define DCRN_UIC2_BASE 0xe0
221#define DCRN_UIC3_BASE 0xf0
222#define UIC2 DCRN_UIC2_BASE
223#define UIC3 DCRN_UIC3_BASE
224#else
225#define DCRN_UIC2_BASE 0x210
226#define DCRN_UICB_BASE 0x200
207#define UIC2 DCRN_UIC2_BASE 227#define UIC2 DCRN_UIC2_BASE
208#define UICB DCRN_UICB_BASE 228#define UICB DCRN_UICB_BASE
229#endif
209 230
210#define DCRN_UIC_SR(base) (base + 0x0) 231#define DCRN_UIC_SR(base) (base + 0x0)
211#define DCRN_UIC_ER(base) (base + 0x2) 232#define DCRN_UIC_ER(base) (base + 0x2)
@@ -218,6 +239,12 @@
218 239
219#define UIC0_UIC1NC 0x00000002 240#define UIC0_UIC1NC 0x00000002
220 241
242#ifdef CONFIG_440SPE
243#define UIC0_UIC1NC 0x00000002
244#define UIC0_UIC2NC 0x00200000
245#define UIC0_UIC3NC 0x00008000
246#endif
247
221#define UICB_UIC0NC 0x40000000 248#define UICB_UIC0NC 0x40000000
222#define UICB_UIC1NC 0x10000000 249#define UICB_UIC1NC 0x10000000
223#define UICB_UIC2NC 0x04000000 250#define UICB_UIC2NC 0x04000000
@@ -297,6 +324,23 @@
297#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ 324#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */
298#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ 325#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */
299 326
327#if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
328/* 440SP/440SPe PLB Arbiter DCRs */
329#define DCRN_PLB_REVID 0x080 /* PLB Revision ID */
330#define DCRN_PLB_CCR 0x088 /* PLB Crossbar Control */
331
332#define DCRN_PLB0_ACR 0x081 /* PLB Arbiter Control */
333#define DCRN_PLB0_BESRL 0x082 /* PLB Error Status */
334#define DCRN_PLB0_BESRH 0x083 /* PLB Error Status */
335#define DCRN_PLB0_BEARL 0x084 /* PLB Error Address Low */
336#define DCRN_PLB0_BEARH 0x085 /* PLB Error Address High */
337
338#define DCRN_PLB1_ACR 0x089 /* PLB Arbiter Control */
339#define DCRN_PLB1_BESRL 0x08a /* PLB Error Status */
340#define DCRN_PLB1_BESRH 0x08b /* PLB Error Status */
341#define DCRN_PLB1_BEARL 0x08c /* PLB Error Address Low */
342#define DCRN_PLB1_BEARH 0x08d /* PLB Error Address High */
343#else
300/* 440GP/GX PLB Arbiter DCRs */ 344/* 440GP/GX PLB Arbiter DCRs */
301#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */ 345#define DCRN_PLB0_REVID 0x082 /* PLB Arbiter Revision ID */
302#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */ 346#define DCRN_PLB0_ACR 0x083 /* PLB Arbiter Control */
@@ -304,6 +348,7 @@
304#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */ 348#define DCRN_PLB0_BEARL 0x086 /* PLB Error Address Low */
305#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */ 349#define DCRN_PLB0_BEAR DCRN_PLB0_BEARL /* 40x compatibility */
306#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */ 350#define DCRN_PLB0_BEARH 0x087 /* PLB Error Address High */
351#endif
307 352
308/* 440GP/GX PLB to OPB bridge DCRs */ 353/* 440GP/GX PLB to OPB bridge DCRs */
309#define DCRN_POB0_BESR0 0x090 354#define DCRN_POB0_BESR0 0x090
@@ -407,9 +452,13 @@
407#define PPC44x_MEM_SIZE_1G 0x40000000 452#define PPC44x_MEM_SIZE_1G 0x40000000
408#define PPC44x_MEM_SIZE_2G 0x80000000 453#define PPC44x_MEM_SIZE_2G 0x80000000
409 454
410/* 440SP memory controller DCRs */ 455/* 440SP/440SPe memory controller DCRs */
411#define DCRN_MQ0_BS0BAS 0x40 456#define DCRN_MQ0_BS0BAS 0x40
412#define DCRN_MQ0_BS1BAS 0x41 457#if defined(CONFIG_440SP)
458#define MQ0_NUM_BANKS 2
459#elif defined(CONFIG_440SPE)
460#define MQ0_NUM_BANKS 4
461#endif
413 462
414#define MQ0_CONFIG_SIZE_MASK 0x0000fff0 463#define MQ0_CONFIG_SIZE_MASK 0x0000fff0
415#define MQ0_CONFIG_SIZE_8M 0x0000ffc0 464#define MQ0_CONFIG_SIZE_8M 0x0000ffc0
@@ -421,8 +470,9 @@
421#define MQ0_CONFIG_SIZE_512M 0x0000f000 470#define MQ0_CONFIG_SIZE_512M 0x0000f000
422#define MQ0_CONFIG_SIZE_1G 0x0000e000 471#define MQ0_CONFIG_SIZE_1G 0x0000e000
423#define MQ0_CONFIG_SIZE_2G 0x0000c000 472#define MQ0_CONFIG_SIZE_2G 0x0000c000
473#define MQ0_CONFIG_SIZE_4G 0x00008000
424 474
425/* Internal SRAM Controller 440GX/440SP */ 475/* Internal SRAM Controller 440GX/440SP/440SPe */
426#define DCRN_SRAM0_BASE 0x000 476#define DCRN_SRAM0_BASE 0x000
427 477
428#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020) 478#define DCRN_SRAM0_SB0CR (DCRN_SRAM0_BASE + 0x020)
@@ -446,7 +496,7 @@
446#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a) 496#define DCRN_SRAM0_DPC (DCRN_SRAM0_BASE + 0x02a)
447#define SRAM_DPC_ENABLE 0x80000000 497#define SRAM_DPC_ENABLE 0x80000000
448 498
449/* L2 Cache Controller 440GX/440SP */ 499/* L2 Cache Controller 440GX/440SP/440SPe */
450#define DCRN_L2C0_CFG 0x030 500#define DCRN_L2C0_CFG 0x030
451#define L2C_CFG_L2M 0x80000000 501#define L2C_CFG_L2M 0x80000000
452#define L2C_CFG_ICU 0x40000000 502#define L2C_CFG_ICU 0x40000000
@@ -610,8 +660,10 @@
610#define IIC_CLOCK 50 660#define IIC_CLOCK 50
611 661
612#undef NR_UICS 662#undef NR_UICS
613#ifdef CONFIG_440GX 663#if defined(CONFIG_440GX)
614#define NR_UICS 3 664#define NR_UICS 3
665#elif defined(CONFIG_440SPE)
666#define NR_UICS 4
615#else 667#else
616#define NR_UICS 2 668#define NR_UICS 2
617#endif 669#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-25 18:03:50 -0500