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1/*
2 * MPC8xx Communication Processor Module.
3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
4 *
5 * This file contains structures and information for the communication
6 * processor channels. Some CPM control and status is available
7 * throught the MPC8xx internal memory map. See immap.h for details.
8 * This file only contains what I need for the moment, not the total
9 * CPM capabilities. I (or someone else) will add definitions as they
10 * are needed. -- Dan
11 *
12 * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
13 * bytes of the DP RAM and relocates the I2C parameter area to the
14 * IDMA1 space. The remaining DP RAM is available for buffer descriptors
15 * or other use.
16 */
17#ifndef __CPM_8XX__
18#define __CPM_8XX__
19
20#include <linux/config.h>
21#include <asm/8xx_immap.h>
22#include <asm/ptrace.h>
23
24/* CPM Command register.
25*/
26#define CPM_CR_RST ((ushort)0x8000)
27#define CPM_CR_OPCODE ((ushort)0x0f00)
28#define CPM_CR_CHAN ((ushort)0x00f0)
29#define CPM_CR_FLG ((ushort)0x0001)
30
31/* Some commands (there are more...later)
32*/
33#define CPM_CR_INIT_TRX ((ushort)0x0000)
34#define CPM_CR_INIT_RX ((ushort)0x0001)
35#define CPM_CR_INIT_TX ((ushort)0x0002)
36#define CPM_CR_HUNT_MODE ((ushort)0x0003)
37#define CPM_CR_STOP_TX ((ushort)0x0004)
38#define CPM_CR_RESTART_TX ((ushort)0x0006)
39#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
40#define CPM_CR_SET_GADDR ((ushort)0x0008)
41#define CPM_CR_SET_TIMER CPM_CR_SET_GADDR
42
43/* Channel numbers.
44*/
45#define CPM_CR_CH_SCC1 ((ushort)0x0000)
46#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
47#define CPM_CR_CH_SCC2 ((ushort)0x0004)
48#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
49#define CPM_CR_CH_TIMER CPM_CR_CH_SPI
50#define CPM_CR_CH_SCC3 ((ushort)0x0008)
51#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
52#define CPM_CR_CH_SCC4 ((ushort)0x000c)
53#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
54
55#define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
56
57/* The dual ported RAM is multi-functional. Some areas can be (and are
58 * being) used for microcode. There is an area that can only be used
59 * as data ram for buffer descriptors, which is all we use right now.
60 * Currently the first 512 and last 256 bytes are used for microcode.
61 */
62#define CPM_DATAONLY_BASE ((uint)0x0800)
63#define CPM_DATAONLY_SIZE ((uint)0x0700)
64#define CPM_DP_NOSPACE ((uint)0x7fffffff)
65
66static inline long IS_DPERR(const uint offset)
67{
68 return (uint)offset > (uint)-1000L;
69}
70
71/* Export the base address of the communication processor registers
72 * and dual port ram.
73 */
74extern cpm8xx_t *cpmp; /* Pointer to comm processor */
75extern uint cpm_dpalloc(uint size, uint align);
76extern int cpm_dpfree(uint offset);
77extern uint cpm_dpalloc_fixed(uint offset, uint size, uint align);
78extern void cpm_dpdump(void);
79extern void *cpm_dpram_addr(uint offset);
80extern void cpm_setbrg(uint brg, uint rate);
81
82extern uint m8xx_cpm_hostalloc(uint size);
83extern int m8xx_cpm_hostfree(uint start);
84extern void m8xx_cpm_hostdump(void);
85
86/* Buffer descriptors used by many of the CPM protocols.
87*/
88typedef struct cpm_buf_desc {
89 ushort cbd_sc; /* Status and Control */
90 ushort cbd_datlen; /* Data length in buffer */
91 uint cbd_bufaddr; /* Buffer address in host memory */
92} cbd_t;
93
94#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */
95#define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */
96#define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */
97#define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */
98#define BD_SC_LAST ((ushort)0x0800) /* Last buffer in frame */
99#define BD_SC_TC ((ushort)0x0400) /* Transmit CRC */
100#define BD_SC_CM ((ushort)0x0200) /* Continous mode */
101#define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */
102#define BD_SC_P ((ushort)0x0100) /* xmt preamble */
103#define BD_SC_BR ((ushort)0x0020) /* Break received */
104#define BD_SC_FR ((ushort)0x0010) /* Framing error */
105#define BD_SC_PR ((ushort)0x0008) /* Parity error */
106#define BD_SC_NAK ((ushort)0x0004) /* NAK - did not respond */
107#define BD_SC_OV ((ushort)0x0002) /* Overrun */
108#define BD_SC_UN ((ushort)0x0002) /* Underrun */
109#define BD_SC_CD ((ushort)0x0001) /* ?? */
110#define BD_SC_CL ((ushort)0x0001) /* Collision */
111
112/* Parameter RAM offsets.
113*/
114#define PROFF_SCC1 ((uint)0x0000)
115#define PROFF_IIC ((uint)0x0080)
116#define PROFF_SCC2 ((uint)0x0100)
117#define PROFF_SPI ((uint)0x0180)
118#define PROFF_SCC3 ((uint)0x0200)
119#define PROFF_SMC1 ((uint)0x0280)
120#define PROFF_SCC4 ((uint)0x0300)
121#define PROFF_SMC2 ((uint)0x0380)
122
123/* Define enough so I can at least use the serial port as a UART.
124 * The MBX uses SMC1 as the host serial port.
125 */
126typedef struct smc_uart {
127 ushort smc_rbase; /* Rx Buffer descriptor base address */
128 ushort smc_tbase; /* Tx Buffer descriptor base address */
129 u_char smc_rfcr; /* Rx function code */
130 u_char smc_tfcr; /* Tx function code */
131 ushort smc_mrblr; /* Max receive buffer length */
132 uint smc_rstate; /* Internal */
133 uint smc_idp; /* Internal */
134 ushort smc_rbptr; /* Internal */
135 ushort smc_ibc; /* Internal */
136 uint smc_rxtmp; /* Internal */
137 uint smc_tstate; /* Internal */
138 uint smc_tdp; /* Internal */
139 ushort smc_tbptr; /* Internal */
140 ushort smc_tbc; /* Internal */
141 uint smc_txtmp; /* Internal */
142 ushort smc_maxidl; /* Maximum idle characters */
143 ushort smc_tmpidl; /* Temporary idle counter */
144 ushort smc_brklen; /* Last received break length */
145 ushort smc_brkec; /* rcv'd break condition counter */
146 ushort smc_brkcr; /* xmt break count register */
147 ushort smc_rmask; /* Temporary bit mask */
148 char res1[8]; /* Reserved */
149 ushort smc_rpbase; /* Relocation pointer */
150} smc_uart_t;
151
152/* Function code bits.
153*/
154#define SMC_EB ((u_char)0x10) /* Set big endian byte order */
155
156/* SMC uart mode register.
157*/
158#define SMCMR_REN ((ushort)0x0001)
159#define SMCMR_TEN ((ushort)0x0002)
160#define SMCMR_DM ((ushort)0x000c)
161#define SMCMR_SM_GCI ((ushort)0x0000)
162#define SMCMR_SM_UART ((ushort)0x0020)
163#define SMCMR_SM_TRANS ((ushort)0x0030)
164#define SMCMR_SM_MASK ((ushort)0x0030)
165#define SMCMR_PM_EVEN ((ushort)0x0100) /* Even parity, else odd */
166#define SMCMR_REVD SMCMR_PM_EVEN
167#define SMCMR_PEN ((ushort)0x0200) /* Parity enable */
168#define SMCMR_BS SMCMR_PEN
169#define SMCMR_SL ((ushort)0x0400) /* Two stops, else one */
170#define SMCR_CLEN_MASK ((ushort)0x7800) /* Character length */
171#define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
172
173/* SMC2 as Centronics parallel printer. It is half duplex, in that
174 * it can only receive or transmit. The parameter ram values for
175 * each direction are either unique or properly overlap, so we can
176 * include them in one structure.
177 */
178typedef struct smc_centronics {
179 ushort scent_rbase;
180 ushort scent_tbase;
181 u_char scent_cfcr;
182 u_char scent_smask;
183 ushort scent_mrblr;
184 uint scent_rstate;
185 uint scent_r_ptr;
186 ushort scent_rbptr;
187 ushort scent_r_cnt;
188 uint scent_rtemp;
189 uint scent_tstate;
190 uint scent_t_ptr;
191 ushort scent_tbptr;
192 ushort scent_t_cnt;
193 uint scent_ttemp;
194 ushort scent_max_sl;
195 ushort scent_sl_cnt;
196 ushort scent_character1;
197 ushort scent_character2;
198 ushort scent_character3;
199 ushort scent_character4;
200 ushort scent_character5;
201 ushort scent_character6;
202 ushort scent_character7;
203 ushort scent_character8;
204 ushort scent_rccm;
205 ushort scent_rccr;
206} smc_cent_t;
207
208/* Centronics Status Mask Register.
209*/
210#define SMC_CENT_F ((u_char)0x08)
211#define SMC_CENT_PE ((u_char)0x04)
212#define SMC_CENT_S ((u_char)0x02)
213
214/* SMC Event and Mask register.
215*/
216#define SMCM_BRKE ((unsigned char)0x40) /* When in UART Mode */
217#define SMCM_BRK ((unsigned char)0x10) /* When in UART Mode */
218#define SMCM_TXE ((unsigned char)0x10) /* When in Transparent Mode */
219#define SMCM_BSY ((unsigned char)0x04)
220#define SMCM_TX ((unsigned char)0x02)
221#define SMCM_RX ((unsigned char)0x01)
222
223/* Baud rate generators.
224*/
225#define CPM_BRG_RST ((uint)0x00020000)
226#define CPM_BRG_EN ((uint)0x00010000)
227#define CPM_BRG_EXTC_INT ((uint)0x00000000)
228#define CPM_BRG_EXTC_CLK2 ((uint)0x00004000)
229#define CPM_BRG_EXTC_CLK6 ((uint)0x00008000)
230#define CPM_BRG_ATB ((uint)0x00002000)
231#define CPM_BRG_CD_MASK ((uint)0x00001ffe)
232#define CPM_BRG_DIV16 ((uint)0x00000001)
233
234/* SI Clock Route Register
235*/
236#define SICR_RCLK_SCC1_BRG1 ((uint)0x00000000)
237#define SICR_TCLK_SCC1_BRG1 ((uint)0x00000000)
238#define SICR_RCLK_SCC2_BRG2 ((uint)0x00000800)
239#define SICR_TCLK_SCC2_BRG2 ((uint)0x00000100)
240#define SICR_RCLK_SCC3_BRG3 ((uint)0x00100000)
241#define SICR_TCLK_SCC3_BRG3 ((uint)0x00020000)
242#define SICR_RCLK_SCC4_BRG4 ((uint)0x18000000)
243#define SICR_TCLK_SCC4_BRG4 ((uint)0x03000000)
244
245/* SCCs.
246*/
247#define SCC_GSMRH_IRP ((uint)0x00040000)
248#define SCC_GSMRH_GDE ((uint)0x00010000)
249#define SCC_GSMRH_TCRC_CCITT ((uint)0x00008000)
250#define SCC_GSMRH_TCRC_BISYNC ((uint)0x00004000)
251#define SCC_GSMRH_TCRC_HDLC ((uint)0x00000000)
252#define SCC_GSMRH_REVD ((uint)0x00002000)
253#define SCC_GSMRH_TRX ((uint)0x00001000)
254#define SCC_GSMRH_TTX ((uint)0x00000800)
255#define SCC_GSMRH_CDP ((uint)0x00000400)
256#define SCC_GSMRH_CTSP ((uint)0x00000200)
257#define SCC_GSMRH_CDS ((uint)0x00000100)
258#define SCC_GSMRH_CTSS ((uint)0x00000080)
259#define SCC_GSMRH_TFL ((uint)0x00000040)
260#define SCC_GSMRH_RFW ((uint)0x00000020)
261#define SCC_GSMRH_TXSY ((uint)0x00000010)
262#define SCC_GSMRH_SYNL16 ((uint)0x0000000c)
263#define SCC_GSMRH_SYNL8 ((uint)0x00000008)
264#define SCC_GSMRH_SYNL4 ((uint)0x00000004)
265#define SCC_GSMRH_RTSM ((uint)0x00000002)
266#define SCC_GSMRH_RSYN ((uint)0x00000001)
267
268#define SCC_GSMRL_SIR ((uint)0x80000000) /* SCC2 only */
269#define SCC_GSMRL_EDGE_NONE ((uint)0x60000000)
270#define SCC_GSMRL_EDGE_NEG ((uint)0x40000000)
271#define SCC_GSMRL_EDGE_POS ((uint)0x20000000)
272#define SCC_GSMRL_EDGE_BOTH ((uint)0x00000000)
273#define SCC_GSMRL_TCI ((uint)0x10000000)
274#define SCC_GSMRL_TSNC_3 ((uint)0x0c000000)
275#define SCC_GSMRL_TSNC_4 ((uint)0x08000000)
276#define SCC_GSMRL_TSNC_14 ((uint)0x04000000)
277#define SCC_GSMRL_TSNC_INF ((uint)0x00000000)
278#define SCC_GSMRL_RINV ((uint)0x02000000)
279#define SCC_GSMRL_TINV ((uint)0x01000000)
280#define SCC_GSMRL_TPL_128 ((uint)0x00c00000)
281#define SCC_GSMRL_TPL_64 ((uint)0x00a00000)
282#define SCC_GSMRL_TPL_48 ((uint)0x00800000)
283#define SCC_GSMRL_TPL_32 ((uint)0x00600000)
284#define SCC_GSMRL_TPL_16 ((uint)0x00400000)
285#define SCC_GSMRL_TPL_8 ((uint)0x00200000)
286#define SCC_GSMRL_TPL_NONE ((uint)0x00000000)
287#define SCC_GSMRL_TPP_ALL1 ((uint)0x00180000)
288#define SCC_GSMRL_TPP_01 ((uint)0x00100000)
289#define SCC_GSMRL_TPP_10 ((uint)0x00080000)
290#define SCC_GSMRL_TPP_ZEROS ((uint)0x00000000)
291#define SCC_GSMRL_TEND ((uint)0x00040000)
292#define SCC_GSMRL_TDCR_32 ((uint)0x00030000)
293#define SCC_GSMRL_TDCR_16 ((uint)0x00020000)
294#define SCC_GSMRL_TDCR_8 ((uint)0x00010000)
295#define SCC_GSMRL_TDCR_1 ((uint)0x00000000)
296#define SCC_GSMRL_RDCR_32 ((uint)0x0000c000)
297#define SCC_GSMRL_RDCR_16 ((uint)0x00008000)
298#define SCC_GSMRL_RDCR_8 ((uint)0x00004000)
299#define SCC_GSMRL_RDCR_1 ((uint)0x00000000)
300#define SCC_GSMRL_RENC_DFMAN ((uint)0x00003000)
301#define SCC_GSMRL_RENC_MANCH ((uint)0x00002000)
302#define SCC_GSMRL_RENC_FM0 ((uint)0x00001000)
303#define SCC_GSMRL_RENC_NRZI ((uint)0x00000800)
304#define SCC_GSMRL_RENC_NRZ ((uint)0x00000000)
305#define SCC_GSMRL_TENC_DFMAN ((uint)0x00000600)
306#define SCC_GSMRL_TENC_MANCH ((uint)0x00000400)
307#define SCC_GSMRL_TENC_FM0 ((uint)0x00000200)
308#define SCC_GSMRL_TENC_NRZI ((uint)0x00000100)
309#define SCC_GSMRL_TENC_NRZ ((uint)0x00000000)
310#define SCC_GSMRL_DIAG_LE ((uint)0x000000c0) /* Loop and echo */
311#define SCC_GSMRL_DIAG_ECHO ((uint)0x00000080)
312#define SCC_GSMRL_DIAG_LOOP ((uint)0x00000040)
313#define SCC_GSMRL_DIAG_NORM ((uint)0x00000000)
314#define SCC_GSMRL_ENR ((uint)0x00000020)
315#define SCC_GSMRL_ENT ((uint)0x00000010)
316#define SCC_GSMRL_MODE_ENET ((uint)0x0000000c)
317#define SCC_GSMRL_MODE_QMC ((uint)0x0000000a)
318#define SCC_GSMRL_MODE_DDCMP ((uint)0x00000009)
319#define SCC_GSMRL_MODE_BISYNC ((uint)0x00000008)
320#define SCC_GSMRL_MODE_V14 ((uint)0x00000007)
321#define SCC_GSMRL_MODE_AHDLC ((uint)0x00000006)
322#define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
323#define SCC_GSMRL_MODE_UART ((uint)0x00000004)
324#define SCC_GSMRL_MODE_SS7 ((uint)0x00000003)
325#define SCC_GSMRL_MODE_ATALK ((uint)0x00000002)
326#define SCC_GSMRL_MODE_HDLC ((uint)0x00000000)
327
328#define SCC_TODR_TOD ((ushort)0x8000)
329
330/* SCC Event and Mask register.
331*/
332#define SCCM_TXE ((unsigned char)0x10)
333#define SCCM_BSY ((unsigned char)0x04)
334#define SCCM_TX ((unsigned char)0x02)
335#define SCCM_RX ((unsigned char)0x01)
336
337typedef struct scc_param {
338 ushort scc_rbase; /* Rx Buffer descriptor base address */
339 ushort scc_tbase; /* Tx Buffer descriptor base address */
340 u_char scc_rfcr; /* Rx function code */
341 u_char scc_tfcr; /* Tx function code */
342 ushort scc_mrblr; /* Max receive buffer length */
343 uint scc_rstate; /* Internal */
344 uint scc_idp; /* Internal */
345 ushort scc_rbptr; /* Internal */
346 ushort scc_ibc; /* Internal */
347 uint scc_rxtmp; /* Internal */
348 uint scc_tstate; /* Internal */
349 uint scc_tdp; /* Internal */
350 ushort scc_tbptr; /* Internal */
351 ushort scc_tbc; /* Internal */
352 uint scc_txtmp; /* Internal */
353 uint scc_rcrc; /* Internal */
354 uint scc_tcrc; /* Internal */
355} sccp_t;
356
357/* Function code bits.
358*/
359#define SCC_EB ((u_char)0x10) /* Set big endian byte order */
360
361/* CPM Ethernet through SCCx.
362 */
363typedef struct scc_enet {
364 sccp_t sen_genscc;
365 uint sen_cpres; /* Preset CRC */
366 uint sen_cmask; /* Constant mask for CRC */
367 uint sen_crcec; /* CRC Error counter */
368 uint sen_alec; /* alignment error counter */
369 uint sen_disfc; /* discard frame counter */
370 ushort sen_pads; /* Tx short frame pad character */
371 ushort sen_retlim; /* Retry limit threshold */
372 ushort sen_retcnt; /* Retry limit counter */
373 ushort sen_maxflr; /* maximum frame length register */
374 ushort sen_minflr; /* minimum frame length register */
375 ushort sen_maxd1; /* maximum DMA1 length */
376 ushort sen_maxd2; /* maximum DMA2 length */
377 ushort sen_maxd; /* Rx max DMA */
378 ushort sen_dmacnt; /* Rx DMA counter */
379 ushort sen_maxb; /* Max BD byte count */
380 ushort sen_gaddr1; /* Group address filter */
381 ushort sen_gaddr2;
382 ushort sen_gaddr3;
383 ushort sen_gaddr4;
384 uint sen_tbuf0data0; /* Save area 0 - current frame */
385 uint sen_tbuf0data1; /* Save area 1 - current frame */
386 uint sen_tbuf0rba; /* Internal */
387 uint sen_tbuf0crc; /* Internal */
388 ushort sen_tbuf0bcnt; /* Internal */
389 ushort sen_paddrh; /* physical address (MSB) */
390 ushort sen_paddrm;
391 ushort sen_paddrl; /* physical address (LSB) */
392 ushort sen_pper; /* persistence */
393 ushort sen_rfbdptr; /* Rx first BD pointer */
394 ushort sen_tfbdptr; /* Tx first BD pointer */
395 ushort sen_tlbdptr; /* Tx last BD pointer */
396 uint sen_tbuf1data0; /* Save area 0 - current frame */
397 uint sen_tbuf1data1; /* Save area 1 - current frame */
398 uint sen_tbuf1rba; /* Internal */
399 uint sen_tbuf1crc; /* Internal */
400 ushort sen_tbuf1bcnt; /* Internal */
401 ushort sen_txlen; /* Tx Frame length counter */
402 ushort sen_iaddr1; /* Individual address filter */
403 ushort sen_iaddr2;
404 ushort sen_iaddr3;
405 ushort sen_iaddr4;
406 ushort sen_boffcnt; /* Backoff counter */
407
408 /* NOTE: Some versions of the manual have the following items
409 * incorrectly documented. Below is the proper order.
410 */
411 ushort sen_taddrh; /* temp address (MSB) */
412 ushort sen_taddrm;
413 ushort sen_taddrl; /* temp address (LSB) */
414} scc_enet_t;
415
416/* SCC Event register as used by Ethernet.
417*/
418#define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */
419#define SCCE_ENET_TXE ((ushort)0x0010) /* Transmit Error */
420#define SCCE_ENET_RXF ((ushort)0x0008) /* Full frame received */
421#define SCCE_ENET_BSY ((ushort)0x0004) /* All incoming buffers full */
422#define SCCE_ENET_TXB ((ushort)0x0002) /* A buffer was transmitted */
423#define SCCE_ENET_RXB ((ushort)0x0001) /* A buffer was received */
424
425/* SCC Mode Register (PMSR) as used by Ethernet.
426*/
427#define SCC_PSMR_HBC ((ushort)0x8000) /* Enable heartbeat */
428#define SCC_PSMR_FC ((ushort)0x4000) /* Force collision */
429#define SCC_PSMR_RSH ((ushort)0x2000) /* Receive short frames */
430#define SCC_PSMR_IAM ((ushort)0x1000) /* Check individual hash */
431#define SCC_PSMR_ENCRC ((ushort)0x0800) /* Ethernet CRC mode */
432#define SCC_PSMR_PRO ((ushort)0x0200) /* Promiscuous mode */
433#define SCC_PSMR_BRO ((ushort)0x0100) /* Catch broadcast pkts */
434#define SCC_PSMR_SBT ((ushort)0x0080) /* Special backoff timer */
435#define SCC_PSMR_LPB ((ushort)0x0040) /* Set Loopback mode */
436#define SCC_PSMR_SIP ((ushort)0x0020) /* Sample Input Pins */
437#define SCC_PSMR_LCW ((ushort)0x0010) /* Late collision window */
438#define SCC_PSMR_NIB22 ((ushort)0x000a) /* Start frame search */
439#define SCC_PSMR_FDE ((ushort)0x0001) /* Full duplex enable */
440
441/* Buffer descriptor control/status used by Ethernet receive.
442*/
443#define BD_ENET_RX_EMPTY ((ushort)0x8000)
444#define BD_ENET_RX_WRAP ((ushort)0x2000)
445#define BD_ENET_RX_INTR ((ushort)0x1000)
446#define BD_ENET_RX_LAST ((ushort)0x0800)
447#define BD_ENET_RX_FIRST ((ushort)0x0400)
448#define BD_ENET_RX_MISS ((ushort)0x0100)
449#define BD_ENET_RX_LG ((ushort)0x0020)
450#define BD_ENET_RX_NO ((ushort)0x0010)
451#define BD_ENET_RX_SH ((ushort)0x0008)
452#define BD_ENET_RX_CR ((ushort)0x0004)
453#define BD_ENET_RX_OV ((ushort)0x0002)
454#define BD_ENET_RX_CL ((ushort)0x0001)
455#define BD_ENET_RX_BC ((ushort)0x0080) /* DA is Broadcast */
456#define BD_ENET_RX_MC ((ushort)0x0040) /* DA is Multicast */
457#define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */
458
459/* Buffer descriptor control/status used by Ethernet transmit.
460*/
461#define BD_ENET_TX_READY ((ushort)0x8000)
462#define BD_ENET_TX_PAD ((ushort)0x4000)
463#define BD_ENET_TX_WRAP ((ushort)0x2000)
464#define BD_ENET_TX_INTR ((ushort)0x1000)
465#define BD_ENET_TX_LAST ((ushort)0x0800)
466#define BD_ENET_TX_TC ((ushort)0x0400)
467#define BD_ENET_TX_DEF ((ushort)0x0200)
468#define BD_ENET_TX_HB ((ushort)0x0100)
469#define BD_ENET_TX_LC ((ushort)0x0080)
470#define BD_ENET_TX_RL ((ushort)0x0040)
471#define BD_ENET_TX_RCMASK ((ushort)0x003c)
472#define BD_ENET_TX_UN ((ushort)0x0002)
473#define BD_ENET_TX_CSL ((ushort)0x0001)
474#define BD_ENET_TX_STATS ((ushort)0x03ff) /* All status bits */
475
476/* SCC as UART
477*/
478typedef struct scc_uart {
479 sccp_t scc_genscc;
480 char res1[8]; /* Reserved */
481 ushort scc_maxidl; /* Maximum idle chars */
482 ushort scc_idlc; /* temp idle counter */
483 ushort scc_brkcr; /* Break count register */
484 ushort scc_parec; /* receive parity error counter */
485 ushort scc_frmec; /* receive framing error counter */
486 ushort scc_nosec; /* receive noise counter */
487 ushort scc_brkec; /* receive break condition counter */
488 ushort scc_brkln; /* last received break length */
489 ushort scc_uaddr1; /* UART address character 1 */
490 ushort scc_uaddr2; /* UART address character 2 */
491 ushort scc_rtemp; /* Temp storage */
492 ushort scc_toseq; /* Transmit out of sequence char */
493 ushort scc_char1; /* control character 1 */
494 ushort scc_char2; /* control character 2 */
495 ushort scc_char3; /* control character 3 */
496 ushort scc_char4; /* control character 4 */
497 ushort scc_char5; /* control character 5 */
498 ushort scc_char6; /* control character 6 */
499 ushort scc_char7; /* control character 7 */
500 ushort scc_char8; /* control character 8 */
501 ushort scc_rccm; /* receive control character mask */
502 ushort scc_rccr; /* receive control character register */
503 ushort scc_rlbc; /* receive last break character */
504} scc_uart_t;
505
506/* SCC Event and Mask registers when it is used as a UART.
507*/
508#define UART_SCCM_GLR ((ushort)0x1000)
509#define UART_SCCM_GLT ((ushort)0x0800)
510#define UART_SCCM_AB ((ushort)0x0200)
511#define UART_SCCM_IDL ((ushort)0x0100)
512#define UART_SCCM_GRA ((ushort)0x0080)
513#define UART_SCCM_BRKE ((ushort)0x0040)
514#define UART_SCCM_BRKS ((ushort)0x0020)
515#define UART_SCCM_CCR ((ushort)0x0008)
516#define UART_SCCM_BSY ((ushort)0x0004)
517#define UART_SCCM_TX ((ushort)0x0002)
518#define UART_SCCM_RX ((ushort)0x0001)
519
520/* The SCC PMSR when used as a UART.
521*/
522#define SCU_PSMR_FLC ((ushort)0x8000)
523#define SCU_PSMR_SL ((ushort)0x4000)
524#define SCU_PSMR_CL ((ushort)0x3000)
525#define SCU_PSMR_UM ((ushort)0x0c00)
526#define SCU_PSMR_FRZ ((ushort)0x0200)
527#define SCU_PSMR_RZS ((ushort)0x0100)
528#define SCU_PSMR_SYN ((ushort)0x0080)
529#define SCU_PSMR_DRT ((ushort)0x0040)
530#define SCU_PSMR_PEN ((ushort)0x0010)
531#define SCU_PSMR_RPM ((ushort)0x000c)
532#define SCU_PSMR_REVP ((ushort)0x0008)
533#define SCU_PSMR_TPM ((ushort)0x0003)
534#define SCU_PSMR_TEVP ((ushort)0x0002)
535
536/* CPM Transparent mode SCC.
537 */
538typedef struct scc_trans {
539 sccp_t st_genscc;
540 uint st_cpres; /* Preset CRC */
541 uint st_cmask; /* Constant mask for CRC */
542} scc_trans_t;
543
544#define BD_SCC_TX_LAST ((ushort)0x0800)
545
546/* IIC parameter RAM.
547*/
548typedef struct iic {
549 ushort iic_rbase; /* Rx Buffer descriptor base address */
550 ushort iic_tbase; /* Tx Buffer descriptor base address */
551 u_char iic_rfcr; /* Rx function code */
552 u_char iic_tfcr; /* Tx function code */
553 ushort iic_mrblr; /* Max receive buffer length */
554 uint iic_rstate; /* Internal */
555 uint iic_rdp; /* Internal */
556 ushort iic_rbptr; /* Internal */
557 ushort iic_rbc; /* Internal */
558 uint iic_rxtmp; /* Internal */
559 uint iic_tstate; /* Internal */
560 uint iic_tdp; /* Internal */
561 ushort iic_tbptr; /* Internal */
562 ushort iic_tbc; /* Internal */
563 uint iic_txtmp; /* Internal */
564 char res1[4]; /* Reserved */
565 ushort iic_rpbase; /* Relocation pointer */
566 char res2[2]; /* Reserved */
567} iic_t;
568
569#define BD_IIC_START ((ushort)0x0400)
570
571/* SPI parameter RAM.
572*/
573typedef struct spi {
574 ushort spi_rbase; /* Rx Buffer descriptor base address */
575 ushort spi_tbase; /* Tx Buffer descriptor base address */
576 u_char spi_rfcr; /* Rx function code */
577 u_char spi_tfcr; /* Tx function code */
578 ushort spi_mrblr; /* Max receive buffer length */
579 uint spi_rstate; /* Internal */
580 uint spi_rdp; /* Internal */
581 ushort spi_rbptr; /* Internal */
582 ushort spi_rbc; /* Internal */
583 uint spi_rxtmp; /* Internal */
584 uint spi_tstate; /* Internal */
585 uint spi_tdp; /* Internal */
586 ushort spi_tbptr; /* Internal */
587 ushort spi_tbc; /* Internal */
588 uint spi_txtmp; /* Internal */
589 uint spi_res;
590 ushort spi_rpbase; /* Relocation pointer */
591 ushort spi_res2;
592} spi_t;
593
594/* SPI Mode register.
595*/
596#define SPMODE_LOOP ((ushort)0x4000) /* Loopback */
597#define SPMODE_CI ((ushort)0x2000) /* Clock Invert */
598#define SPMODE_CP ((ushort)0x1000) /* Clock Phase */
599#define SPMODE_DIV16 ((ushort)0x0800) /* BRG/16 mode */
600#define SPMODE_REV ((ushort)0x0400) /* Reversed Data */
601#define SPMODE_MSTR ((ushort)0x0200) /* SPI Master */
602#define SPMODE_EN ((ushort)0x0100) /* Enable */
603#define SPMODE_LENMSK ((ushort)0x00f0) /* character length */
604#define SPMODE_LEN4 ((ushort)0x0030) /* 4 bits per char */
605#define SPMODE_LEN8 ((ushort)0x0070) /* 8 bits per char */
606#define SPMODE_LEN16 ((ushort)0x00f0) /* 16 bits per char */
607#define SPMODE_PMMSK ((ushort)0x000f) /* prescale modulus */
608
609/* SPIE fields */
610#define SPIE_MME 0x20
611#define SPIE_TXE 0x10
612#define SPIE_BSY 0x04
613#define SPIE_TXB 0x02
614#define SPIE_RXB 0x01
615
616/*
617 * RISC Controller Configuration Register definitons
618 */
619#define RCCR_TIME 0x8000 /* RISC Timer Enable */
620#define RCCR_TIMEP(t) (((t) & 0x3F)<<8) /* RISC Timer Period */
621#define RCCR_TIME_MASK 0x00FF /* not RISC Timer related bits */
622
623/* RISC Timer Parameter RAM offset */
624#define PROFF_RTMR ((uint)0x01B0)
625
626typedef struct risc_timer_pram {
627 unsigned short tm_base; /* RISC Timer Table Base Address */
628 unsigned short tm_ptr; /* RISC Timer Table Pointer (internal) */
629 unsigned short r_tmr; /* RISC Timer Mode Register */
630 unsigned short r_tmv; /* RISC Timer Valid Register */
631 unsigned long tm_cmd; /* RISC Timer Command Register */
632 unsigned long tm_cnt; /* RISC Timer Internal Count */
633} rt_pram_t;
634
635/* Bits in RISC Timer Command Register */
636#define TM_CMD_VALID 0x80000000 /* Valid - Enables the timer */
637#define TM_CMD_RESTART 0x40000000 /* Restart - for automatic restart */
638#define TM_CMD_PWM 0x20000000 /* Run in Pulse Width Modulation Mode */
639#define TM_CMD_NUM(n) (((n)&0xF)<<16) /* Timer Number */
640#define TM_CMD_PERIOD(p) ((p)&0xFFFF) /* Timer Period */
641
642/* CPM interrupts. There are nearly 32 interrupts generated by CPM
643 * channels or devices. All of these are presented to the PPC core
644 * as a single interrupt. The CPM interrupt handler dispatches its
645 * own handlers, in a similar fashion to the PPC core handler. We
646 * use the table as defined in the manuals (i.e. no special high
647 * priority and SCC1 == SCCa, etc...).
648 */
649#define CPMVEC_NR 32
650#define CPMVEC_PIO_PC15 ((ushort)0x1f)
651#define CPMVEC_SCC1 ((ushort)0x1e)
652#define CPMVEC_SCC2 ((ushort)0x1d)
653#define CPMVEC_SCC3 ((ushort)0x1c)
654#define CPMVEC_SCC4 ((ushort)0x1b)
655#define CPMVEC_PIO_PC14 ((ushort)0x1a)
656#define CPMVEC_TIMER1 ((ushort)0x19)
657#define CPMVEC_PIO_PC13 ((ushort)0x18)
658#define CPMVEC_PIO_PC12 ((ushort)0x17)
659#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
660#define CPMVEC_IDMA1 ((ushort)0x15)
661#define CPMVEC_IDMA2 ((ushort)0x14)
662#define CPMVEC_TIMER2 ((ushort)0x12)
663#define CPMVEC_RISCTIMER ((ushort)0x11)
664#define CPMVEC_I2C ((ushort)0x10)
665#define CPMVEC_PIO_PC11 ((ushort)0x0f)
666#define CPMVEC_PIO_PC10 ((ushort)0x0e)
667#define CPMVEC_TIMER3 ((ushort)0x0c)
668#define CPMVEC_PIO_PC9 ((ushort)0x0b)
669#define CPMVEC_PIO_PC8 ((ushort)0x0a)
670#define CPMVEC_PIO_PC7 ((ushort)0x09)
671#define CPMVEC_TIMER4 ((ushort)0x07)
672#define CPMVEC_PIO_PC6 ((ushort)0x06)
673#define CPMVEC_SPI ((ushort)0x05)
674#define CPMVEC_SMC1 ((ushort)0x04)
675#define CPMVEC_SMC2 ((ushort)0x03)
676#define CPMVEC_PIO_PC5 ((ushort)0x02)
677#define CPMVEC_PIO_PC4 ((ushort)0x01)
678#define CPMVEC_ERROR ((ushort)0x00)
679
680/* CPM interrupt configuration vector.
681*/
682#define CICR_SCD_SCC4 ((uint)0x00c00000) /* SCC4 @ SCCd */
683#define CICR_SCC_SCC3 ((uint)0x00200000) /* SCC3 @ SCCc */
684#define CICR_SCB_SCC2 ((uint)0x00040000) /* SCC2 @ SCCb */
685#define CICR_SCA_SCC1 ((uint)0x00000000) /* SCC1 @ SCCa */
686#define CICR_IRL_MASK ((uint)0x0000e000) /* Core interrrupt */
687#define CICR_HP_MASK ((uint)0x00001f00) /* Hi-pri int. */
688#define CICR_IEN ((uint)0x00000080) /* Int. enable */
689#define CICR_SPS ((uint)0x00000001) /* SCC Spread */
690
691extern void cpm_install_handler(int vec,
692 void (*handler)(void *, struct pt_regs *regs), void *dev_id);
693extern void cpm_free_handler(int vec);
694
695#endif /* __CPM_8XX__ */
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