58 files changed, 2299 insertions, 424 deletions

diff --git a/include/asm-powerpc/backlight.h b/include/asm-powerpc/backlight.h
index 1ba1f27a0b63..a5e9e656e332 100644
--- a/include/asm-powerpc/backlight.h
+++ b/include/asm-powerpc/backlight.h
@@ -2,30 +2,30 @@
  * Routines for handling backlight control on PowerBooks
  *
  * For now, implementation resides in
- * arch/powerpc/platforms/powermac/pmac_support.c
+ * arch/powerpc/platforms/powermac/backlight.c
  *
  */
 #ifndef __ASM_POWERPC_BACKLIGHT_H
 #define __ASM_POWERPC_BACKLIGHT_H
 #ifdef __KERNEL__
 
-/* Abstract values */
-#define BACKLIGHT_OFF   0
-#define BACKLIGHT_MIN   1
-#define BACKLIGHT_MAX   0xf
+#include <linux/fb.h>
+#include <linux/mutex.h>
 
-struct backlight_controller {
-        int (*set_enable)(int enable, int level, void *data);
-        int (*set_level)(int level, void *data);
-};
+/* For locking instructions, see the implementation file */
+extern struct backlight_device *pmac_backlight;
+extern struct mutex pmac_backlight_mutex;
 
-extern void register_backlight_controller(struct backlight_controller *ctrler, void *data, char *type);
-extern void unregister_backlight_controller(struct backlight_controller *ctrler, void *data);
+extern void pmac_backlight_calc_curve(struct fb_info*);
+extern int pmac_backlight_curve_lookup(struct fb_info *info, int value);
 
-extern int set_backlight_enable(int enable);
-extern int get_backlight_enable(void);
-extern int set_backlight_level(int level);
-extern int get_backlight_level(void);
+extern int pmac_has_backlight_type(const char *type);
+
+extern void pmac_backlight_key_up(void);
+extern void pmac_backlight_key_down(void);
+
+extern int pmac_backlight_set_legacy_brightness(int brightness);
+extern int pmac_backlight_get_legacy_brightness(void);
 
 #endif /* __KERNEL__ */
 #endif
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
index d1c2a4405660..76e2f08c3c83 100644
--- a/include/asm-powerpc/bitops.h
+++ b/include/asm-powerpc/bitops.h
@@ -288,8 +288,8 @@ static __inline__ int test_le_bit(unsigned long nr,
 #define __test_and_clear_le_bit(nr, addr) \
         __test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
 
-#define find_first_zero_le_bit(addr, size) find_next_zero_le_bit((addr), (size), 0)
-unsigned long find_next_zero_le_bit(const unsigned long *addr,
+#define find_first_zero_le_bit(addr, size) generic_find_next_zero_le_bit((addr), (size), 0)
+unsigned long generic_find_next_zero_le_bit(const unsigned long *addr,
                                     unsigned long size, unsigned long offset);
 
 /* Bitmap functions for the ext2 filesystem */
@@ -309,7 +309,7 @@ unsigned long find_next_zero_le_bit(const unsigned long *addr,
 #define ext2_find_first_zero_bit(addr, size) \
         find_first_zero_le_bit((unsigned long*)addr, size)
 #define ext2_find_next_zero_bit(addr, size, off) \
-        find_next_zero_le_bit((unsigned long*)addr, size, off)
+        generic_find_next_zero_le_bit((unsigned long*)addr, size, off)
 
 /* Bitmap functions for the minix filesystem.  */
 
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 9fcf0162d859..1ba3c9983614 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -24,6 +24,9 @@
 #define PPC_FEATURE_ICACHE_SNOOP        0x00002000
 #define PPC_FEATURE_ARCH_2_05           0x00001000
 
+#define PPC_FEATURE_TRUE_LE             0x00000002
+#define PPC_FEATURE_PPC_LE              0x00000001
+
 #ifdef __KERNEL__
 #ifndef __ASSEMBLY__
 
@@ -69,6 +72,13 @@ struct cpu_spec {
         /* Processor specific oprofile operations */
         enum powerpc_oprofile_type oprofile_type;
 
+        /* Bit locations inside the mmcra change */
+        unsigned long   oprofile_mmcra_sihv;
+        unsigned long   oprofile_mmcra_sipr;
+
+        /* Bits to clear during an oprofile exception */
+        unsigned long   oprofile_mmcra_clear;
+
         /* Name of processor class, for the ELF AT_PLATFORM entry */
         char            *platform;
 };
@@ -104,41 +114,33 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTR_NO_BTIC                 ASM_CONST(0x0000000000040000)
 #define CPU_FTR_BIG_PHYS                ASM_CONST(0x0000000000080000)
 #define CPU_FTR_NODSISRALIGN            ASM_CONST(0x0000000000100000)
+#define CPU_FTR_PPC_LE                  ASM_CONST(0x0000000000200000)
+#define CPU_FTR_REAL_LE                 ASM_CONST(0x0000000000400000)
 
+/*
+ * Add the 64-bit processor unique features in the top half of the word;
+ * on 32-bit, make the names available but defined to be 0.
+ */
 #ifdef __powerpc64__
-/* Add the 64b processor unique features in the top half of the word */
-#define CPU_FTR_SLB                     ASM_CONST(0x0000000100000000)
-#define CPU_FTR_16M_PAGE                ASM_CONST(0x0000000200000000)
-#define CPU_FTR_TLBIEL                  ASM_CONST(0x0000000400000000)
-#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0000000800000000)
-#define CPU_FTR_IABR                    ASM_CONST(0x0000002000000000)
-#define CPU_FTR_MMCRA                   ASM_CONST(0x0000004000000000)
-#define CPU_FTR_CTRL                    ASM_CONST(0x0000008000000000)
-#define CPU_FTR_SMT                     ASM_CONST(0x0000010000000000)
-#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0000020000000000)
-#define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0000040000000000)
-#define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0000080000000000)
-#define CPU_FTR_CI_LARGE_PAGE           ASM_CONST(0x0000100000000000)
-#define CPU_FTR_PAUSE_ZERO              ASM_CONST(0x0000200000000000)
-#define CPU_FTR_PURR                    ASM_CONST(0x0000400000000000)
+#define LONG_ASM_CONST(x)               ASM_CONST(x)
 #else
-/* ensure on 32b processors the flags are available for compiling but
- * don't do anything */
-#define CPU_FTR_SLB                     ASM_CONST(0x0)
-#define CPU_FTR_16M_PAGE                ASM_CONST(0x0)
-#define CPU_FTR_TLBIEL                  ASM_CONST(0x0)
-#define CPU_FTR_NOEXECUTE               ASM_CONST(0x0)
-#define CPU_FTR_IABR                    ASM_CONST(0x0)
-#define CPU_FTR_MMCRA                   ASM_CONST(0x0)
-#define CPU_FTR_CTRL                    ASM_CONST(0x0)
-#define CPU_FTR_SMT                     ASM_CONST(0x0)
-#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x0)
-#define CPU_FTR_LOCKLESS_TLBIE          ASM_CONST(0x0)
-#define CPU_FTR_MMCRA_SIHV              ASM_CONST(0x0)
-#define CPU_FTR_CI_LARGE_PAGE           ASM_CONST(0x0)
-#define CPU_FTR_PURR                    ASM_CONST(0x0)
+#define LONG_ASM_CONST(x)               0
 #endif
 
+#define CPU_FTR_SLB                     LONG_ASM_CONST(0x0000000100000000)
+#define CPU_FTR_16M_PAGE                LONG_ASM_CONST(0x0000000200000000)
+#define CPU_FTR_TLBIEL                  LONG_ASM_CONST(0x0000000400000000)
+#define CPU_FTR_NOEXECUTE               LONG_ASM_CONST(0x0000000800000000)
+#define CPU_FTR_IABR                    LONG_ASM_CONST(0x0000002000000000)
+#define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000004000000000)
+#define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000008000000000)
+#define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000010000000000)
+#define CPU_FTR_COHERENT_ICACHE         LONG_ASM_CONST(0x0000020000000000)
+#define CPU_FTR_LOCKLESS_TLBIE          LONG_ASM_CONST(0x0000040000000000)
+#define CPU_FTR_CI_LARGE_PAGE           LONG_ASM_CONST(0x0000100000000000)
+#define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000200000000000)
+#define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000400000000000)
+
 #ifndef __ASSEMBLY__
 
 #define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
@@ -192,92 +194,95 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE)
 #define CPU_FTRS_603    (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
-            CPU_FTR_MAYBE_CAN_NAP)
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 #define CPU_FTRS_604    (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-            CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE)
+            CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE | \
+            CPU_FTR_PPC_LE)
 #define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-            CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
+            CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 #define CPU_FTRS_740    (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
+            CPU_FTR_PPC_LE)
 #define CPU_FTRS_750    (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
-            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP)
+            CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
+            CPU_FTR_PPC_LE)
 #define CPU_FTRS_750FX1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
+            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
 #define CPU_FTRS_750FX2 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-            CPU_FTR_NO_DPM)
+            CPU_FTR_NO_DPM | CPU_FTR_PPC_LE)
 #define CPU_FTRS_750FX  (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
             CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS)
+            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
 #define CPU_FTRS_750GX  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
-            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS)
+            CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
-            CPU_FTR_MAYBE_CAN_NAP)
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7400   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
             CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
-            CPU_FTR_MAYBE_CAN_NAP)
+            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7450_20        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-            CPU_FTR_NEED_COHERENT)
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7450_21        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | \
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
-            CPU_FTR_NEED_COHERENT)
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7450_23        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | \
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
-            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT)
+            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | \
             CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
-            CPU_FTR_NEED_COHERENT)
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7455_20        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | \
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
-            CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS)
+            CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7455   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | \
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-            CPU_FTR_NEED_COHERENT)
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7447_10        (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | \
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC)
+            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7447   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | \
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
             CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-            CPU_FTR_NEED_COHERENT)
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 #define CPU_FTRS_7447A  (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | \
             CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
             CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
-            CPU_FTR_NEED_COHERENT)
+            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 #define CPU_FTRS_82XX   (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 #define CPU_FTRS_G2_LE  (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE | \
@@ -287,13 +292,6 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
             CPU_FTR_COMMON)
 #define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
             CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
-#define CPU_FTRS_POWER3_32      (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
-#define CPU_FTRS_POWER4_32      (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_NODSISRALIGN)
-#define CPU_FTRS_970_32 (CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE | \
-            CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP | \
-            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
 #define CPU_FTRS_8XX    (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB)
 #define CPU_FTRS_40X    (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
             CPU_FTR_NODSISRALIGN)
@@ -307,7 +305,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
 #define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 #ifdef __powerpc64__
 #define CPU_FTRS_POWER3 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
-            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR)
+            CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
 #define CPU_FTRS_RS64   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
             CPU_FTR_MMCRA | CPU_FTR_CTRL)
@@ -320,16 +318,16 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
-            CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR)
+            CPU_FTR_PURR)
 #define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
             CPU_FTR_MMCRA | CPU_FTR_SMT | \
             CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
-            CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE)
+            CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_REAL_LE)
 #define CPU_FTRS_CELL   (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
             CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
-            CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO)
+            CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
 #define CPU_FTRS_COMPATIBLE     (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
             CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
 #endif
@@ -354,12 +352,6 @@ enum {
 #else
             CPU_FTRS_GENERIC_32 |
 #endif
-#ifdef CONFIG_PPC64BRIDGE
-            CPU_FTRS_POWER3_32 |
-#endif
-#ifdef CONFIG_POWER4
-            CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
-#endif
 #ifdef CONFIG_8xx
             CPU_FTRS_8XX |
 #endif
@@ -399,12 +391,6 @@ enum {
 #else
             CPU_FTRS_GENERIC_32 &
 #endif
-#ifdef CONFIG_PPC64BRIDGE
-            CPU_FTRS_POWER3_32 &
-#endif
-#ifdef CONFIG_POWER4
-            CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
-#endif
 #ifdef CONFIG_8xx
             CPU_FTRS_8XX &
 #endif
diff --git a/include/asm-powerpc/delay.h b/include/asm-powerpc/delay.h
index 057a60955474..f9200a65c632 100644
--- a/include/asm-powerpc/delay.h
+++ b/include/asm-powerpc/delay.h
@@ -17,5 +17,18 @@
 extern void __delay(unsigned long loops);
 extern void udelay(unsigned long usecs);
 
+/*
+ * On shared processor machines the generic implementation of mdelay can
+ * result in large errors. While each iteration of the loop inside mdelay
+ * is supposed to take 1ms, the hypervisor could sleep our partition for
+ * longer (eg 10ms). With the right timing these errors can add up.
+ *
+ * Since there is no 32bit overflow issue on 64bit kernels, just call
+ * udelay directly.
+ */
+#ifdef CONFIG_PPC64
+#define mdelay(n)       udelay((n) * 1000)
+#endif
+
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_DELAY_H */
diff --git a/include/asm-powerpc/eeh.h b/include/asm-powerpc/eeh.h
index e9c86b1eedab..4df3e80118f4 100644
--- a/include/asm-powerpc/eeh.h
+++ b/include/asm-powerpc/eeh.h
@@ -292,8 +292,6 @@ static inline void eeh_memcpy_toio(volatile void __iomem *dest, const void *src,
 static inline u8 eeh_inb(unsigned long port)
 {
         u8 val;
-        if (!_IO_IS_VALID(port))
-                return ~0;
         val = in_8((u8 __iomem *)(port+pci_io_base));
         if (EEH_POSSIBLE_ERROR(val, u8))
                 return eeh_check_failure((void __iomem *)(port), val);
@@ -302,15 +300,12 @@ static inline u8 eeh_inb(unsigned long port)
 
 static inline void eeh_outb(u8 val, unsigned long port)
 {
-        if (_IO_IS_VALID(port))
-                out_8((u8 __iomem *)(port+pci_io_base), val);
+        out_8((u8 __iomem *)(port+pci_io_base), val);
 }
 
 static inline u16 eeh_inw(unsigned long port)
 {
         u16 val;
-        if (!_IO_IS_VALID(port))
-                return ~0;
         val = in_le16((u16 __iomem *)(port+pci_io_base));
         if (EEH_POSSIBLE_ERROR(val, u16))
                 return eeh_check_failure((void __iomem *)(port), val);
@@ -319,15 +314,12 @@ static inline u16 eeh_inw(unsigned long port)
 
 static inline void eeh_outw(u16 val, unsigned long port)
 {
-        if (_IO_IS_VALID(port))
-                out_le16((u16 __iomem *)(port+pci_io_base), val);
+        out_le16((u16 __iomem *)(port+pci_io_base), val);
 }
 
 static inline u32 eeh_inl(unsigned long port)
 {
         u32 val;
-        if (!_IO_IS_VALID(port))
-                return ~0;
         val = in_le32((u32 __iomem *)(port+pci_io_base));
         if (EEH_POSSIBLE_ERROR(val, u32))
                 return eeh_check_failure((void __iomem *)(port), val);
@@ -336,8 +328,7 @@ static inline u32 eeh_inl(unsigned long port)
 
 static inline void eeh_outl(u32 val, unsigned long port)
 {
-        if (_IO_IS_VALID(port))
-                out_le32((u32 __iomem *)(port+pci_io_base), val);
+        out_le32((u32 __iomem *)(port+pci_io_base), val);
 }
 
 /* in-string eeh macros */
diff --git a/include/asm-powerpc/eeh_event.h b/include/asm-powerpc/eeh_event.h
index 93d55a2bebfd..dc6bf0ffb796 100644
--- a/include/asm-powerpc/eeh_event.h
+++ b/include/asm-powerpc/eeh_event.h
@@ -18,8 +18,8 @@
  * Copyright (c) 2005 Linas Vepstas <linas@linas.org>
  */
 
-#ifndef ASM_PPC64_EEH_EVENT_H
-#define ASM_PPC64_EEH_EVENT_H
+#ifndef ASM_POWERPC_EEH_EVENT_H
+#define ASM_POWERPC_EEH_EVENT_H
 #ifdef __KERNEL__
 
 /** EEH event -- structure holding pci controller data that describes
@@ -39,7 +39,7 @@ struct eeh_event {
  * @dev pci device
  *
  * This routine builds a PCI error event which will be delivered
- * to all listeners on the peh_notifier_chain.
+ * to all listeners on the eeh_notifier_chain.
  *
  * This routine can be called within an interrupt context;
  * the actual event will be delivered in a normal context
@@ -51,7 +51,7 @@ int eeh_send_failure_event (struct device_node *dn,
                             int time_unavail);
 
 /* Main recovery function */
-void handle_eeh_events (struct eeh_event *);
+struct pci_dn * handle_eeh_events (struct eeh_event *);
 
 #endif /* __KERNEL__ */
-#endif /* ASM_PPC64_EEH_EVENT_H */
+#endif /* ASM_POWERPC_EEH_EVENT_H */
diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h
index 99c18b71aa82..9a83a987d396 100644
--- a/include/asm-powerpc/elf.h
+++ b/include/asm-powerpc/elf.h
@@ -293,7 +293,7 @@ do {									\
         NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize);                      \
         NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize);                      \
         NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize);                      \
-        VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base)        \
+        VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->mm->context.vdso_base)   \
 } while (0)
 
 /* PowerPC64 relocations defined by the ABIs */
diff --git a/include/asm-powerpc/floppy.h b/include/asm-powerpc/floppy.h
index 7e2d169ee856..fd242a22331c 100644
--- a/include/asm-powerpc/floppy.h
+++ b/include/asm-powerpc/floppy.h
@@ -27,8 +27,7 @@
 #define fd_disable_irq()        disable_irq(FLOPPY_IRQ)
 #define fd_cacheflush(addr,size) /* nothing */
 #define fd_request_irq()        request_irq(FLOPPY_IRQ, floppy_interrupt, \
-                                            SA_INTERRUPT|SA_SAMPLE_RANDOM, \
-                                            "floppy", NULL)
+                                            IRQF_DISABLED, "floppy", NULL)
 #define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
 
 #ifdef CONFIG_PCI
diff --git a/include/asm-powerpc/hvcall.h b/include/asm-powerpc/hvcall.h
index 6cc7e1fb7bfd..0d3c4e85711a 100644
--- a/include/asm-powerpc/hvcall.h
+++ b/include/asm-powerpc/hvcall.h
@@ -102,6 +102,15 @@
 #define H_PP1                   (1UL<<(63-62))
 #define H_PP2                   (1UL<<(63-63))
 
+/* VASI States */
+#define H_VASI_INVALID          0
+#define H_VASI_ENABLED          1
+#define H_VASI_ABORTED          2
+#define H_VASI_SUSPENDING       3
+#define H_VASI_SUSPENDED        4
+#define H_VASI_RESUMED          5
+#define H_VASI_COMPLETED        6
+
 /* DABRX flags */
 #define H_DABRX_HYPERVISOR      (1UL<<(63-61))
 #define H_DABRX_KERNEL          (1UL<<(63-62))
@@ -190,6 +199,7 @@
 #define H_QUERY_INT_STATE       0x1E4
 #define H_POLL_PENDING          0x1D8
 #define H_JOIN                  0x298
+#define H_VASI_STATE            0x2A4
 #define H_ENABLE_CRQ            0x2B0
 
 #ifndef __ASSEMBLY__
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index ce0f7db63c16..d40359204aba 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -86,27 +86,27 @@ static inline void local_irq_save_ptr(unsigned long *flags)
 #define mask_irq(irq)                                           \
         ({                                                      \
                 irq_desc_t *desc = get_irq_desc(irq);           \
-                if (desc->handler && desc->handler->disable)    \
-                        desc->handler->disable(irq);            \
+                if (desc->chip && desc->chip->disable)  \
+                        desc->chip->disable(irq);               \
         })
 #define unmask_irq(irq)                                         \
         ({                                                      \
                 irq_desc_t *desc = get_irq_desc(irq);           \
-                if (desc->handler && desc->handler->enable)     \
-                        desc->handler->enable(irq);             \
+                if (desc->chip && desc->chip->enable)   \
+                        desc->chip->enable(irq);                \
         })
 #define ack_irq(irq)                                            \
         ({                                                      \
                 irq_desc_t *desc = get_irq_desc(irq);           \
-                if (desc->handler && desc->handler->ack)        \
-                        desc->handler->ack(irq);                \
+                if (desc->chip && desc->chip->ack)      \
+                        desc->chip->ack(irq);           \
         })
 
-/* Should we handle this via lost interrupts and IPIs or should we don't care like
- * we do now ? --BenH.
+/*
+ * interrupt-retrigger: should we handle this via lost interrupts and IPIs
+ * or should we not care like we do now ? --BenH.
  */
 struct hw_interrupt_type;
-static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
 
 #endif  /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/include/asm-powerpc/i8259.h b/include/asm-powerpc/i8259.h
index 0392159e16e4..c80e113052cd 100644
--- a/include/asm-powerpc/i8259.h
+++ b/include/asm-powerpc/i8259.h
@@ -4,11 +4,13 @@
 
 #include <linux/irq.h>
 
-extern struct hw_interrupt_type i8259_pic;
-
+#ifdef CONFIG_PPC_MERGE
+extern void i8259_init(struct device_node *node, unsigned long intack_addr);
+extern unsigned int i8259_irq(struct pt_regs *regs);
+#else
 extern void i8259_init(unsigned long intack_addr, int offset);
 extern int i8259_irq(struct pt_regs *regs);
-extern int i8259_irq_cascade(struct pt_regs *regs, void *unused);
+#endif
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_I8259_H */
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
new file mode 100644
index 000000000000..d905b6622268
--- /dev/null
+++ b/include/asm-powerpc/immap_86xx.h
@@ -0,0 +1,199 @@
+/*
+ * MPC86xx Internal Memory Map
+ *
+ * Author: Jeff Brown
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#ifndef __ASM_POWERPC_IMMAP_86XX_H__
+#define __ASM_POWERPC_IMMAP_86XX_H__
+#ifdef __KERNEL__
+
+/* Eventually this should define all the IO block registers in 86xx */
+
+/* PCI Registers */
+typedef struct ccsr_pci {
+        uint    cfg_addr;       /* 0x.000 - PCI Configuration Address Register */
+        uint    cfg_data;       /* 0x.004 - PCI Configuration Data Register */
+        uint    int_ack;        /* 0x.008 - PCI Interrupt Acknowledge Register */
+        char    res1[3060];
+        uint    potar0;         /* 0x.c00 - PCI Outbound Transaction Address Register 0 */
+        uint    potear0;        /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */
+        uint    powbar0;        /* 0x.c08 - PCI Outbound Window Base Address Register 0 */
+        char    res2[4];
+        uint    powar0;         /* 0x.c10 - PCI Outbound Window Attributes Register 0 */
+        char    res3[12];
+        uint    potar1;         /* 0x.c20 - PCI Outbound Transaction Address Register 1 */
+        uint    potear1;        /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */
+        uint    powbar1;        /* 0x.c28 - PCI Outbound Window Base Address Register 1 */
+        char    res4[4];
+        uint    powar1;         /* 0x.c30 - PCI Outbound Window Attributes Register 1 */
+        char    res5[12];
+        uint    potar2;         /* 0x.c40 - PCI Outbound Transaction Address Register 2 */
+        uint    potear2;        /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */
+        uint    powbar2;        /* 0x.c48 - PCI Outbound Window Base Address Register 2 */
+        char    res6[4];
+        uint    powar2;         /* 0x.c50 - PCI Outbound Window Attributes Register 2 */
+        char    res7[12];
+        uint    potar3;         /* 0x.c60 - PCI Outbound Transaction Address Register 3 */
+        uint    potear3;        /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */
+        uint    powbar3;        /* 0x.c68 - PCI Outbound Window Base Address Register 3 */
+        char    res8[4];
+        uint    powar3;         /* 0x.c70 - PCI Outbound Window Attributes Register 3 */
+        char    res9[12];
+        uint    potar4;         /* 0x.c80 - PCI Outbound Transaction Address Register 4 */
+        uint    potear4;        /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */
+        uint    powbar4;        /* 0x.c88 - PCI Outbound Window Base Address Register 4 */
+        char    res10[4];
+        uint    powar4;         /* 0x.c90 - PCI Outbound Window Attributes Register 4 */
+        char    res11[268];
+        uint    pitar3;         /* 0x.da0 - PCI Inbound Translation Address Register 3  */
+        char    res12[4];
+        uint    piwbar3;        /* 0x.da8 - PCI Inbound Window Base Address Register 3 */
+        uint    piwbear3;       /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */
+        uint    piwar3;         /* 0x.db0 - PCI Inbound Window Attributes Register 3 */
+        char    res13[12];
+        uint    pitar2;         /* 0x.dc0 - PCI Inbound Translation Address Register 2  */
+        char    res14[4];
+        uint    piwbar2;        /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */
+        uint    piwbear2;       /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */
+        uint    piwar2;         /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */
+        char    res15[12];
+        uint    pitar1;         /* 0x.de0 - PCI Inbound Translation Address Register 1  */
+        char    res16[4];
+        uint    piwbar1;        /* 0x.de8 - PCI Inbound Window Base Address Register 1 */
+        char    res17[4];
+        uint    piwar1;         /* 0x.df0 - PCI Inbound Window Attributes Register 1 */
+        char    res18[12];
+        uint    err_dr;         /* 0x.e00 - PCI Error Detect Register */
+        uint    err_cap_dr;     /* 0x.e04 - PCI Error Capture Disable Register */
+        uint    err_en;         /* 0x.e08 - PCI Error Enable Register */
+        uint    err_attrib;     /* 0x.e0c - PCI Error Attributes Capture Register */
+        uint    err_addr;       /* 0x.e10 - PCI Error Address Capture Register */
+        uint    err_ext_addr;   /* 0x.e14 - PCI Error Extended Address Capture Register */
+        uint    err_dl;         /* 0x.e18 - PCI Error Data Low Capture Register */
+        uint    err_dh;         /* 0x.e1c - PCI Error Data High Capture Register */
+        uint    gas_timr;       /* 0x.e20 - PCI Gasket Timer Register */
+        uint    pci_timr;       /* 0x.e24 - PCI Timer Register */
+        char    res19[472];
+} ccsr_pci_t;
+
+/* PCI Express Registers */
+typedef struct ccsr_pex {
+        uint    pex_config_addr;        /* 0x.000 - PCI Express Configuration Address Register */
+        uint    pex_config_data;        /* 0x.004 - PCI Express Configuration Data Register */
+        char    res1[4];
+        uint    pex_otb_cpl_tor;        /* 0x.00c - PCI Express Outbound completion timeout register */
+        uint    pex_conf_tor;           /* 0x.010 - PCI Express configuration timeout register */
+        char    res2[12];
+        uint    pex_pme_mes_dr;         /* 0x.020 - PCI Express PME and message detect register */
+        uint    pex_pme_mes_disr;       /* 0x.024 - PCI Express PME and message disable register */
+        uint    pex_pme_mes_ier;        /* 0x.028 - PCI Express PME and message interrupt enable register */
+        uint    pex_pmcr;               /* 0x.02c - PCI Express power management command register */
+        char    res3[3024];
+        uint    pexotar0;               /* 0x.c00 - PCI Express outbound translation address register 0 */
+        uint    pexotear0;              /* 0x.c04 - PCI Express outbound translation extended address register 0*/
+        char    res4[8];
+        uint    pexowar0;               /* 0x.c10 - PCI Express outbound window attributes register 0*/
+        char    res5[12];
+        uint    pexotar1;               /* 0x.c20 - PCI Express outbound translation address register 1 */
+        uint    pexotear1;              /* 0x.c24 - PCI Express outbound translation extended address register 1*/
+        uint    pexowbar1;              /* 0x.c28 - PCI Express outbound window base address register 1*/
+        char    res6[4];
+        uint    pexowar1;               /* 0x.c30 - PCI Express outbound window attributes register 1*/
+        char    res7[12];
+        uint    pexotar2;               /* 0x.c40 - PCI Express outbound translation address register 2 */
+        uint    pexotear2;              /* 0x.c44 - PCI Express outbound translation extended address register 2*/
+        uint    pexowbar2;              /* 0x.c48 - PCI Express outbound window base address register 2*/
+        char    res8[4];
+        uint    pexowar2;               /* 0x.c50 - PCI Express outbound window attributes register 2*/
+        char    res9[12];
+        uint    pexotar3;               /* 0x.c60 - PCI Express outbound translation address register 3 */
+        uint    pexotear3;              /* 0x.c64 - PCI Express outbound translation extended address register 3*/
+        uint    pexowbar3;              /* 0x.c68 - PCI Express outbound window base address register 3*/
+        char    res10[4];
+        uint    pexowar3;               /* 0x.c70 - PCI Express outbound window attributes register 3*/
+        char    res11[12];
+        uint    pexotar4;               /* 0x.c80 - PCI Express outbound translation address register 4 */
+        uint    pexotear4;              /* 0x.c84 - PCI Express outbound translation extended address register 4*/
+        uint    pexowbar4;              /* 0x.c88 - PCI Express outbound window base address register 4*/
+        char    res12[4];
+        uint    pexowar4;               /* 0x.c90 - PCI Express outbound window attributes register 4*/
+        char    res13[12];
+        char    res14[256];
+        uint    pexitar3;               /* 0x.da0 - PCI Express inbound translation address register 3 */
+        char    res15[4];
+        uint    pexiwbar3;              /* 0x.da8 - PCI Express inbound window base address register 3 */
+        uint    pexiwbear3;             /* 0x.dac - PCI Express inbound window base extended address register 3 */
+        uint    pexiwar3;               /* 0x.db0 - PCI Express inbound window attributes register 3 */
+        char    res16[12];
+        uint    pexitar2;               /* 0x.dc0 - PCI Express inbound translation address register 2 */
+        char    res17[4];
+        uint    pexiwbar2;              /* 0x.dc8 - PCI Express inbound window base address register 2 */
+        uint    pexiwbear2;             /* 0x.dcc - PCI Express inbound window base extended address register 2 */
+        uint    pexiwar2;               /* 0x.dd0 - PCI Express inbound window attributes register 2 */
+        char    res18[12];
+        uint    pexitar1;               /* 0x.de0 - PCI Express inbound translation address register 2 */
+        char    res19[4];
+        uint    pexiwbar1;              /* 0x.de8 - PCI Express inbound window base address register 2 */
+        uint    pexiwbear1;             /* 0x.dec - PCI Express inbound window base extended address register 2 */
+        uint    pexiwar1;               /* 0x.df0 - PCI Express inbound window attributes register 2 */
+        char    res20[12];
+        uint    pex_err_dr;             /* 0x.e00 - PCI Express error detect register */
+        char    res21[4];
+        uint    pex_err_en;             /* 0x.e08 - PCI Express error interrupt enable register */
+        char    res22[4];
+        uint    pex_err_disr;           /* 0x.e10 - PCI Express error disable register */
+        char    res23[12];
+        uint    pex_err_cap_stat;       /* 0x.e20 - PCI Express error capture status register */
+        char    res24[4];
+        uint    pex_err_cap_r0;         /* 0x.e28 - PCI Express error capture register 0 */
+        uint    pex_err_cap_r1;         /* 0x.e2c - PCI Express error capture register 0 */
+        uint    pex_err_cap_r2;         /* 0x.e30 - PCI Express error capture register 0 */
+        uint    pex_err_cap_r3;         /* 0x.e34 - PCI Express error capture register 0 */
+} ccsr_pex_t;
+
+/* Global Utility Registers */
+typedef struct ccsr_guts {
+        uint    porpllsr;       /* 0x.0000 - POR PLL Ratio Status Register */
+        uint    porbmsr;        /* 0x.0004 - POR Boot Mode Status Register */
+        uint    porimpscr;      /* 0x.0008 - POR I/O Impedance Status and Control Register */
+        uint    pordevsr;       /* 0x.000c - POR I/O Device Status Register */
+        uint    pordbgmsr;      /* 0x.0010 - POR Debug Mode Status Register */
+        char    res1[12];
+        uint    gpporcr;        /* 0x.0020 - General-Purpose POR Configuration Register */
+        char    res2[12];
+        uint    gpiocr;         /* 0x.0030 - GPIO Control Register */
+        char    res3[12];
+        uint    gpoutdr;        /* 0x.0040 - General-Purpose Output Data Register */
+        char    res4[12];
+        uint    gpindr;         /* 0x.0050 - General-Purpose Input Data Register */
+        char    res5[12];
+        uint    pmuxcr;         /* 0x.0060 - Alternate Function Signal Multiplex Control */
+        char    res6[12];
+        uint    devdisr;        /* 0x.0070 - Device Disable Control */
+        char    res7[12];
+        uint    powmgtcsr;      /* 0x.0080 - Power Management Status and Control Register */
+        char    res8[12];
+        uint    mcpsumr;        /* 0x.0090 - Machine Check Summary Register */
+        char    res9[12];
+        uint    pvr;            /* 0x.00a0 - Processor Version Register */
+        uint    svr;            /* 0x.00a4 - System Version Register */
+        char    res10[3416];
+        uint    clkocr;         /* 0x.0e00 - Clock Out Select Register */
+        char    res11[12];
+        uint    ddrdllcr;       /* 0x.0e10 - DDR DLL Control Register */
+        char    res12[12];
+        uint    lbcdllcr;       /* 0x.0e20 - LBC DLL Control Register */
+        char    res13[61916];
+} ccsr_guts_t;
+
+#endif /* __ASM_POWERPC_IMMAP_86XX_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index f1c2469b8844..a9496f34b048 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -40,12 +40,6 @@ extern int check_legacy_ioport(unsigned long base_port);
 
 extern unsigned long isa_io_base;
 extern unsigned long pci_io_base;
-extern unsigned long io_page_mask;
-
-#define MAX_ISA_PORT 0x10000
-
-#define _IO_IS_VALID(port) ((port) >= MAX_ISA_PORT || (1 << (port>>PAGE_SHIFT)) \
-                            & io_page_mask)
 
 #ifdef CONFIG_PPC_ISERIES
 /* __raw_* accessors aren't supported on iSeries */
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
index 2acf7b29ef06..a5e98641a2ae 100644
--- a/include/asm-powerpc/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -66,7 +66,8 @@ extern void iommu_free_table(struct device_node *dn);
 /* Initializes an iommu_table based in values set in the passed-in
  * structure
  */
-extern struct iommu_table *iommu_init_table(struct iommu_table * tbl);
+extern struct iommu_table *iommu_init_table(struct iommu_table * tbl,
+                                            int nid);
 
 extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
                 struct scatterlist *sglist, int nelems, unsigned long mask,
@@ -75,7 +76,8 @@ extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
                 int nelems, enum dma_data_direction direction);
 
 extern void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
-                dma_addr_t *dma_handle, unsigned long mask, gfp_t flag);
+                dma_addr_t *dma_handle, unsigned long mask,
+                gfp_t flag, int node);
 extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
                 void *vaddr, dma_addr_t dma_handle);
 extern dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index 1e9f25330307..e05754752028 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -9,31 +9,14 @@
  * 2 of the License, or (at your option) any later version.
  */
 
+#include <linux/config.h>
 #include <linux/threads.h>
+#include <linux/list.h>
+#include <linux/radix-tree.h>
 
 #include <asm/types.h>
 #include <asm/atomic.h>
 
-/* this number is used when no interrupt has been assigned */
-#define NO_IRQ                  (-1)
-
-/*
- * These constants are used for passing information about interrupt
- * signal polarity and level/edge sensing to the low-level PIC chip
- * drivers.
- */
-#define IRQ_SENSE_MASK          0x1
-#define IRQ_SENSE_LEVEL         0x1     /* interrupt on active level */
-#define IRQ_SENSE_EDGE          0x0     /* interrupt triggered by edge */
-
-#define IRQ_POLARITY_MASK       0x2
-#define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
-#define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
-
-/*
- * IRQ line status macro IRQ_PER_CPU is used
- */
-#define ARCH_HAS_IRQ_PER_CPU
 
 #define get_irq_desc(irq) (&irq_desc[(irq)])
 
@@ -41,50 +24,325 @@
 #define for_each_irq(i) \
         for ((i) = 0; (i) < NR_IRQS; ++(i))
 
-#ifdef CONFIG_PPC64
+extern atomic_t ppc_n_lost_interrupts;
 
-/*
- * Maximum number of interrupt sources that we can handle.
+#ifdef CONFIG_PPC_MERGE
+
+/* This number is used when no interrupt has been assigned */
+#define NO_IRQ                  (0)
+
+/* This is a special irq number to return from get_irq() to tell that
+ * no interrupt happened _and_ ignore it (don't count it as bad). Some
+ * platforms like iSeries rely on that.
  */
+#define NO_IRQ_IGNORE           ((unsigned int)-1)
+
+/* Total number of virq in the platform (make it a CONFIG_* option ? */
 #define NR_IRQS         512
 
-/* Interrupt numbers are virtual in case they are sparsely
- * distributed by the hardware.
+/* Number of irqs reserved for the legacy controller */
+#define NUM_ISA_INTERRUPTS      16
+
+/* This type is the placeholder for a hardware interrupt number. It has to
+ * be big enough to enclose whatever representation is used by a given
+ * platform.
+ */
+typedef unsigned long irq_hw_number_t;
+
+/* Interrupt controller "host" data structure. This could be defined as a
+ * irq domain controller. That is, it handles the mapping between hardware
+ * and virtual interrupt numbers for a given interrupt domain. The host
+ * structure is generally created by the PIC code for a given PIC instance
+ * (though a host can cover more than one PIC if they have a flat number
+ * model). It's the host callbacks that are responsible for setting the
+ * irq_chip on a given irq_desc after it's been mapped.
+ *
+ * The host code and data structures are fairly agnostic to the fact that
+ * we use an open firmware device-tree. We do have references to struct
+ * device_node in two places: in irq_find_host() to find the host matching
+ * a given interrupt controller node, and of course as an argument to its
+ * counterpart host->ops->match() callback. However, those are treated as
+ * generic pointers by the core and the fact that it's actually a device-node
+ * pointer is purely a convention between callers and implementation. This
+ * code could thus be used on other architectures by replacing those two
+ * by some sort of arch-specific void * "token" used to identify interrupt
+ * controllers.
+ */
+struct irq_host;
+struct radix_tree_root;
+
+/* Functions below are provided by the host and called whenever a new mapping
+ * is created or an old mapping is disposed. The host can then proceed to
+ * whatever internal data structures management is required. It also needs
+ * to setup the irq_desc when returning from map().
+ */
+struct irq_host_ops {
+        /* Match an interrupt controller device node to a host, returns
+         * 1 on a match
+         */
+        int (*match)(struct irq_host *h, struct device_node *node);
+
+        /* Create or update a mapping between a virtual irq number and a hw
+         * irq number. This can be called several times for the same mapping
+         * but with different flags, though unmap shall always be called
+         * before the virq->hw mapping is changed.
+         */
+        int (*map)(struct irq_host *h, unsigned int virq,
+                   irq_hw_number_t hw, unsigned int flags);
+
+        /* Dispose of such a mapping */
+        void (*unmap)(struct irq_host *h, unsigned int virq);
+
+        /* Translate device-tree interrupt specifier from raw format coming
+         * from the firmware to a irq_hw_number_t (interrupt line number) and
+         * trigger flags that can be passed to irq_create_mapping().
+         * If no translation is provided, raw format is assumed to be one cell
+         * for interrupt line and default sense.
+         */
+        int (*xlate)(struct irq_host *h, struct device_node *ctrler,
+                     u32 *intspec, unsigned int intsize,
+                     irq_hw_number_t *out_hwirq, unsigned int *out_flags);
+};
+
+struct irq_host {
+        struct list_head        link;
+
+        /* type of reverse mapping technique */
+        unsigned int            revmap_type;
+#define IRQ_HOST_MAP_LEGACY     0 /* legacy 8259, gets irqs 1..15 */
+#define IRQ_HOST_MAP_NOMAP      1 /* no fast reverse mapping */
+#define IRQ_HOST_MAP_LINEAR     2 /* linear map of interrupts */
+#define IRQ_HOST_MAP_TREE       3 /* radix tree */
+        union {
+                struct {
+                        unsigned int size;
+                        unsigned int *revmap;
+                } linear;
+                struct radix_tree_root tree;
+        } revmap_data;
+        struct irq_host_ops     *ops;
+        void                    *host_data;
+        irq_hw_number_t         inval_irq;
+};
+
+/* The main irq map itself is an array of NR_IRQ entries containing the
+ * associate host and irq number. An entry with a host of NULL is free.
+ * An entry can be allocated if it's free, the allocator always then sets
+ * hwirq first to the host's invalid irq number and then fills ops.
+ */
+struct irq_map_entry {
+        irq_hw_number_t hwirq;
+        struct irq_host *host;
+};
+
+extern struct irq_map_entry irq_map[NR_IRQS];
+
+
+/***
+ * irq_alloc_host - Allocate a new irq_host data structure
+ * @node: device-tree node of the interrupt controller
+ * @revmap_type: type of reverse mapping to use
+ * @revmap_arg: for IRQ_HOST_MAP_LINEAR linear only: size of the map
+ * @ops: map/unmap host callbacks
+ * @inval_irq: provide a hw number in that host space that is always invalid
+ *
+ * Allocates and initialize and irq_host structure. Note that in the case of
+ * IRQ_HOST_MAP_LEGACY, the map() callback will be called before this returns
+ * for all legacy interrupts except 0 (which is always the invalid irq for
+ * a legacy controller). For a IRQ_HOST_MAP_LINEAR, the map is allocated by
+ * this call as well. For a IRQ_HOST_MAP_TREE, the radix tree will be allocated
+ * later during boot automatically (the reverse mapping will use the slow path
+ * until that happens).
+ */
+extern struct irq_host *irq_alloc_host(unsigned int revmap_type,
+                                       unsigned int revmap_arg,
+                                       struct irq_host_ops *ops,
+                                       irq_hw_number_t inval_irq);
+
+
+/***
+ * irq_find_host - Locates a host for a given device node
+ * @node: device-tree node of the interrupt controller
+ */
+extern struct irq_host *irq_find_host(struct device_node *node);
+
+
+/***
+ * irq_set_default_host - Set a "default" host
+ * @host: default host pointer
+ *
+ * For convenience, it's possible to set a "default" host that will be used
+ * whenever NULL is passed to irq_create_mapping(). It makes life easier for
+ * platforms that want to manipulate a few hard coded interrupt numbers that
+ * aren't properly represented in the device-tree.
+ */
+extern void irq_set_default_host(struct irq_host *host);
+
+
+/***
+ * irq_set_virq_count - Set the maximum number of virt irqs
+ * @count: number of linux virtual irqs, capped with NR_IRQS
+ *
+ * This is mainly for use by platforms like iSeries who want to program
+ * the virtual irq number in the controller to avoid the reverse mapping
+ */
+extern void irq_set_virq_count(unsigned int count);
+
+
+/***
+ * irq_create_mapping - Map a hardware interrupt into linux virq space
+ * @host: host owning this hardware interrupt or NULL for default host
+ * @hwirq: hardware irq number in that host space
+ * @flags: flags passed to the controller. contains the trigger type among
+ *         others. Use IRQ_TYPE_* defined in include/linux/irq.h
+ *
+ * Only one mapping per hardware interrupt is permitted. Returns a linux
+ * virq number. The flags can be used to provide sense information to the
+ * controller (typically extracted from the device-tree). If no information
+ * is passed, the controller defaults will apply (for example, xics can only
+ * do edge so flags are irrelevant for some pseries specific irqs).
+ *
+ * The device-tree generally contains the trigger info in an encoding that is
+ * specific to a given type of controller. In that case, you can directly use
+ * host->ops->trigger_xlate() to translate that.
+ *
+ * It is recommended that new PICs that don't have existing OF bindings chose
+ * to use a representation of triggers identical to linux.
+ */
+extern unsigned int irq_create_mapping(struct irq_host *host,
+                                       irq_hw_number_t hwirq,
+                                       unsigned int flags);
+
+
+/***
+ * irq_dispose_mapping - Unmap an interrupt
+ * @virq: linux virq number of the interrupt to unmap
+ */
+extern void irq_dispose_mapping(unsigned int virq);
+
+/***
+ * irq_find_mapping - Find a linux virq from an hw irq number.
+ * @host: host owning this hardware interrupt
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is a slow path, for use by generic code. It's expected that an
+ * irq controller implementation directly calls the appropriate low level
+ * mapping function.
+ */
+extern unsigned int irq_find_mapping(struct irq_host *host,
+                                     irq_hw_number_t hwirq);
+
+
+/***
+ * irq_radix_revmap - Find a linux virq from a hw irq number.
+ * @host: host owning this hardware interrupt
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is a fast path, for use by irq controller code that uses radix tree
+ * revmaps
  */
-extern unsigned int virt_irq_to_real_map[NR_IRQS];
+extern unsigned int irq_radix_revmap(struct irq_host *host,
+                                     irq_hw_number_t hwirq);
 
-/* The maximum virtual IRQ number that we support.  This
- * can be set by the platform and will be reduced by the
- * value of __irq_offset_value.  It defaults to and is
- * capped by (NR_IRQS - 1).
+/***
+ * irq_linear_revmap - Find a linux virq from a hw irq number.
+ * @host: host owning this hardware interrupt
+ * @hwirq: hardware irq number in that host space
+ *
+ * This is a fast path, for use by irq controller code that uses linear
+ * revmaps. It does fallback to the slow path if the revmap doesn't exist
+ * yet and will create the revmap entry with appropriate locking
  */
-extern unsigned int virt_irq_max;
 
-/* Create a mapping for a real_irq if it doesn't already exist.
- * Return the virtual irq as a convenience.
+extern unsigned int irq_linear_revmap(struct irq_host *host,
+                                      irq_hw_number_t hwirq);
+
+
+
+/***
+ * irq_alloc_virt - Allocate virtual irq numbers
+ * @host: host owning these new virtual irqs
+ * @count: number of consecutive numbers to allocate
+ * @hint: pass a hint number, the allocator will try to use a 1:1 mapping
+ *
+ * This is a low level function that is used internally by irq_create_mapping()
+ * and that can be used by some irq controllers implementations for things
+ * like allocating ranges of numbers for MSIs. The revmaps are left untouched.
+ */
+extern unsigned int irq_alloc_virt(struct irq_host *host,
+                                   unsigned int count,
+                                   unsigned int hint);
+
+/***
+ * irq_free_virt - Free virtual irq numbers
+ * @virq: virtual irq number of the first interrupt to free
+ * @count: number of interrupts to free
+ *
+ * This function is the opposite of irq_alloc_virt. It will not clear reverse
+ * maps, this should be done previously by unmap'ing the interrupt. In fact,
+ * all interrupts covered by the range being freed should have been unmapped
+ * prior to calling this.
+ */
+extern void irq_free_virt(unsigned int virq, unsigned int count);
+
+
+/* -- OF helpers -- */
+
+/* irq_create_of_mapping - Map a hardware interrupt into linux virq space
+ * @controller: Device node of the interrupt controller
+ * @inspec: Interrupt specifier from the device-tree
+ * @intsize: Size of the interrupt specifier from the device-tree
+ *
+ * This function is identical to irq_create_mapping except that it takes
+ * as input informations straight from the device-tree (typically the results
+ * of the of_irq_map_*() functions
  */
-int virt_irq_create_mapping(unsigned int real_irq);
-void virt_irq_init(void);
+extern unsigned int irq_create_of_mapping(struct device_node *controller,
+                                          u32 *intspec, unsigned int intsize);
 
-static inline unsigned int virt_irq_to_real(unsigned int virt_irq)
+
+/* irq_of_parse_and_map - Parse nad Map an interrupt into linux virq space
+ * @device: Device node of the device whose interrupt is to be mapped
+ * @index: Index of the interrupt to map
+ *
+ * This function is a wrapper that chains of_irq_map_one() and
+ * irq_create_of_mapping() to make things easier to callers
+ */
+extern unsigned int irq_of_parse_and_map(struct device_node *dev, int index);
+
+/* -- End OF helpers -- */
+
+/***
+ * irq_early_init - Init irq remapping subsystem
+ */
+extern void irq_early_init(void);
+
+static __inline__ int irq_canonicalize(int irq)
 {
-        return virt_irq_to_real_map[virt_irq];
+        return irq;
 }
 
-extern unsigned int real_irq_to_virt_slowpath(unsigned int real_irq);
+
+#else /* CONFIG_PPC_MERGE */
+
+/* This number is used when no interrupt has been assigned */
+#define NO_IRQ                  (-1)
+#define NO_IRQ_IGNORE           (-2)
+
 
 /*
- * List of interrupt controllers.
+ * These constants are used for passing information about interrupt
+ * signal polarity and level/edge sensing to the low-level PIC chip
+ * drivers.
  */
-#define IC_INVALID    0
-#define IC_OPEN_PIC   1
-#define IC_PPC_XIC    2
-#define IC_CELL_PIC   3
-#define IC_ISERIES    4
+#define IRQ_SENSE_MASK          0x1
+#define IRQ_SENSE_LEVEL         0x1     /* interrupt on active level */
+#define IRQ_SENSE_EDGE          0x0     /* interrupt triggered by edge */
 
-extern u64 ppc64_interrupt_controller;
+#define IRQ_POLARITY_MASK       0x2
+#define IRQ_POLARITY_POSITIVE   0x2     /* high level or low->high edge */
+#define IRQ_POLARITY_NEGATIVE   0x0     /* low level or high->low edge */
 
-#else /* 32-bit */
 
 #if defined(CONFIG_40x)
 #include <asm/ibm4xx.h>
@@ -347,6 +605,92 @@ extern u64 ppc64_interrupt_controller;
 #define SIU_INT_PC1             ((uint)0x3e+CPM_IRQ_OFFSET)
 #define SIU_INT_PC0             ((uint)0x3f+CPM_IRQ_OFFSET)
 
+#elif defined(CONFIG_PPC_86xx)
+#include <asm/mpc86xx.h>
+
+#define NR_EPIC_INTS 48
+#ifndef NR_8259_INTS
+#define NR_8259_INTS 16 /*ULI 1575 can route 12 interrupts */
+#endif
+#define NUM_8259_INTERRUPTS NR_8259_INTS
+
+#ifndef I8259_OFFSET
+#define I8259_OFFSET 0
+#endif
+
+#define NR_IRQS 256
+
+/* Internal IRQs on MPC86xx OpenPIC */
+
+#ifndef MPC86xx_OPENPIC_IRQ_OFFSET
+#define MPC86xx_OPENPIC_IRQ_OFFSET NR_8259_INTS
+#endif
+
+/* The 48 internal sources */
+#define MPC86xx_IRQ_NULL        ( 0 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_MCM         ( 1 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DDR         ( 2 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_LBC         ( 3 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA0        ( 4 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA1        ( 5 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA2        ( 6 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_DMA3        ( 7 + MPC86xx_OPENPIC_IRQ_OFFSET)
+
+/* no 10,11 */
+#define MPC86xx_IRQ_UART2       (12 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_TX    (13 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_RX    (14 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_TX    (15 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_RX    (16 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC3_ERROR (17 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC1_ERROR (18 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_TX    (19 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_RX    (20 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_TX    (21 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_RX    (22 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC4_ERROR (23 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_TSEC2_ERROR (24 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 25 */
+#define MPC86xx_IRQ_UART1       (26 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_IIC         (27 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_PERFMON       (28 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 29,30,31 */
+#define MPC86xx_IRQ_SRIO_ERROR    (32 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_OUT_BELL (33 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_BELL  (34 + MPC86xx_OPENPIC_IRQ_OFFSET)
+/* no 35,36 */
+#define MPC86xx_IRQ_SRIO_OUT_MSG1 (37 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_MSG1  (38 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_OUT_MSG2 (39 + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_SRIO_IN_MSG2  (40 + MPC86xx_OPENPIC_IRQ_OFFSET)
+
+/* The 12 external interrupt lines */
+#define MPC86xx_IRQ_EXT_BASE    48
+#define MPC86xx_IRQ_EXT0        (0 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT1        (1 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT2        (2 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT3        (3 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT4        (4 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT5        (5 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT6        (6 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT7        (7 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT8        (8 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT9        (9 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT10       (10 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+#define MPC86xx_IRQ_EXT11       (11 + MPC86xx_IRQ_EXT_BASE \
+                + MPC86xx_OPENPIC_IRQ_OFFSET)
+
 #else /* CONFIG_40x + CONFIG_8xx */
 /*
  * this is the # irq's for all ppc arch's (pmac/chrp/prep)
@@ -431,16 +775,11 @@ extern u64 ppc64_interrupt_controller;
 
 #endif /* CONFIG_8260 */
 
-#endif
+#endif /* Whatever way too big #ifdef */
 
 #define NR_MASK_WORDS   ((NR_IRQS + 31) / 32)
 /* pedantic: these are long because they are used with set_bit --RR */
 extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
-extern atomic_t ppc_n_lost_interrupts;
-
-#define virt_irq_create_mapping(x)      (x)
-
-#endif
 
 /*
  * Because many systems have two overlapping names spaces for
@@ -479,6 +818,7 @@ static __inline__ int irq_canonicalize(int irq)
                 irq = 9;
         return irq;
 }
+#endif /* CONFIG_PPC_MERGE */
 
 extern int distribute_irqs;
 
@@ -498,9 +838,8 @@ extern struct thread_info *softirq_ctx[NR_CPUS];
 
 extern void irq_ctx_init(void);
 extern void call_do_softirq(struct thread_info *tp);
-extern int call___do_IRQ(int irq, struct pt_regs *regs,
-                struct thread_info *tp);
-
+extern int call_handle_irq(int irq, void *p1, void *p2,
+                           struct thread_info *tp, void *func);
 #else
 #define irq_ctx_init()
 
diff --git a/include/asm-powerpc/irqflags.h b/include/asm-powerpc/irqflags.h
new file mode 100644
index 000000000000..7970cbaeaa54
--- /dev/null
+++ b/include/asm-powerpc/irqflags.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-powerpc/irqflags.h
+ *
+ * IRQ flags handling
+ *
+ * This file gets included from lowlevel asm headers too, to provide
+ * wrapped versions of the local_irq_*() APIs, based on the
+ * raw_local_irq_*() macros from the lowlevel headers.
+ */
+#ifndef _ASM_IRQFLAGS_H
+#define _ASM_IRQFLAGS_H
+
+/*
+ * Get definitions for raw_local_save_flags(x), etc.
+ */
+#include <asm-powerpc/hw_irq.h>
+
+/*
+ * Do the CPU's IRQ-state tracing from assembly code. We call a
+ * C function, so save all the C-clobbered registers:
+ */
+#ifdef CONFIG_TRACE_IRQFLAGS
+
+#error No support on PowerPC yet for CONFIG_TRACE_IRQFLAGS
+
+#else
+# define TRACE_IRQS_ON
+# define TRACE_IRQS_OFF
+#endif
+
+#endif
diff --git a/include/asm-powerpc/iseries/iommu.h b/include/asm-powerpc/iseries/iommu.h
new file mode 100644
index 000000000000..0edbfe10cb37
--- /dev/null
+++ b/include/asm-powerpc/iseries/iommu.h
@@ -0,0 +1,35 @@
+#ifndef _ASM_POWERPC_ISERIES_IOMMU_H
+#define _ASM_POWERPC_ISERIES_IOMMU_H
+
+/*
+ * Copyright (C) 2005  Stephen Rothwell, IBM Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the:
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330,
+ * Boston, MA  02111-1307  USA
+ */
+
+struct device_node;
+struct iommu_table;
+
+/* Creates table for an individual device node */
+extern void iommu_devnode_init_iSeries(struct device_node *dn);
+
+/* Get table parameters from HV */
+extern void iommu_table_getparms_iSeries(unsigned long busno,
+                unsigned char slotno, unsigned char virtbus,
+                struct iommu_table *tbl);
+
+#endif /* _ASM_POWERPC_ISERIES_IOMMU_H */
diff --git a/include/asm-powerpc/iseries/it_lp_queue.h b/include/asm-powerpc/iseries/it_lp_queue.h
index b7c6fc12cce2..284c5a7db3ac 100644
--- a/include/asm-powerpc/iseries/it_lp_queue.h
+++ b/include/asm-powerpc/iseries/it_lp_queue.h
@@ -29,20 +29,20 @@
 
 struct HvLpEvent;
 
-#define ITMaxLpQueues   8
+#define IT_LP_MAX_QUEUES        8
 
-#define NotUsed         0       // Queue will not be used by PLIC
-#define DedicatedIo     1       // Queue dedicated to IO processor specified
-#define DedicatedLp     2       // Queue dedicated to LP specified
-#define Shared          3       // Queue shared for both IO and LP
+#define IT_LP_NOT_USED          0       /* Queue will not be used by PLIC */
+#define IT_LP_DEDICATED_IO      1       /* Queue dedicated to IO processor specified */
+#define IT_LP_DEDICATED_LP      2       /* Queue dedicated to LP specified */
+#define IT_LP_SHARED            3       /* Queue shared for both IO and LP */
 
-#define LpEventStackSize        4096
-#define LpEventMaxSize          256
-#define LpEventAlign            64
+#define IT_LP_EVENT_STACK_SIZE  4096
+#define IT_LP_EVENT_MAX_SIZE    256
+#define IT_LP_EVENT_ALIGN       64
 
 struct hvlpevent_queue {
 /*
- * The xSlicCurEventPtr is the pointer to the next event stack entry
+ * The hq_current_event is the pointer to the next event stack entry
  * that will become valid.  The OS must peek at this entry to determine
  * if it is valid.  PLIC will set the valid indicator as the very last
  * store into that entry.
@@ -52,23 +52,23 @@ struct hvlpevent_queue {
  * location again.
  *
  * If the event stack fills and there are overflow events, then PLIC
- * will set the xPlicOverflowIntPending flag in which case the OS will
+ * will set the hq_overflow_pending flag in which case the OS will
  * have to fetch the additional LP events once they have drained the
  * event stack.
  *
  * The first 16-bytes are known by both the OS and PLIC.  The remainder
  * of the cache line is for use by the OS.
  */
-        u8      xPlicOverflowIntPending;// 0x00 Overflow events are pending
-        u8      xPlicStatus;            // 0x01 DedicatedIo or DedicatedLp or NotUsed
-        u16     xSlicLogicalProcIndex;  // 0x02 Logical Proc Index for correlation
-        u8      xPlicRsvd[12];          // 0x04
-        char    *xSlicCurEventPtr;      // 0x10
-        char    *xSlicLastValidEventPtr; // 0x18
-        char    *xSlicEventStackPtr;    // 0x20
-        u8      xIndex;                 // 0x28 unique sequential index.
-        u8      xSlicRsvd[3];           // 0x29-2b
-        spinlock_t      lock;
+        u8              hq_overflow_pending;    /* 0x00 Overflow events are pending */
+        u8              hq_status;              /* 0x01 DedicatedIo or DedicatedLp or NotUsed */
+        u16             hq_proc_index;          /* 0x02 Logical Proc Index for correlation */
+        u8              hq_reserved1[12];       /* 0x04 */
+        char            *hq_current_event;      /* 0x10 */
+        char            *hq_last_event;         /* 0x18 */
+        char            *hq_event_stack;        /* 0x20 */
+        u8              hq_index;               /* 0x28 unique sequential index. */
+        u8              hq_reserved2[3];        /* 0x29-2b */
+        spinlock_t      hq_lock;
 };
 
 extern struct hvlpevent_queue hvlpevent_queue;
diff --git a/include/asm-powerpc/kdebug.h b/include/asm-powerpc/kdebug.h
index c01786ab5fa6..532bfee934f4 100644
--- a/include/asm-powerpc/kdebug.h
+++ b/include/asm-powerpc/kdebug.h
@@ -18,6 +18,8 @@ struct die_args {
 
 extern int register_die_notifier(struct notifier_block *);
 extern int unregister_die_notifier(struct notifier_block *);
+extern int register_page_fault_notifier(struct notifier_block *);
+extern int unregister_page_fault_notifier(struct notifier_block *);
 extern struct atomic_notifier_head powerpc_die_chain;
 
 /* Grossly misnamed. */
diff --git a/include/asm-powerpc/kdump.h b/include/asm-powerpc/kdump.h
index a87aed00d61f..dc1574c945f8 100644
--- a/include/asm-powerpc/kdump.h
+++ b/include/asm-powerpc/kdump.h
@@ -1,13 +1,40 @@
 #ifndef _PPC64_KDUMP_H
 #define _PPC64_KDUMP_H
 
+/* Kdump kernel runs at 32 MB, change at your peril. */
+#define KDUMP_KERNELBASE        0x2000000
+
 /* How many bytes to reserve at zero for kdump. The reserve limit should
- * be greater or equal to the trampoline's end address. */
+ * be greater or equal to the trampoline's end address.
+ * Reserve to the end of the FWNMI area, see head_64.S */
 #define KDUMP_RESERVE_LIMIT     0x8000
 
+#ifdef CONFIG_CRASH_DUMP
+
+#define PHYSICAL_START  KDUMP_KERNELBASE
 #define KDUMP_TRAMPOLINE_START  0x0100
 #define KDUMP_TRAMPOLINE_END    0x3000
 
-extern void kdump_setup(void);
+#define KDUMP_MIN_TCE_ENTRIES   2048
+
+#else /* !CONFIG_CRASH_DUMP */
+
+#define PHYSICAL_START  0x0
+
+#endif /* CONFIG_CRASH_DUMP */
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_CRASH_DUMP
+
+extern void reserve_kdump_trampoline(void);
+extern void setup_kdump_trampoline(void);
+
+#else /* !CONFIG_CRASH_DUMP */
+
+static inline void reserve_kdump_trampoline(void) { ; }
+static inline void setup_kdump_trampoline(void) { ; }
+
+#endif /* CONFIG_CRASH_DUMP */
+#endif /* __ASSEMBLY__ */
 
 #endif /* __PPC64_KDUMP_H */
diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h
index 6a2af2f6853b..8f7fd5cfec34 100644
--- a/include/asm-powerpc/kexec.h
+++ b/include/asm-powerpc/kexec.h
@@ -31,9 +31,10 @@
 #define KEXEC_ARCH KEXEC_ARCH_PPC
 #endif
 
+#ifndef __ASSEMBLY__
+
 #ifdef CONFIG_KEXEC
 
-#ifndef __ASSEMBLY__
 #ifdef __powerpc64__
 /*
  * This function is responsible for capturing register states if coming
@@ -111,9 +112,13 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
 #ifdef __powerpc64__
 extern void kexec_smp_wait(void);       /* get and clear naca physid, wait for
                                           master to copy new code to 0 */
-extern void __init kexec_setup(void);
 extern int crashing_cpu;
 extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
+extern cpumask_t cpus_in_sr;
+static inline int kexec_sr_activated(int cpu)
+{
+        return cpu_isset(cpu,cpus_in_sr);
+}
 #endif /* __powerpc64 __ */
 
 struct kimage;
@@ -123,8 +128,22 @@ extern int default_machine_kexec_prepare(struct kimage *image);
 extern void default_machine_crash_shutdown(struct pt_regs *regs);
 
 extern void machine_kexec_simple(struct kimage *image);
+extern void crash_kexec_secondary(struct pt_regs *regs);
+extern int overlaps_crashkernel(unsigned long start, unsigned long size);
+extern void reserve_crashkernel(void);
+
+#else /* !CONFIG_KEXEC */
+static inline int kexec_sr_activated(int cpu) { return 0; }
+static inline void crash_kexec_secondary(struct pt_regs *regs) { }
+
+static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
+{
+        return 0;
+}
+
+static inline void reserve_crashkernel(void) { ; }
 
-#endif /* ! __ASSEMBLY__ */
 #endif /* CONFIG_KEXEC */
+#endif /* ! __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_KEXEC_H */
diff --git a/include/asm-powerpc/kprobes.h b/include/asm-powerpc/kprobes.h
index f466bc804f41..2d0af52c823d 100644
--- a/include/asm-powerpc/kprobes.h
+++ b/include/asm-powerpc/kprobes.h
@@ -50,6 +50,8 @@ typedef unsigned int kprobe_opcode_t;
                         IS_TWI(instr) || IS_TDI(instr))
 
 #define ARCH_SUPPORTS_KRETPROBES
+#define  ARCH_INACTIVE_KPROBE_COUNT 1
+
 void kretprobe_trampoline(void);
 extern void arch_remove_kprobe(struct kprobe *p);
 
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index 3e7d37aa4a6d..c17c13742401 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -81,6 +81,8 @@ struct machdep_calls {
         void            (*tce_free)(struct iommu_table *tbl,
                                     long index,
                                     long npages);
+        unsigned long   (*tce_get)(struct iommu_table *tbl,
+                                    long index);
         void            (*tce_flush)(struct iommu_table *tbl);
         void            (*iommu_dev_setup)(struct pci_dev *dev);
         void            (*iommu_bus_setup)(struct pci_bus *bus);
@@ -95,7 +97,7 @@ struct machdep_calls {
         void            (*show_percpuinfo)(struct seq_file *m, int i);
 
         void            (*init_IRQ)(void);
-        int             (*get_irq)(struct pt_regs *);
+        unsigned int    (*get_irq)(struct pt_regs *);
 #ifdef CONFIG_KEXEC
         void            (*kexec_cpu_down)(int crash_shutdown, int secondary);
 #endif
@@ -237,6 +239,11 @@ struct machdep_calls {
          */
         void (*machine_kexec)(struct kimage *image);
 #endif /* CONFIG_KEXEC */
+
+#ifdef CONFIG_PCI_MSI
+        int (*enable_msi)(struct pci_dev *pdev);
+        void (*disable_msi)(struct pci_dev *pdev);
+#endif /* CONFIG_PCI_MSI */
 };
 
 extern void power4_idle(void);
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index 31f721994bd8..c3fc7a28e3cd 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -96,6 +96,8 @@ extern char initial_stab[];
 #define HPTE_R_FLAGS            ASM_CONST(0x00000000000003ff)
 #define HPTE_R_PP               ASM_CONST(0x0000000000000003)
 #define HPTE_R_N                ASM_CONST(0x0000000000000004)
+#define HPTE_R_C                ASM_CONST(0x0000000000000080)
+#define HPTE_R_R                ASM_CONST(0x0000000000000100)
 
 /* Values for PP (assumes Ks=0, Kp=1) */
 /* pp0 will always be 0 for linux     */
@@ -163,6 +165,16 @@ struct mmu_psize_def
 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 extern int mmu_linear_psize;
 extern int mmu_virtual_psize;
+extern int mmu_vmalloc_psize;
+extern int mmu_io_psize;
+
+/*
+ * If the processor supports 64k normal pages but not 64k cache
+ * inhibited pages, we have to be prepared to switch processes
+ * to use 4k pages when they create cache-inhibited mappings.
+ * If this is the case, mmu_ci_restrictions will be set to 1.
+ */
+extern int mmu_ci_restrictions;
 
 #ifdef CONFIG_HUGETLB_PAGE
 /*
@@ -226,7 +238,6 @@ extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
                           unsigned long ea, unsigned long vsid, int local,
                           unsigned long trap);
 
-extern void htab_finish_init(void);
 extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
                              unsigned long pstart, unsigned long mode,
                              int psize);
@@ -254,6 +265,7 @@ extern long iSeries_hpte_insert(unsigned long hpte_group,
 
 extern void stabs_alloc(void);
 extern void slb_initialize(void);
+extern void slb_flush_and_rebolt(void);
 extern void stab_initialize(unsigned long stab);
 
 #endif /* __ASSEMBLY__ */
@@ -357,9 +369,12 @@ typedef unsigned long mm_context_id_t;
 
 typedef struct {
         mm_context_id_t id;
+        u16 user_psize;                 /* page size index */
+        u16 sllp;                       /* SLB entry page size encoding */
 #ifdef CONFIG_HUGETLB_PAGE
         u16 low_htlb_areas, high_htlb_areas;
 #endif
+        unsigned long vdso_base;
 } mm_context_t;
 
 
diff --git a/include/asm-powerpc/mmu_context.h b/include/asm-powerpc/mmu_context.h
index 1b8a25fd48f3..083ac917bd29 100644
--- a/include/asm-powerpc/mmu_context.h
+++ b/include/asm-powerpc/mmu_context.h
@@ -20,20 +20,18 @@
  * 2 of the License, or (at your option) any later version.
  */
 
-/*
- * Getting into a kernel thread, there is no valid user segment, mark
- * paca->pgdir NULL so that SLB miss on user addresses will fault
- */
 static inline void enter_lazy_tlb(struct mm_struct *mm,
                                   struct task_struct *tsk)
 {
-#ifdef CONFIG_PPC_64K_PAGES
-        get_paca()->pgdir = NULL;
-#endif /* CONFIG_PPC_64K_PAGES */
 }
 
+/*
+ * The proto-VSID space has 2^35 - 1 segments available for user mappings.
+ * Each segment contains 2^28 bytes.  Each context maps 2^44 bytes,
+ * so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
+ */
 #define NO_CONTEXT      0
-#define MAX_CONTEXT     (0x100000-1)
+#define MAX_CONTEXT     ((1UL << 19) - 1)
 
 extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 extern void destroy_context(struct mm_struct *mm);
@@ -52,13 +50,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
                 cpu_set(smp_processor_id(), next->cpu_vm_mask);
 
         /* No need to flush userspace segments if the mm doesnt change */
-#ifdef CONFIG_PPC_64K_PAGES
-        if (prev == next && get_paca()->pgdir == next->pgd)
-                return;
-#else
         if (prev == next)
                 return;
-#endif /* CONFIG_PPC_64K_PAGES */
 
 #ifdef CONFIG_ALTIVEC
         if (cpu_has_feature(CPU_FTR_ALTIVEC))
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
new file mode 100644
index 000000000000..f260382739fa
--- /dev/null
+++ b/include/asm-powerpc/mpc86xx.h
@@ -0,0 +1,42 @@
+/*
+ * MPC86xx definitions
+ *
+ * Author: Jeff Brown
+ *
+ * Copyright 2004 Freescale Semiconductor, Inc
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_POWERPC_MPC86xx_H__
+#define __ASM_POWERPC_MPC86xx_H__
+
+#include <asm/mmu.h>
+
+#ifdef CONFIG_PPC_86xx
+
+#define _IO_BASE        isa_io_base
+#define _ISA_MEM_BASE   isa_mem_base
+#ifdef CONFIG_PCI
+#define PCI_DRAM_OFFSET pci_dram_offset
+#else
+#define PCI_DRAM_OFFSET 0
+#endif
+
+#define CPU0_BOOT_RELEASE 0x01000000
+#define CPU1_BOOT_RELEASE 0x02000000
+#define CPU_ALL_RELEASED (CPU0_BOOT_RELEASE | CPU1_BOOT_RELEASE)
+#define MCM_PORT_CONFIG_OFFSET 0x1010
+
+/* Offset from CCSRBAR */
+#define MPC86xx_OPENPIC_OFFSET  (0x40000)
+#define MPC86xx_MCM_OFFSET      (0x00000)
+#define MPC86xx_MCM_SIZE        (0x02000)
+
+#endif /* CONFIG_PPC_86xx */
+#endif /* __ASM_POWERPC_MPC86xx_H__ */
+#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index 6b9e78142f4f..eb241c99c457 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -22,6 +22,10 @@
 #define         MPIC_GREG_GCONF_8259_PTHROU_DIS         0x20000000
 #define         MPIC_GREG_GCONF_BASE_MASK               0x000fffff
 #define MPIC_GREG_GLOBAL_CONF_1         0x00030
+#define         MPIC_GREG_GLOBAL_CONF_1_SIE             0x08000000
+#define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK  0x70000000
+#define         MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(r)    \
+                        (((r) << 28) & MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK)
 #define MPIC_GREG_VENDOR_0              0x00040
 #define MPIC_GREG_VENDOR_1              0x00050
 #define MPIC_GREG_VENDOR_2              0x00060
@@ -110,9 +114,6 @@
 #define MPIC_VEC_TIMER_1        248
 #define MPIC_VEC_TIMER_0        247
 
-/* Type definition of the cascade handler */
-typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
-
 #ifdef CONFIG_MPIC_BROKEN_U3
 /* Fixup table entry */
 struct mpic_irq_fixup
@@ -128,10 +129,19 @@ struct mpic_irq_fixup
 /* The instance data of a given MPIC */
 struct mpic
 {
+        /* The device node of the interrupt controller */
+        struct device_node      *of_node;
+
+        /* The remapper for this MPIC */
+        struct irq_host         *irqhost;
+
         /* The "linux" controller struct */
-        hw_irq_controller       hc_irq;
+        struct irq_chip         hc_irq;
+#ifdef CONFIG_MPIC_BROKEN_U3
+        struct irq_chip         hc_ht_irq;
+#endif
 #ifdef CONFIG_SMP
-        hw_irq_controller       hc_ipi;
+        struct irq_chip         hc_ipi;
 #endif
         const char              *name;
         /* Flags */
@@ -140,20 +150,12 @@ struct mpic
         unsigned int            isu_size;
         unsigned int            isu_shift;
         unsigned int            isu_mask;
-        /* Offset of irq vector numbers */
-        unsigned int            irq_offset;     
         unsigned int            irq_count;
-        /* Offset of ipi vector numbers */
-        unsigned int            ipi_offset;
         /* Number of sources */
         unsigned int            num_sources;
         /* Number of CPUs */
         unsigned int            num_cpus;
-        /* cascade handler */
-        mpic_cascade_t          cascade;
-        void                    *cascade_data;
-        unsigned int            cascade_vec;
-        /* senses array */
+        /* default senses array */
         unsigned char           *senses;
         unsigned int            senses_count;
 
@@ -209,14 +211,11 @@ struct mpic
  * The values in the array start at the first source of the MPIC,
  * that is senses[0] correspond to linux irq "irq_offset".
  */
-extern struct mpic *mpic_alloc(unsigned long phys_addr,
+extern struct mpic *mpic_alloc(struct device_node *node,
+                               unsigned long phys_addr,
                                unsigned int flags,
                                unsigned int isu_size,
-                               unsigned int irq_offset,
                                unsigned int irq_count,
-                               unsigned int ipi_offset,
-                               unsigned char *senses,
-                               unsigned int senses_num,
                                const char *name);
 
 /* Assign ISUs, to call before mpic_init()
@@ -228,22 +227,27 @@ extern struct mpic *mpic_alloc(unsigned long phys_addr,
 extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
                             unsigned long phys_addr);
 
+/* Set default sense codes
+ *
+ * @mpic:       controller
+ * @senses:     array of sense codes
+ * @count:      size of above array
+ *
+ * Optionally provide an array (indexed on hardware interrupt numbers
+ * for this MPIC) of default sense codes for the chip. Those are linux
+ * sense codes IRQ_TYPE_*
+ *
+ * The driver gets ownership of the pointer, don't dispose of it or
+ * anything like that. __init only.
+ */
+extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
+
+
 /* Initialize the controller. After this has been called, none of the above
  * should be called again for this mpic
  */
 extern void mpic_init(struct mpic *mpic);
 
-/* Setup a cascade. Currently, only one cascade is supported this
- * way, though you can always do a normal request_irq() and add
- * other cascades this way. You should call this _after_ having
- * added all the ISUs
- *
- * @irq_no:     "linux" irq number of the cascade (that is offset'ed vector)
- * @handler:    cascade handler function
- */
-extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
-                               void *data);
-
 /*
  * All of the following functions must only be used after the
  * ISUs have been assigned and the controller fully initialized
@@ -280,12 +284,15 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
 void smp_mpic_message_pass(int target, int msg);
 
 /* Fetch interrupt from a given mpic */
-extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
+extern unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
 /* This one gets to the primary mpic */
-extern int mpic_get_irq(struct pt_regs *regs);
+extern unsigned int mpic_get_irq(struct pt_regs *regs);
+
+/* Set the EPIC clock ratio */
+void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio);
 
-/* global mpic for pSeries */
-extern struct mpic *pSeries_mpic;
+/* Enable/Disable EPIC serial interrupt mode */
+void mpic_set_serial_int(struct mpic *mpic, int enable);
 
 #endif /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_MPIC_H */
diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h
index 6249a7c39639..c5c0b0b3cd52 100644
--- a/include/asm-powerpc/of_device.h
+++ b/include/asm-powerpc/of_device.h
@@ -9,7 +9,7 @@
 /*
  * The of_platform_bus_type is a bus type used by drivers that do not
  * attach to a macio or similar bus but still use OF probing
- * mecanism
+ * mechanism
  */
 extern struct bus_type of_platform_bus_type;
 
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
index 3c6f644d49b4..2d4585f06209 100644
--- a/include/asm-powerpc/paca.h
+++ b/include/asm-powerpc/paca.h
@@ -78,11 +78,9 @@ struct paca_struct {
         u64 exmc[10];           /* used for machine checks */
         u64 exslb[10];          /* used for SLB/segment table misses
                                  * on the linear mapping */
-#ifdef CONFIG_PPC_64K_PAGES
-        pgd_t *pgdir;
-#endif /* CONFIG_PPC_64K_PAGES */
 
         mm_context_t context;
+        u16 vmalloc_sllp;
         u16 slb_cache[SLB_CACHE_ENTRIES];
         u16 slb_cache_ptr;
 
diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h
index f0469b961359..fb597b37c2a2 100644
--- a/include/asm-powerpc/page.h
+++ b/include/asm-powerpc/page.h
@@ -12,6 +12,7 @@
 
 #ifdef __KERNEL__
 #include <asm/asm-compat.h>
+#include <asm/kdump.h>
 
 /*
  * On PPC32 page size is 4K. For PPC64 we support either 4K or 64K software
@@ -51,13 +52,6 @@
  * If you want to test if something's a kernel address, use is_kernel_addr().
  */
 
-#ifdef CONFIG_CRASH_DUMP
-/* Kdump kernel runs at 32 MB, change at your peril. */
-#define PHYSICAL_START  0x2000000
-#else
-#define PHYSICAL_START  0x0
-#endif
-
 #define PAGE_OFFSET     ASM_CONST(CONFIG_KERNEL_START)
 #define KERNELBASE      (PAGE_OFFSET + PHYSICAL_START)
 
@@ -197,6 +191,9 @@ extern void copy_user_page(void *to, void *from, unsigned long vaddr,
                 struct page *p);
 extern int page_is_ram(unsigned long pfn);
 
+struct vm_area_struct;
+extern const char *arch_vma_name(struct vm_area_struct *vma);
+
 #include <asm-generic/memory_model.h>
 #endif /* __ASSEMBLY__ */
 
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index 38de92d41a14..4f55573762bb 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -6,6 +6,7 @@
 #include <asm-ppc/pci-bridge.h>
 #else
 
+#include <linux/config.h>
 #include <linux/pci.h>
 #include <linux/list.h>
 
@@ -22,6 +23,7 @@
 struct pci_controller {
         struct pci_bus *bus;
         char is_dynamic;
+        int node;
         void *arch_data;
         struct list_head list_node;
 
@@ -78,12 +80,6 @@ struct pci_dn {
         struct  iommu_table *iommu_table;       /* for phb's or bridges */
         struct  pci_dev *pcidev;        /* back-pointer to the pci device */
         struct  device_node *node;      /* back-pointer to the device_node */
-#ifdef CONFIG_PPC_ISERIES
-        struct  list_head Device_List;
-        int     Irq;                    /* Assigned IRQ */
-        int     Flags;                  /* Possible flags(disable/bist)*/
-        u8      LogicalSlot;            /* Hv Slot Index for Tces */
-#endif
         u32     config_space[16];       /* saved PCI config space */
 };
 
@@ -171,6 +167,12 @@ static inline unsigned long pci_address_to_pio(phys_addr_t address)
 #define PCI_PROBE_NORMAL        0       /* Do normal PCI probing */
 #define PCI_PROBE_DEVTREE       1       /* Instantiate from device tree */
 
+#ifdef CONFIG_NUMA
+#define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = (NODE))
+#else
+#define PHB_SET_NODE(PHB, NODE)         ((PHB)->node = -1)
+#endif
+
 #endif /* CONFIG_PPC64 */
 #endif /* __KERNEL__ */
 #endif
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
index 5d2c9e6c4be2..46afd29b904e 100644
--- a/include/asm-powerpc/pci.h
+++ b/include/asm-powerpc/pci.h
@@ -242,7 +242,7 @@ extern pgprot_t	pci_phys_mem_access_prot(struct file *file,
 #define HAVE_ARCH_PCI_RESOURCE_TO_USER
 extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
                                  const struct resource *rsrc,
-                                 u64 *start, u64 *end);
+                                 resource_size_t *start, resource_size_t *end);
 #endif /* CONFIG_PPC_MULTIPLATFORM || CONFIG_PPC32 */
 
 #endif  /* __KERNEL__ */
diff --git a/include/asm-powerpc/percpu.h b/include/asm-powerpc/percpu.h
index 184a7a4d2fdf..2f2e3024fa61 100644
--- a/include/asm-powerpc/percpu.h
+++ b/include/asm-powerpc/percpu.h
@@ -14,6 +14,7 @@
 
 #define __per_cpu_offset(cpu) (paca[cpu].data_offset)
 #define __my_cpu_offset() get_paca()->data_offset
+#define per_cpu_offset(x) (__per_cpu_offset(x))
 
 /* Separate out the type, so (int[3], foo) works. */
 #define DEFINE_PER_CPU(type, name) \
@@ -22,6 +23,7 @@
 /* var is in discarded region: offset to particular copy we want */
 #define per_cpu(var, cpu) (*RELOC_HIDE(&per_cpu__##var, __per_cpu_offset(cpu)))
 #define __get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, __my_cpu_offset()))
+#define __raw_get_cpu_var(var) (*RELOC_HIDE(&per_cpu__##var, __my_cpu_offset()))
 
 /* A macro to avoid #include hell... */
 #define percpu_modcopy(pcpudst, src, size)                      \
@@ -41,6 +43,7 @@ extern void setup_per_cpu_areas(void);
 
 #define per_cpu(var, cpu)                       (*((void)(cpu), &per_cpu__##var))
 #define __get_cpu_var(var)                      per_cpu__##var
+#define __raw_get_cpu_var(var)                  per_cpu__##var
 
 #endif  /* SMP */
 
diff --git a/include/asm-powerpc/pgtable-4k.h b/include/asm-powerpc/pgtable-4k.h
index b2e18629932a..e7036155672e 100644
--- a/include/asm-powerpc/pgtable-4k.h
+++ b/include/asm-powerpc/pgtable-4k.h
@@ -78,6 +78,8 @@
 
 #define pte_iterate_hashed_end() } while(0)
 
+#define pte_pagesize_index(pte) MMU_PAGE_4K
+
 /*
  * 4-level page tables related bits
  */
diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h
index 653915014dcd..4b7126c53f37 100644
--- a/include/asm-powerpc/pgtable-64k.h
+++ b/include/asm-powerpc/pgtable-64k.h
@@ -90,6 +90,8 @@
 
 #define pte_iterate_hashed_end() } while(0); } } while(0)
 
+#define pte_pagesize_index(pte) \
+        (((pte) & _PAGE_COMBO)? MMU_PAGE_4K: MMU_PAGE_64K)
 
 #endif /*  __ASSEMBLY__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/pgtable.h b/include/asm-powerpc/pgtable.h
index 964e312a1ffc..8dbf5ad8150f 100644
--- a/include/asm-powerpc/pgtable.h
+++ b/include/asm-powerpc/pgtable.h
@@ -46,8 +46,8 @@ struct mm_struct;
 /*
  * Define the address range of the vmalloc VM area.
  */
-#define VMALLOC_START (0xD000000000000000ul)
-#define VMALLOC_SIZE  (0x80000000000UL)
+#define VMALLOC_START ASM_CONST(0xD000000000000000)
+#define VMALLOC_SIZE  ASM_CONST(0x80000000000)
 #define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)
 
 /*
@@ -412,12 +412,6 @@ static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
                 flush_tlb_pending();
         }
         pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
-
-#ifdef CONFIG_PPC_64K_PAGES
-        if (mmu_virtual_psize != MMU_PAGE_64K)
-                pte = __pte(pte_val(pte) | _PAGE_COMBO);
-#endif /* CONFIG_PPC_64K_PAGES */
-
         *ptep = pte;
 }
 
diff --git a/include/asm-powerpc/pmac_pfunc.h b/include/asm-powerpc/pmac_pfunc.h
index cef61304ffc2..1330d6a58c57 100644
--- a/include/asm-powerpc/pmac_pfunc.h
+++ b/include/asm-powerpc/pmac_pfunc.h
@@ -205,7 +205,7 @@ extern void pmf_do_irq(struct pmf_function *func);
  *
  * The args array contains as many arguments as is required by the function,
  * this is dependent on the function you are calling, unfortunately Apple
- * mecanism provides no way to encode that so you have to get it right at
+ * mechanism provides no way to encode that so you have to get it right at
  * the call site. Some functions require no args, in which case, you can
  * pass NULL.
  *
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
index 93f83efeb310..22e54a2a6604 100644
--- a/include/asm-powerpc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -149,11 +149,11 @@ struct thread_struct {
                 unsigned int val;       /* Floating point status */
         } fpscr;
         int             fpexc_mode;     /* floating-point exception mode */
+        unsigned int    align_ctl;      /* alignment handling control */
 #ifdef CONFIG_PPC64
         unsigned long   start_tb;       /* Start purr when proc switched in */
         unsigned long   accum_tb;       /* Total accumilated purr for process */
 #endif
-        unsigned long   vdso_base;      /* base of the vDSO library */
         unsigned long   dabr;           /* Data address breakpoint register */
 #ifdef CONFIG_ALTIVEC
         /* Complete AltiVec register set */
@@ -190,7 +190,7 @@ struct thread_struct {
         .fs = KERNEL_DS, \
         .fpr = {0}, \
         .fpscr = { .val = 0, }, \
-        .fpexc_mode = MSR_FE0|MSR_FE1, \
+        .fpexc_mode = 0, \
 }
 #endif
 
@@ -212,6 +212,18 @@ unsigned long get_wchan(struct task_struct *p);
 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 
+#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
+#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
+
+extern int get_endian(struct task_struct *tsk, unsigned long adr);
+extern int set_endian(struct task_struct *tsk, unsigned int val);
+
+#define GET_UNALIGN_CTL(tsk, adr)       get_unalign_ctl((tsk), (adr))
+#define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
+
+extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
+extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
+
 static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 {
         return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index f4e2ca6fd53f..b095a285c84b 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -64,11 +64,6 @@ struct boot_param_header
 typedef u32 phandle;
 typedef u32 ihandle;
 
-struct interrupt_info {
-        int     line;
-        int     sense;          /* +ve/-ve logic, edge or level, etc. */
-};
-
 struct property {
         char    *name;
         int     length;
@@ -81,8 +76,6 @@ struct device_node {
         char    *type;
         phandle node;
         phandle linux_phandle;
-        int     n_intrs;
-        struct  interrupt_info *intrs;
         char    *full_name;
 
         struct  property *properties;
@@ -167,8 +160,8 @@ extern void unflatten_device_tree(void);
 extern void early_init_devtree(void *);
 extern int device_is_compatible(struct device_node *device, const char *);
 extern int machine_is_compatible(const char *compat);
-extern unsigned char *get_property(struct device_node *node, const char *name,
-                                   int *lenp);
+extern void *get_property(struct device_node *node, const char *name,
+                int *lenp);
 extern void print_properties(struct device_node *node);
 extern int prom_n_addr_cells(struct device_node* np);
 extern int prom_n_size_cells(struct device_node* np);
@@ -204,6 +197,15 @@ extern int release_OF_resource(struct device_node* node, int index);
  */
 
 
+/* Helper to read a big number */
+static inline u64 of_read_number(u32 *cell, int size)
+{
+        u64 r = 0;
+        while (size--)
+                r = (r << 32) | *(cell++);
+        return r;
+}
+
 /* Translate an OF address block into a CPU physical address
  */
 #define OF_BAD_ADDR     ((u64)-1)
@@ -229,7 +231,94 @@ extern int of_address_to_resource(struct device_node *dev, int index,
 extern int of_pci_address_to_resource(struct device_node *dev, int bar,
                                       struct resource *r);
 
+/* Parse the ibm,dma-window property of an OF node into the busno, phys and
+ * size parameters.
+ */
+void of_parse_dma_window(struct device_node *dn, unsigned char *dma_window_prop,
+                unsigned long *busno, unsigned long *phys, unsigned long *size);
+
 extern void kdump_move_device_tree(void);
 
+/* CPU OF node matching */
+struct device_node *of_get_cpu_node(int cpu, unsigned int *thread);
+
+
+/*
+ * OF interrupt mapping
+ */
+
+/* This structure is returned when an interrupt is mapped. The controller
+ * field needs to be put() after use
+ */
+
+#define OF_MAX_IRQ_SPEC          4 /* We handle specifiers of at most 4 cells */
+
+struct of_irq {
+        struct device_node *controller; /* Interrupt controller node */
+        u32 size;                       /* Specifier size */
+        u32 specifier[OF_MAX_IRQ_SPEC]; /* Specifier copy */
+};
+
+/***
+ * of_irq_map_init - Initialize the irq remapper
+ * @flags:      flags defining workarounds to enable
+ *
+ * Some machines have bugs in the device-tree which require certain workarounds
+ * to be applied. Call this before any interrupt mapping attempts to enable
+ * those workarounds.
+ */
+#define OF_IMAP_OLDWORLD_MAC    0x00000001
+#define OF_IMAP_NO_PHANDLE      0x00000002
+
+extern void of_irq_map_init(unsigned int flags);
+
+/***
+ * of_irq_map_raw - Low level interrupt tree parsing
+ * @parent:     the device interrupt parent
+ * @intspec:    interrupt specifier ("interrupts" property of the device)
+ * @addr:       address specifier (start of "reg" property of the device)
+ * @out_irq:    structure of_irq filled by this function
+ *
+ * Returns 0 on success and a negative number on error
+ *
+ * This function is a low-level interrupt tree walking function. It
+ * can be used to do a partial walk with synthetized reg and interrupts
+ * properties, for example when resolving PCI interrupts when no device
+ * node exist for the parent.
+ *
+ */
+
+extern int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 *addr,
+                          struct of_irq *out_irq);
+
+
+/***
+ * of_irq_map_one - Resolve an interrupt for a device
+ * @device:     the device whose interrupt is to be resolved
+ * @index:      index of the interrupt to resolve
+ * @out_irq:    structure of_irq filled by this function
+ *
+ * This function resolves an interrupt, walking the tree, for a given
+ * device-tree node. It's the high level pendant to of_irq_map_raw().
+ * It also implements the workarounds for OldWolrd Macs.
+ */
+extern int of_irq_map_one(struct device_node *device, int index,
+                          struct of_irq *out_irq);
+
+/***
+ * of_irq_map_pci - Resolve the interrupt for a PCI device
+ * @pdev:       the device whose interrupt is to be resolved
+ * @out_irq:    structure of_irq filled by this function
+ *
+ * This function resolves the PCI interrupt for a given PCI device. If a
+ * device-node exists for a given pci_dev, it will use normal OF tree
+ * walking. If not, it will implement standard swizzling and walk up the
+ * PCI tree until an device-node is found, at which point it will finish
+ * resolving using the OF tree walking.
+ */
+struct pci_dev;
+extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
+
+
 #endif /* __KERNEL__ */
 #endif /* _POWERPC_PROM_H */
diff --git a/include/asm-powerpc/ptrace.h b/include/asm-powerpc/ptrace.h
index 9c550b314823..dc4cb9cc73a1 100644
--- a/include/asm-powerpc/ptrace.h
+++ b/include/asm-powerpc/ptrace.h
@@ -229,13 +229,13 @@ do {									      \
 #define PTRACE_GET_DEBUGREG     25
 #define PTRACE_SET_DEBUGREG     26
 
-#ifdef __powerpc64__
 /* Additional PTRACE requests implemented on PowerPC. */
 #define PPC_PTRACE_GETREGS      0x99    /* Get GPRs 0 - 31 */
 #define PPC_PTRACE_SETREGS      0x98    /* Set GPRs 0 - 31 */
 #define PPC_PTRACE_GETFPREGS    0x97    /* Get FPRs 0 - 31 */
 #define PPC_PTRACE_SETFPREGS    0x96    /* Set FPRs 0 - 31 */
 
+#ifdef __powerpc64__
 /* Calls to trace a 64bit program from a 32bit program */
 #define PPC_PTRACE_PEEKTEXT_3264 0x95
 #define PPC_PTRACE_PEEKDATA_3264 0x94
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index bd467bf5cf5a..cf73475a0c69 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -93,8 +93,8 @@
 #define MSR_LE          __MASK(MSR_LE_LG)       /* Little Endian */
 
 #ifdef CONFIG_PPC64
-#define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
-#define MSR_KERNEL      MSR_ | MSR_SF | MSR_HV
+#define MSR_            MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF |MSR_HV
+#define MSR_KERNEL      MSR_ | MSR_SF
 
 #define MSR_USER32      MSR_ | MSR_PR | MSR_EE
 #define MSR_USER64      MSR_USER32 | MSR_SF
@@ -153,7 +153,7 @@
 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
 #define   DABR_TRANSLATION      (1UL << 2)
 #define SPRN_DAR        0x013   /* Data Address Register */
-#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
+#define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 #define   DSISR_NOHPTE          0x40000000      /* no translation found */
 #define   DSISR_PROTFAULT       0x08000000      /* protection fault */
 #define   DSISR_ISSTORE         0x02000000      /* access was a store */
@@ -258,16 +258,16 @@
 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
 #define SPRN_HID4       0x3F4           /* 970 HID4 */
 #define SPRN_HID5       0x3F6           /* 970 HID5 */
-#define SPRN_HID6       0x3F9   /* BE HID 6 */
-#define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
-#define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
-#define SPRN_TSC_CELL   0x399   /* Thread switch control on Cell */
-#define   TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
-#define   TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
-#define   TSC_CELL_EE_ENABLE    0x100000 /* External Interrupt */
-#define   TSC_CELL_EE_BOOST     0x080000 /* External Interrupt Boost */
-#define SPRN_TSC        0x3FD   /* Thread switch control on others */
-#define SPRN_TST        0x3FC   /* Thread switch timeout on others */
+#define SPRN_HID6       0x3F9   /* BE HID 6 */
+#define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
+#define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
+#define SPRN_TSC_CELL   0x399   /* Thread switch control on Cell */
+#define   TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
+#define   TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
+#define   TSC_CELL_EE_ENABLE    0x100000 /* External Interrupt */
+#define   TSC_CELL_EE_BOOST     0x080000 /* External Interrupt Boost */
+#define SPRN_TSC        0x3FD   /* Thread switch control on others */
+#define SPRN_TST        0x3FC   /* Thread switch timeout on others */
 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
 #define SPRN_IAC1       0x3F4           /* Instruction Address Compare 1 */
 #define SPRN_IAC2       0x3F5           /* Instruction Address Compare 2 */
@@ -362,7 +362,7 @@
 #endif
 #define SPRN_PTEHI      0x3D5   /* 981 7450 PTE HI word (S/W TLB load) */
 #define SPRN_PTELO      0x3D6   /* 982 7450 PTE LO word (S/W TLB load) */
-#define SPRN_PURR       0x135   /* Processor Utilization of Resources Reg */
+#define SPRN_PURR       0x135   /* Processor Utilization of Resources Reg */
 #define SPRN_PVR        0x11F   /* Processor Version Register */
 #define SPRN_RPA        0x3D6   /* Required Physical Address Register */
 #define SPRN_SDA        0x3BF   /* Sampled Data Address Register */
@@ -386,6 +386,8 @@
 #define   SRR1_WAKEMT           0x00280000 /* mtctrl */
 #define   SRR1_WAKEDEC          0x00180000 /* Decrementer interrupt */
 #define   SRR1_WAKETHERM        0x00100000 /* Thermal management interrupt */
+#define SPRN_HSRR0      0x13A   /* Save/Restore Register 0 */
+#define SPRN_HSRR1      0x13B   /* Save/Restore Register 1 */
 
 #ifndef SPRN_SVR
 #define SPRN_SVR        0x11E   /* System Version Register */
@@ -443,6 +445,10 @@
 #define   MMCRA_SIHV    0x10000000UL /* state of MSR HV when SIAR set */
 #define   MMCRA_SIPR    0x08000000UL /* state of MSR PR when SIAR set */
 #define   MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
+#define   POWER6_MMCRA_SIHV   0x0000040000000000ULL
+#define   POWER6_MMCRA_SIPR   0x0000020000000000ULL
+#define   POWER6_MMCRA_THRM     0x00000020UL
+#define   POWER6_MMCRA_OTHER    0x0000000EUL
 #define SPRN_PMC1       787
 #define SPRN_PMC2       788
 #define SPRN_PMC3       789
@@ -495,6 +501,19 @@
 #define MMCR0_PMC2_LOADMISSTIME 0x5
 #endif
 
+/*
+ * An mtfsf instruction with the L bit set. On CPUs that support this a
+ * full 64bits of FPSCR is restored and on other CPUs it is ignored.
+ *
+ * Until binutils gets the new form of mtfsf, hardwire the instruction.
+ */
+#ifdef CONFIG_PPC64
+#define MTFSF_L(REG) \
+        .long (0xfc00058e | ((0xff) << 17) | ((REG) << 11) | (1 << 25))
+#else
+#define MTFSF_L(REG)    mtfsf   0xff, (REG)
+#endif
+
 /* Processor Version Register (PVR) field extraction */
 
 #define PVR_VER(pvr)    (((pvr) >>  16) & 0xFFFF)       /* Version field */
@@ -559,20 +578,20 @@
 
 /* 64-bit processors */
 /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
-#define PV_NORTHSTAR    0x0033
-#define PV_PULSAR       0x0034
-#define PV_POWER4       0x0035
-#define PV_ICESTAR      0x0036
-#define PV_SSTAR        0x0037
-#define PV_POWER4p      0x0038
+#define PV_NORTHSTAR    0x0033
+#define PV_PULSAR       0x0034
+#define PV_POWER4       0x0035
+#define PV_ICESTAR      0x0036
+#define PV_SSTAR        0x0037
+#define PV_POWER4p      0x0038
 #define PV_970          0x0039
-#define PV_POWER5       0x003A
+#define PV_POWER5       0x003A
 #define PV_POWER5p      0x003B
 #define PV_970FX        0x003C
-#define PV_630          0x0040
-#define PV_630p 0x0041
-#define PV_970MP        0x0044
-#define PV_BE           0x0070
+#define PV_630          0x0040
+#define PV_630p 0x0041
+#define PV_970MP        0x0044
+#define PV_BE           0x0070
 
 /*
  * Number of entries in the SLB. If this ever changes we should handle
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
index f43c6835e62a..a33c6acffa61 100644
--- a/include/asm-powerpc/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -24,6 +24,7 @@
 #define RTAS_RMOBUF_MAX (64 * 1024)
 
 /* RTAS return status codes */
+#define RTAS_NOT_SUSPENDABLE    -9004
 #define RTAS_BUSY               -2    /* RTAS Busy */
 #define RTAS_EXTENDED_DELAY_MIN 9900
 #define RTAS_EXTENDED_DELAY_MAX 9905
@@ -177,12 +178,11 @@ extern unsigned long rtas_get_boot_time(void);
 extern void rtas_get_rtc_time(struct rtc_time *rtc_time);
 extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
 
-/* Given an RTAS status code of 9900..9905 compute the hinted delay */
-unsigned int rtas_extended_busy_delay_time(int status);
-static inline int rtas_is_extended_busy(int status)
-{
-        return status >= 9900 && status <= 9909;
-}
+extern unsigned int rtas_busy_delay_time(int status);
+extern unsigned int rtas_busy_delay(int status);
+
+extern int early_init_dt_scan_rtas(unsigned long node,
+                const char *uname, int depth, void *data);
 
 extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
 
diff --git a/include/asm-powerpc/rwsem.h b/include/asm-powerpc/rwsem.h
index 2c2fe9647595..e929145e1e46 100644
--- a/include/asm-powerpc/rwsem.h
+++ b/include/asm-powerpc/rwsem.h
@@ -28,24 +28,11 @@ struct rw_semaphore {
 #define RWSEM_ACTIVE_WRITE_BIAS         (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
         spinlock_t              wait_lock;
         struct list_head        wait_list;
-#if RWSEM_DEBUG
-        int                     debug;
-#endif
 };
 
-/*
- * initialisation
- */
-#if RWSEM_DEBUG
-#define __RWSEM_DEBUG_INIT      , 0
-#else
-#define __RWSEM_DEBUG_INIT      /* */
-#endif
-
 #define __RWSEM_INITIALIZER(name) \
         { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
-          LIST_HEAD_INIT((name).wait_list) \
-          __RWSEM_DEBUG_INIT }
+          LIST_HEAD_INIT((name).wait_list) }
 
 #define DECLARE_RWSEM(name)             \
         struct rw_semaphore name = __RWSEM_INITIALIZER(name)
@@ -60,9 +47,6 @@ static inline void init_rwsem(struct rw_semaphore *sem)
         sem->count = RWSEM_UNLOCKED_VALUE;
         spin_lock_init(&sem->wait_lock);
         INIT_LIST_HEAD(&sem->wait_list);
-#if RWSEM_DEBUG
-        sem->debug = 0;
-#endif
 }
 
 /*
diff --git a/include/asm-powerpc/signal.h b/include/asm-powerpc/signal.h
index a4d8f8648541..a8c7babf4950 100644
--- a/include/asm-powerpc/signal.h
+++ b/include/asm-powerpc/signal.h
@@ -63,7 +63,6 @@ typedef struct {
  * SA_FLAGS values:
  *
  * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
- * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
  * SA_RESTART flag to get restarting signals (which were the default long ago)
  * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
  * SA_RESETHAND clears the handler when the signal is delivered.
@@ -83,7 +82,6 @@ typedef struct {
 
 #define SA_NOMASK       SA_NODEFER
 #define SA_ONESHOT      SA_RESETHAND
-#define SA_INTERRUPT    0x20000000u /* dummy -- ignored */
 
 #define SA_RESTORER     0x04000000U
 
diff --git a/include/asm-powerpc/socket.h b/include/asm-powerpc/socket.h
index e4b8177d4acc..c8b1da50e72d 100644
--- a/include/asm-powerpc/socket.h
+++ b/include/asm-powerpc/socket.h
@@ -55,5 +55,6 @@
 #define SO_ACCEPTCONN           30
 
 #define SO_PEERSEC              31
+#define SO_PASSSEC              34
 
 #endif  /* _ASM_POWERPC_SOCKET_H */
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 95713f397357..c02d105d8294 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -24,8 +24,8 @@
 #define _SPU_H
 #ifdef __KERNEL__
 
-#include <linux/kref.h>
 #include <linux/workqueue.h>
+#include <linux/sysdev.h>
 
 #define LS_SIZE (256 * 1024)
 #define LS_ADDR_MASK (LS_SIZE - 1)
@@ -117,12 +117,12 @@ struct spu {
         struct list_head sched_list;
         int number;
         int nid;
+        unsigned int irqs[3];
         u32 isrc;
         u32 node;
         u64 flags;
         u64 dar;
         u64 dsisr;
-        struct kref kref;
         size_t ls_size;
         unsigned int slb_replace;
         struct mm_struct *mm;
@@ -134,7 +134,6 @@ struct spu {
         int class_0_pending;
         spinlock_t register_lock;
 
-        u32 stop_code;
         void (* wbox_callback)(struct spu *spu);
         void (* ibox_callback)(struct spu *spu);
         void (* stop_callback)(struct spu *spu);
@@ -143,6 +142,8 @@ struct spu {
         char irq_c0[8];
         char irq_c1[8];
         char irq_c2[8];
+
+        struct sys_device sysdev;
 };
 
 struct spu *spu_alloc(void);
@@ -181,29 +182,6 @@ static inline void unregister_spu_syscalls(struct spufs_calls *calls)
 #endif /* MODULE */
 
 
-/* access to priv1 registers */
-void spu_int_mask_and(struct spu *spu, int class, u64 mask);
-void spu_int_mask_or(struct spu *spu, int class, u64 mask);
-void spu_int_mask_set(struct spu *spu, int class, u64 mask);
-u64 spu_int_mask_get(struct spu *spu, int class);
-void spu_int_stat_clear(struct spu *spu, int class, u64 stat);
-u64 spu_int_stat_get(struct spu *spu, int class);
-void spu_int_route_set(struct spu *spu, u64 route);
-u64 spu_mfc_dar_get(struct spu *spu);
-u64 spu_mfc_dsisr_get(struct spu *spu);
-void spu_mfc_dsisr_set(struct spu *spu, u64 dsisr);
-void spu_mfc_sdr_set(struct spu *spu, u64 sdr);
-void spu_mfc_sr1_set(struct spu *spu, u64 sr1);
-u64 spu_mfc_sr1_get(struct spu *spu);
-void spu_mfc_tclass_id_set(struct spu *spu, u64 tclass_id);
-u64 spu_mfc_tclass_id_get(struct spu *spu);
-void spu_tlb_invalidate(struct spu *spu);
-void spu_resource_allocation_groupID_set(struct spu *spu, u64 id);
-u64 spu_resource_allocation_groupID_get(struct spu *spu);
-void spu_resource_allocation_enable_set(struct spu *spu, u64 enable);
-u64 spu_resource_allocation_enable_get(struct spu *spu);
-
-
 /*
  * This defines the Local Store, Problem Area and Privlege Area of an SPU.
  */
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
index ba18d7d4dde2..964c2d38ccb7 100644
--- a/include/asm-powerpc/spu_csa.h
+++ b/include/asm-powerpc/spu_csa.h
@@ -86,10 +86,18 @@ struct spu_lscsa {
         struct spu_reg128 event_mask;
         struct spu_reg128 srr0;
         struct spu_reg128 stopped_status;
-        struct spu_reg128 pad[119];     /* 'ls' must be page-aligned. */
-        unsigned char ls[LS_SIZE];
+
+        /*
+         * 'ls' must be page-aligned on all configurations.
+         * Since we don't want to rely on having the spu-gcc
+         * installed to build the kernel and this structure
+         * is used in the SPU-side code, make it 64k-page
+         * aligned for now.
+         */
+        unsigned char ls[LS_SIZE] __attribute__((aligned(65536)));
 };
 
+#ifndef __SPU__
 /*
  * struct spu_problem_collapsed - condensed problem state area, w/o pads.
  */
@@ -250,6 +258,7 @@ extern int spu_restore(struct spu_state *new, struct spu *spu);
 extern int spu_switch(struct spu_state *prev, struct spu_state *new,
                       struct spu *spu);
 
+#endif /* !__SPU__ */
 #endif /* __KERNEL__ */
 #endif /* !__ASSEMBLY__ */
 #endif /* _SPU_CSA_H_ */
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
new file mode 100644
index 000000000000..300c458b6d06
--- /dev/null
+++ b/include/asm-powerpc/spu_priv1.h
@@ -0,0 +1,182 @@
+/*
+ * Defines an spu hypervisor abstraction layer.
+ *
+ *  Copyright 2006 Sony Corp.
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#if !defined(_SPU_PRIV1_H)
+#define _SPU_PRIV1_H
+#if defined(__KERNEL__)
+
+struct spu;
+
+/* access to priv1 registers */
+
+struct spu_priv1_ops
+{
+        void (*int_mask_and) (struct spu *spu, int class, u64 mask);
+        void (*int_mask_or) (struct spu *spu, int class, u64 mask);
+        void (*int_mask_set) (struct spu *spu, int class, u64 mask);
+        u64 (*int_mask_get) (struct spu *spu, int class);
+        void (*int_stat_clear) (struct spu *spu, int class, u64 stat);
+        u64 (*int_stat_get) (struct spu *spu, int class);
+        void (*cpu_affinity_set) (struct spu *spu, int cpu);
+        u64 (*mfc_dar_get) (struct spu *spu);
+        u64 (*mfc_dsisr_get) (struct spu *spu);
+        void (*mfc_dsisr_set) (struct spu *spu, u64 dsisr);
+        void (*mfc_sdr_set) (struct spu *spu, u64 sdr);
+        void (*mfc_sr1_set) (struct spu *spu, u64 sr1);
+        u64 (*mfc_sr1_get) (struct spu *spu);
+        void (*mfc_tclass_id_set) (struct spu *spu, u64 tclass_id);
+        u64 (*mfc_tclass_id_get) (struct spu *spu);
+        void (*tlb_invalidate) (struct spu *spu);
+        void (*resource_allocation_groupID_set) (struct spu *spu, u64 id);
+        u64 (*resource_allocation_groupID_get) (struct spu *spu);
+        void (*resource_allocation_enable_set) (struct spu *spu, u64 enable);
+        u64 (*resource_allocation_enable_get) (struct spu *spu);
+};
+
+extern const struct spu_priv1_ops* spu_priv1_ops;
+
+static inline void
+spu_int_mask_and (struct spu *spu, int class, u64 mask)
+{
+        spu_priv1_ops->int_mask_and(spu, class, mask);
+}
+
+static inline void
+spu_int_mask_or (struct spu *spu, int class, u64 mask)
+{
+        spu_priv1_ops->int_mask_or(spu, class, mask);
+}
+
+static inline void
+spu_int_mask_set (struct spu *spu, int class, u64 mask)
+{
+        spu_priv1_ops->int_mask_set(spu, class, mask);
+}
+
+static inline u64
+spu_int_mask_get (struct spu *spu, int class)
+{
+        return spu_priv1_ops->int_mask_get(spu, class);
+}
+
+static inline void
+spu_int_stat_clear (struct spu *spu, int class, u64 stat)
+{
+        spu_priv1_ops->int_stat_clear(spu, class, stat);
+}
+
+static inline u64
+spu_int_stat_get (struct spu *spu, int class)
+{
+        return spu_priv1_ops->int_stat_get (spu, class);
+}
+
+static inline void
+spu_cpu_affinity_set (struct spu *spu, int cpu)
+{
+        spu_priv1_ops->cpu_affinity_set(spu, cpu);
+}
+
+static inline u64
+spu_mfc_dar_get (struct spu *spu)
+{
+        return spu_priv1_ops->mfc_dar_get(spu);
+}
+
+static inline u64
+spu_mfc_dsisr_get (struct spu *spu)
+{
+        return spu_priv1_ops->mfc_dsisr_get(spu);
+}
+
+static inline void
+spu_mfc_dsisr_set (struct spu *spu, u64 dsisr)
+{
+        spu_priv1_ops->mfc_dsisr_set(spu, dsisr);
+}
+
+static inline void
+spu_mfc_sdr_set (struct spu *spu, u64 sdr)
+{
+        spu_priv1_ops->mfc_sdr_set(spu, sdr);
+}
+
+static inline void
+spu_mfc_sr1_set (struct spu *spu, u64 sr1)
+{
+        spu_priv1_ops->mfc_sr1_set(spu, sr1);
+}
+
+static inline u64
+spu_mfc_sr1_get (struct spu *spu)
+{
+        return spu_priv1_ops->mfc_sr1_get(spu);
+}
+
+static inline void
+spu_mfc_tclass_id_set (struct spu *spu, u64 tclass_id)
+{
+        spu_priv1_ops->mfc_tclass_id_set(spu, tclass_id);
+}
+
+static inline u64
+spu_mfc_tclass_id_get (struct spu *spu)
+{
+        return spu_priv1_ops->mfc_tclass_id_get(spu);
+}
+
+static inline void
+spu_tlb_invalidate (struct spu *spu)
+{
+        spu_priv1_ops->tlb_invalidate(spu);
+}
+
+static inline void
+spu_resource_allocation_groupID_set (struct spu *spu, u64 id)
+{
+        spu_priv1_ops->resource_allocation_groupID_set(spu, id);
+}
+
+static inline u64
+spu_resource_allocation_groupID_get (struct spu *spu)
+{
+        return spu_priv1_ops->resource_allocation_groupID_get(spu);
+}
+
+static inline void
+spu_resource_allocation_enable_set (struct spu *spu, u64 enable)
+{
+        spu_priv1_ops->resource_allocation_enable_set(spu, enable);
+}
+
+static inline u64
+spu_resource_allocation_enable_get (struct spu *spu)
+{
+        return spu_priv1_ops->resource_allocation_enable_get(spu);
+}
+
+/* The declarations folowing are put here for convenience
+ * and only intended to be used by the platform setup code
+ * for initializing spu_priv1_ops.
+ */
+
+extern const struct spu_priv1_ops spu_priv1_mmio_ops;
+
+#endif /* __KERNEL__ */
+#endif
diff --git a/include/asm-powerpc/systbl.h b/include/asm-powerpc/systbl.h
new file mode 100644
index 000000000000..eac85ce101b6
--- /dev/null
+++ b/include/asm-powerpc/systbl.h
@@ -0,0 +1,306 @@
+/*
+ * List of powerpc syscalls. For the meaning of the _SPU suffix see
+ * arch/powerpc/platforms/cell/spu_callbacks.c
+ */
+
+SYSCALL(restart_syscall)
+SYSCALL(exit)
+PPC_SYS(fork)
+SYSCALL_SPU(read)
+SYSCALL_SPU(write)
+COMPAT_SYS_SPU(open)
+SYSCALL_SPU(close)
+COMPAT_SYS_SPU(waitpid)
+COMPAT_SYS_SPU(creat)
+SYSCALL_SPU(link)
+SYSCALL_SPU(unlink)
+COMPAT_SYS(execve)
+SYSCALL_SPU(chdir)
+COMPAT_SYS_SPU(time)
+SYSCALL_SPU(mknod)
+SYSCALL_SPU(chmod)
+SYSCALL_SPU(lchown)
+SYSCALL(ni_syscall)
+OLDSYS(stat)
+SYSX_SPU(sys_lseek,ppc32_lseek,sys_lseek)
+SYSCALL_SPU(getpid)
+COMPAT_SYS(mount)
+SYSX(sys_ni_syscall,sys_oldumount,sys_oldumount)
+SYSCALL_SPU(setuid)
+SYSCALL_SPU(getuid)
+COMPAT_SYS_SPU(stime)
+COMPAT_SYS(ptrace)
+SYSCALL_SPU(alarm)
+OLDSYS(fstat)
+COMPAT_SYS(pause)
+COMPAT_SYS(utime)
+SYSCALL(ni_syscall)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(access)
+COMPAT_SYS_SPU(nice)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(sync)
+COMPAT_SYS_SPU(kill)
+SYSCALL_SPU(rename)
+COMPAT_SYS_SPU(mkdir)
+SYSCALL_SPU(rmdir)
+SYSCALL_SPU(dup)
+SYSCALL_SPU(pipe)
+COMPAT_SYS_SPU(times)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(brk)
+SYSCALL_SPU(setgid)
+SYSCALL_SPU(getgid)
+SYSCALL(signal)
+SYSCALL_SPU(geteuid)
+SYSCALL_SPU(getegid)
+SYSCALL(acct)
+SYSCALL(umount)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(ioctl)
+COMPAT_SYS_SPU(fcntl)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(setpgid)
+SYSCALL(ni_syscall)
+SYSX(sys_ni_syscall,sys_olduname, sys_olduname)
+COMPAT_SYS_SPU(umask)
+SYSCALL_SPU(chroot)
+SYSCALL(ustat)
+SYSCALL_SPU(dup2)
+SYSCALL_SPU(getppid)
+SYSCALL_SPU(getpgrp)
+SYSCALL_SPU(setsid)
+SYS32ONLY(sigaction)
+SYSCALL_SPU(sgetmask)
+COMPAT_SYS_SPU(ssetmask)
+SYSCALL_SPU(setreuid)
+SYSCALL_SPU(setregid)
+SYS32ONLY(sigsuspend)
+COMPAT_SYS(sigpending)
+COMPAT_SYS_SPU(sethostname)
+COMPAT_SYS_SPU(setrlimit)
+COMPAT_SYS(old_getrlimit)
+COMPAT_SYS_SPU(getrusage)
+COMPAT_SYS_SPU(gettimeofday)
+COMPAT_SYS_SPU(settimeofday)
+COMPAT_SYS_SPU(getgroups)
+COMPAT_SYS_SPU(setgroups)
+SYSX(sys_ni_syscall,sys_ni_syscall,ppc_select)
+SYSCALL_SPU(symlink)
+OLDSYS(lstat)
+COMPAT_SYS_SPU(readlink)
+SYSCALL(uselib)
+SYSCALL(swapon)
+SYSCALL(reboot)
+SYSX(sys_ni_syscall,old32_readdir,old_readdir)
+SYSCALL_SPU(mmap)
+SYSCALL_SPU(munmap)
+SYSCALL_SPU(truncate)
+SYSCALL_SPU(ftruncate)
+SYSCALL_SPU(fchmod)
+SYSCALL_SPU(fchown)
+COMPAT_SYS_SPU(getpriority)
+COMPAT_SYS_SPU(setpriority)
+SYSCALL(ni_syscall)
+COMPAT_SYS(statfs)
+COMPAT_SYS(fstatfs)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(socketcall)
+COMPAT_SYS_SPU(syslog)
+COMPAT_SYS_SPU(setitimer)
+COMPAT_SYS_SPU(getitimer)
+COMPAT_SYS_SPU(newstat)
+COMPAT_SYS_SPU(newlstat)
+COMPAT_SYS_SPU(newfstat)
+SYSX(sys_ni_syscall,sys_uname,sys_uname)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(vhangup)
+SYSCALL(ni_syscall)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(wait4)
+SYSCALL(swapoff)
+COMPAT_SYS_SPU(sysinfo)
+COMPAT_SYS(ipc)
+SYSCALL_SPU(fsync)
+SYS32ONLY(sigreturn)
+PPC_SYS(clone)
+COMPAT_SYS_SPU(setdomainname)
+PPC_SYS_SPU(newuname)
+SYSCALL(ni_syscall)
+COMPAT_SYS_SPU(adjtimex)
+SYSCALL_SPU(mprotect)
+SYSX(sys_ni_syscall,compat_sys_sigprocmask,sys_sigprocmask)
+SYSCALL(ni_syscall)
+SYSCALL(init_module)
+SYSCALL(delete_module)
+SYSCALL(ni_syscall)
+SYSCALL(quotactl)
+COMPAT_SYS_SPU(getpgid)
+SYSCALL_SPU(fchdir)
+SYSCALL_SPU(bdflush)
+COMPAT_SYS(sysfs)
+SYSX_SPU(ppc64_personality,ppc64_personality,sys_personality)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(setfsuid)
+SYSCALL_SPU(setfsgid)
+SYSCALL_SPU(llseek)
+COMPAT_SYS_SPU(getdents)
+SYSX_SPU(sys_select,ppc32_select,ppc_select)
+SYSCALL_SPU(flock)
+SYSCALL_SPU(msync)
+COMPAT_SYS_SPU(readv)
+COMPAT_SYS_SPU(writev)
+COMPAT_SYS_SPU(getsid)
+SYSCALL_SPU(fdatasync)
+COMPAT_SYS(sysctl)
+SYSCALL_SPU(mlock)
+SYSCALL_SPU(munlock)
+SYSCALL_SPU(mlockall)
+SYSCALL_SPU(munlockall)
+COMPAT_SYS_SPU(sched_setparam)
+COMPAT_SYS_SPU(sched_getparam)
+COMPAT_SYS_SPU(sched_setscheduler)
+COMPAT_SYS_SPU(sched_getscheduler)
+SYSCALL_SPU(sched_yield)
+COMPAT_SYS_SPU(sched_get_priority_max)
+COMPAT_SYS_SPU(sched_get_priority_min)
+COMPAT_SYS_SPU(sched_rr_get_interval)
+COMPAT_SYS_SPU(nanosleep)
+SYSCALL_SPU(mremap)
+SYSCALL_SPU(setresuid)
+SYSCALL_SPU(getresuid)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(poll)
+COMPAT_SYS(nfsservctl)
+SYSCALL_SPU(setresgid)
+SYSCALL_SPU(getresgid)
+COMPAT_SYS_SPU(prctl)
+COMPAT_SYS(rt_sigreturn)
+COMPAT_SYS(rt_sigaction)
+COMPAT_SYS(rt_sigprocmask)
+COMPAT_SYS(rt_sigpending)
+COMPAT_SYS(rt_sigtimedwait)
+COMPAT_SYS(rt_sigqueueinfo)
+COMPAT_SYS(rt_sigsuspend)
+COMPAT_SYS_SPU(pread64)
+COMPAT_SYS_SPU(pwrite64)
+SYSCALL_SPU(chown)
+SYSCALL_SPU(getcwd)
+SYSCALL_SPU(capget)
+SYSCALL_SPU(capset)
+COMPAT_SYS(sigaltstack)
+SYSX_SPU(sys_sendfile64,compat_sys_sendfile,sys_sendfile)
+SYSCALL(ni_syscall)
+SYSCALL(ni_syscall)
+PPC_SYS(vfork)
+COMPAT_SYS_SPU(getrlimit)
+COMPAT_SYS_SPU(readahead)
+SYS32ONLY(mmap2)
+SYS32ONLY(truncate64)
+SYS32ONLY(ftruncate64)
+SYSX(sys_ni_syscall,sys_stat64,sys_stat64)
+SYSX(sys_ni_syscall,sys_lstat64,sys_lstat64)
+SYSX(sys_ni_syscall,sys_fstat64,sys_fstat64)
+SYSCALL(pciconfig_read)
+SYSCALL(pciconfig_write)
+SYSCALL(pciconfig_iobase)
+SYSCALL(ni_syscall)
+SYSCALL_SPU(getdents64)
+SYSCALL_SPU(pivot_root)
+SYSX(sys_ni_syscall,compat_sys_fcntl64,sys_fcntl64)
+SYSCALL_SPU(madvise)
+SYSCALL_SPU(mincore)
+SYSCALL_SPU(gettid)
+SYSCALL_SPU(tkill)
+SYSCALL_SPU(setxattr)
+SYSCALL_SPU(lsetxattr)
+SYSCALL_SPU(fsetxattr)
+SYSCALL_SPU(getxattr)
+SYSCALL_SPU(lgetxattr)
+SYSCALL_SPU(fgetxattr)
+SYSCALL_SPU(listxattr)
+SYSCALL_SPU(llistxattr)
+SYSCALL_SPU(flistxattr)
+SYSCALL_SPU(removexattr)
+SYSCALL_SPU(lremovexattr)
+SYSCALL_SPU(fremovexattr)
+COMPAT_SYS_SPU(futex)
+COMPAT_SYS_SPU(sched_setaffinity)
+COMPAT_SYS_SPU(sched_getaffinity)
+SYSCALL(ni_syscall)
+SYSCALL(ni_syscall)
+SYS32ONLY(sendfile64)
+COMPAT_SYS_SPU(io_setup)
+SYSCALL_SPU(io_destroy)
+COMPAT_SYS_SPU(io_getevents)
+COMPAT_SYS_SPU(io_submit)
+SYSCALL_SPU(io_cancel)
+SYSCALL(set_tid_address)
+SYSX_SPU(sys_fadvise64,ppc32_fadvise64,sys_fadvise64)
+SYSCALL(exit_group)
+SYSX(sys_lookup_dcookie,ppc32_lookup_dcookie,sys_lookup_dcookie)
+SYSCALL_SPU(epoll_create)
+SYSCALL_SPU(epoll_ctl)
+SYSCALL_SPU(epoll_wait)
+SYSCALL_SPU(remap_file_pages)
+SYSX_SPU(sys_timer_create,compat_sys_timer_create,sys_timer_create)
+COMPAT_SYS_SPU(timer_settime)
+COMPAT_SYS_SPU(timer_gettime)
+SYSCALL_SPU(timer_getoverrun)
+SYSCALL_SPU(timer_delete)
+COMPAT_SYS_SPU(clock_settime)
+COMPAT_SYS_SPU(clock_gettime)
+COMPAT_SYS_SPU(clock_getres)
+COMPAT_SYS_SPU(clock_nanosleep)
+SYSX(ppc64_swapcontext,ppc32_swapcontext,ppc_swapcontext)
+COMPAT_SYS_SPU(tgkill)
+COMPAT_SYS_SPU(utimes)
+COMPAT_SYS_SPU(statfs64)
+COMPAT_SYS_SPU(fstatfs64)
+SYSX(sys_ni_syscall, ppc_fadvise64_64, ppc_fadvise64_64)
+PPC_SYS_SPU(rtas)
+OLDSYS(debug_setcontext)
+SYSCALL(ni_syscall)
+SYSCALL(ni_syscall)
+COMPAT_SYS(mbind)
+COMPAT_SYS(get_mempolicy)
+COMPAT_SYS(set_mempolicy)
+COMPAT_SYS(mq_open)
+SYSCALL(mq_unlink)
+COMPAT_SYS(mq_timedsend)
+COMPAT_SYS(mq_timedreceive)
+COMPAT_SYS(mq_notify)
+COMPAT_SYS(mq_getsetattr)
+COMPAT_SYS(kexec_load)
+COMPAT_SYS(add_key)
+COMPAT_SYS(request_key)
+COMPAT_SYS(keyctl)
+COMPAT_SYS(waitid)
+COMPAT_SYS(ioprio_set)
+COMPAT_SYS(ioprio_get)
+SYSCALL(inotify_init)
+SYSCALL(inotify_add_watch)
+SYSCALL(inotify_rm_watch)
+SYSCALL(spu_run)
+SYSCALL(spu_create)
+COMPAT_SYS(pselect6)
+COMPAT_SYS(ppoll)
+SYSCALL_SPU(unshare)
+SYSCALL_SPU(splice)
+SYSCALL_SPU(tee)
+SYSCALL_SPU(vmsplice)
+COMPAT_SYS_SPU(openat)
+SYSCALL_SPU(mkdirat)
+SYSCALL_SPU(mknodat)
+SYSCALL_SPU(fchownat)
+COMPAT_SYS_SPU(futimesat)
+SYSX_SPU(sys_newfstatat, sys_fstatat64, sys_fstatat64)
+SYSCALL_SPU(unlinkat)
+SYSCALL_SPU(renameat)
+SYSCALL_SPU(linkat)
+SYSCALL_SPU(symlinkat)
+SYSCALL_SPU(readlinkat)
+SYSCALL_SPU(fchmodat)
+SYSCALL_SPU(faccessat)
+COMPAT_SYS_SPU(get_robust_list)
+COMPAT_SYS_SPU(set_robust_list)
diff --git a/include/asm-powerpc/tce.h b/include/asm-powerpc/tce.h
index 6fa200ad7a7f..c9483adbf599 100644
--- a/include/asm-powerpc/tce.h
+++ b/include/asm-powerpc/tce.h
@@ -35,32 +35,15 @@
 #define TCE_PAGE_SIZE   (1 << TCE_SHIFT)
 #define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
 
-
-/* tce_entry
- * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
- * abstracted so layout is irrelevant.
- */
-union tce_entry {
-        unsigned long te_word;
-        struct {
-                unsigned int  tb_cacheBits :6;  /* Cache hash bits - not used */
-                unsigned int  tb_rsvd      :6;
-                unsigned long tb_rpn       :40; /* Real page number */
-                unsigned int  tb_valid     :1;  /* Tce is valid (vb only) */
-                unsigned int  tb_allio     :1;  /* Tce is valid for all lps (vb only) */
-                unsigned int  tb_lpindex   :8;  /* LpIndex for user of TCE (vb only) */
-                unsigned int  tb_pciwr     :1;  /* Write allowed (pci only) */
-                unsigned int  tb_rdwr      :1;  /* Read allowed  (pci), Write allowed (vb) */
-        } te_bits;
-#define te_cacheBits te_bits.tb_cacheBits
-#define te_rpn       te_bits.tb_rpn
-#define te_valid     te_bits.tb_valid
-#define te_allio     te_bits.tb_allio
-#define te_lpindex   te_bits.tb_lpindex
-#define te_pciwr     te_bits.tb_pciwr
-#define te_rdwr      te_bits.tb_rdwr
-};
-
+#define TCE_ENTRY_SIZE          8               /* each TCE is 64 bits */
+
+#define TCE_RPN_MASK            0xfffffffffful  /* 40-bit RPN (4K pages) */
+#define TCE_RPN_SHIFT           12
+#define TCE_VALID               0x800           /* TCE valid */
+#define TCE_ALLIO               0x400           /* TCE valid for all lpars */
+#define TCE_PCI_WRITE           0x2             /* write from PCI allowed */
+#define TCE_PCI_READ            0x1             /* read from PCI allowed */
+#define TCE_VB_WRITE            0x1             /* write from VB allowed */
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_TCE_H */
diff --git a/include/asm-powerpc/termbits.h b/include/asm-powerpc/termbits.h
index ebf6055481dc..6d533b07aaf5 100644
--- a/include/asm-powerpc/termbits.h
+++ b/include/asm-powerpc/termbits.h
@@ -153,6 +153,7 @@ struct termios {
 #define HUPCL   00040000
 
 #define CLOCAL  00100000
+#define CMSPAR    010000000000          /* mark or space (stick) parity */
 #define CRTSCTS   020000000000          /* flow control */
 
 /* c_lflag bits */
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
index 4463148c659f..dcde4410348d 100644
--- a/include/asm-powerpc/time.h
+++ b/include/asm-powerpc/time.h
@@ -18,8 +18,9 @@
 #include <linux/percpu.h>
 
 #include <asm/processor.h>
-#ifdef CONFIG_PPC64
+#ifdef CONFIG_PPC_ISERIES
 #include <asm/paca.h>
+#include <asm/firmware.h>
 #include <asm/iseries/hv_call.h>
 #endif
 
@@ -177,7 +178,8 @@ static inline void set_dec(int val)
 #ifdef CONFIG_PPC_ISERIES
         int cur_dec;
 
-        if (get_lppaca()->shared_proc) {
+        if (firmware_has_feature(FW_FEATURE_ISERIES) &&
+                        get_lppaca()->shared_proc) {
                 get_lppaca()->virtual_decr = val;
                 cur_dec = get_dec();
                 if (cur_dec > val)
diff --git a/include/asm-powerpc/todc.h b/include/asm-powerpc/todc.h
new file mode 100644
index 000000000000..60a8c39b8c11
--- /dev/null
+++ b/include/asm-powerpc/todc.h
@@ -0,0 +1,487 @@
+/*
+ * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
+ * Clock chips.
+ *
+ * Author: Mark A. Greer <mgreer@mvista.com>
+ *
+ * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+
+/*
+ * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
+ * Purpose is to make one generic file that handles all of these chips instead
+ * of every platform implementing the same code over & over again.
+ */
+
+#ifndef __PPC_KERNEL_TODC_H
+#define __PPC_KERNEL_TODC_H
+
+typedef struct {
+        uint rtc_type;          /* your particular chip */
+
+        /*
+         * Following are the addresses of the AS0, AS1, and DATA registers
+         * of these chips.  Note that these are board-specific.
+         */
+        unsigned int nvram_as0;
+        unsigned int nvram_as1;
+        unsigned int nvram_data;
+
+        /*
+         * Define bits to stop external set of regs from changing so
+         * the chip can be read/written reliably.
+         */
+        unsigned char enable_read;
+        unsigned char enable_write;
+
+        /*
+         * Following is the number of AS0 address bits.  This is normally
+         * 8 but some bad hardware routes address lines incorrectly.
+         */
+        int as0_bits;
+
+        int nvram_size; /* Size of NVRAM on chip */
+        int sw_flags;   /* Software control flags */
+
+        /* Following are the register offsets for the particular chip */
+        int year;
+        int month;
+        int day_of_month;
+        int day_of_week;
+        int hours;
+        int minutes;
+        int seconds;
+        int control_b;
+        int control_a;
+        int watchdog;
+        int interrupts;
+        int alarm_date;
+        int alarm_hour;
+        int alarm_minutes;
+        int alarm_seconds;
+        int century;
+        int flags;
+
+        /*
+         * Some RTC chips have their NVRAM buried behind a addr/data pair of
+         * regs on the first level/clock registers.  The following fields
+         * are the addresses for those addr/data regs.
+         */
+        int nvram_addr_reg;
+        int nvram_data_reg;
+} todc_info_t;
+
+/*
+ * Define the types of TODC/RTC variants that are supported in
+ * arch/ppc/kernel/todc_time.c
+ * Make a new one of these for any chip somehow differs from what's already
+ * defined.  That way, if you ever need to put in code to touch those
+ * bits/registers in todc_time.c, you can put it inside an
+ * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break
+ * anyone else.
+ */
+#define TODC_TYPE_MK48T35               1
+#define TODC_TYPE_MK48T37               2
+#define TODC_TYPE_MK48T59               3
+#define TODC_TYPE_DS1693                4       /* Dallas DS1693 RTC */
+#define TODC_TYPE_DS1743                5       /* Dallas DS1743 RTC */
+#define TODC_TYPE_DS1746                6       /* Dallas DS1746 RTC */
+#define TODC_TYPE_DS1747                7       /* Dallas DS1747 RTC */
+#define TODC_TYPE_DS1501                8       /* Dallas DS1501 RTC */
+#define TODC_TYPE_DS1643                9       /* Dallas DS1643 RTC */
+#define TODC_TYPE_PC97307               10      /* PC97307 internal RTC */
+#define TODC_TYPE_DS1557                11      /* Dallas DS1557 RTC */
+#define TODC_TYPE_DS17285               12      /* Dallas DS17285 RTC */
+#define TODC_TYPE_DS1553                13      /* Dallas DS1553 RTC */
+#define TODC_TYPE_MC146818              100     /* Leave room for m48txx's */
+
+/*
+ * Bit to clear/set to enable reads/writes to the chip
+ */
+#define TODC_MK48TXX_CNTL_A_R           0x40
+#define TODC_MK48TXX_CNTL_A_W           0x80
+#define TODC_MK48TXX_DAY_CB             0x80
+
+#define TODC_DS1501_CNTL_B_TE           0x80
+
+/*
+ * Define flag bits used by todc routines.
+ */
+#define TODC_FLAG_2_LEVEL_NVRAM         0x00000001
+
+/*
+ * Define the values for the various RTC's that should to into the todc_info
+ * table.
+ * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
+ * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
+ */
+#define TODC_TYPE_MK48T35_NVRAM_SIZE            0x7ff8
+#define TODC_TYPE_MK48T35_SW_FLAGS              0
+#define TODC_TYPE_MK48T35_YEAR                  0x7fff
+#define TODC_TYPE_MK48T35_MONTH                 0x7ffe
+#define TODC_TYPE_MK48T35_DOM                   0x7ffd  /* Day of Month */
+#define TODC_TYPE_MK48T35_DOW                   0x7ffc  /* Day of Week */
+#define TODC_TYPE_MK48T35_HOURS                 0x7ffb
+#define TODC_TYPE_MK48T35_MINUTES               0x7ffa
+#define TODC_TYPE_MK48T35_SECONDS               0x7ff9
+#define TODC_TYPE_MK48T35_CNTL_B                0x7ff9
+#define TODC_TYPE_MK48T35_CNTL_A                0x7ff8
+#define TODC_TYPE_MK48T35_WATCHDOG              0x0000
+#define TODC_TYPE_MK48T35_INTERRUPTS            0x0000
+#define TODC_TYPE_MK48T35_ALARM_DATE            0x0000
+#define TODC_TYPE_MK48T35_ALARM_HOUR            0x0000
+#define TODC_TYPE_MK48T35_ALARM_MINUTES         0x0000
+#define TODC_TYPE_MK48T35_ALARM_SECONDS         0x0000
+#define TODC_TYPE_MK48T35_CENTURY               0x0000
+#define TODC_TYPE_MK48T35_FLAGS                 0x0000
+#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG        0
+#define TODC_TYPE_MK48T35_NVRAM_DATA_REG        0
+
+#define TODC_TYPE_MK48T37_NVRAM_SIZE            0x7ff0
+#define TODC_TYPE_MK48T37_SW_FLAGS              0
+#define TODC_TYPE_MK48T37_YEAR                  0x7fff
+#define TODC_TYPE_MK48T37_MONTH                 0x7ffe
+#define TODC_TYPE_MK48T37_DOM                   0x7ffd  /* Day of Month */
+#define TODC_TYPE_MK48T37_DOW                   0x7ffc  /* Day of Week */
+#define TODC_TYPE_MK48T37_HOURS                 0x7ffb
+#define TODC_TYPE_MK48T37_MINUTES               0x7ffa
+#define TODC_TYPE_MK48T37_SECONDS               0x7ff9
+#define TODC_TYPE_MK48T37_CNTL_B                0x7ff9
+#define TODC_TYPE_MK48T37_CNTL_A                0x7ff8
+#define TODC_TYPE_MK48T37_WATCHDOG              0x7ff7
+#define TODC_TYPE_MK48T37_INTERRUPTS            0x7ff6
+#define TODC_TYPE_MK48T37_ALARM_DATE            0x7ff5
+#define TODC_TYPE_MK48T37_ALARM_HOUR            0x7ff4
+#define TODC_TYPE_MK48T37_ALARM_MINUTES         0x7ff3
+#define TODC_TYPE_MK48T37_ALARM_SECONDS         0x7ff2
+#define TODC_TYPE_MK48T37_CENTURY               0x7ff1
+#define TODC_TYPE_MK48T37_FLAGS                 0x7ff0
+#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG        0
+#define TODC_TYPE_MK48T37_NVRAM_DATA_REG        0
+
+#define TODC_TYPE_MK48T59_NVRAM_SIZE            0x1ff0
+#define TODC_TYPE_MK48T59_SW_FLAGS              0
+#define TODC_TYPE_MK48T59_YEAR                  0x1fff
+#define TODC_TYPE_MK48T59_MONTH                 0x1ffe
+#define TODC_TYPE_MK48T59_DOM                   0x1ffd  /* Day of Month */
+#define TODC_TYPE_MK48T59_DOW                   0x1ffc  /* Day of Week */
+#define TODC_TYPE_MK48T59_HOURS                 0x1ffb
+#define TODC_TYPE_MK48T59_MINUTES               0x1ffa
+#define TODC_TYPE_MK48T59_SECONDS               0x1ff9
+#define TODC_TYPE_MK48T59_CNTL_B                0x1ff9
+#define TODC_TYPE_MK48T59_CNTL_A                0x1ff8
+#define TODC_TYPE_MK48T59_WATCHDOG              0x1fff
+#define TODC_TYPE_MK48T59_INTERRUPTS            0x1fff
+#define TODC_TYPE_MK48T59_ALARM_DATE            0x1fff
+#define TODC_TYPE_MK48T59_ALARM_HOUR            0x1fff
+#define TODC_TYPE_MK48T59_ALARM_MINUTES         0x1fff
+#define TODC_TYPE_MK48T59_ALARM_SECONDS         0x1fff
+#define TODC_TYPE_MK48T59_CENTURY               0x1fff
+#define TODC_TYPE_MK48T59_FLAGS                 0x1fff
+#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG        0
+#define TODC_TYPE_MK48T59_NVRAM_DATA_REG        0
+
+#define TODC_TYPE_DS1501_NVRAM_SIZE     0x100
+#define TODC_TYPE_DS1501_SW_FLAGS       TODC_FLAG_2_LEVEL_NVRAM
+#define TODC_TYPE_DS1501_YEAR           (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
+#define TODC_TYPE_DS1501_MONTH          (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
+#define TODC_TYPE_DS1501_DOM            (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
+#define TODC_TYPE_DS1501_DOW            (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
+#define TODC_TYPE_DS1501_HOURS          (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
+#define TODC_TYPE_DS1501_MINUTES        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
+#define TODC_TYPE_DS1501_SECONDS        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
+#define TODC_TYPE_DS1501_CNTL_B         (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
+#define TODC_TYPE_DS1501_CNTL_A         (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
+#define TODC_TYPE_DS1501_WATCHDOG       (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define TODC_TYPE_DS1501_INTERRUPTS     (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define TODC_TYPE_DS1501_ALARM_DATE     (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
+#define TODC_TYPE_DS1501_ALARM_HOUR     (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
+#define TODC_TYPE_DS1501_ALARM_MINUTES  (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
+#define TODC_TYPE_DS1501_ALARM_SECONDS  (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
+#define TODC_TYPE_DS1501_CENTURY        (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
+#define TODC_TYPE_DS1501_FLAGS          (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
+#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
+#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
+
+#define TODC_TYPE_DS1553_NVRAM_SIZE             0x1ff0
+#define TODC_TYPE_DS1553_SW_FLAGS               0
+#define TODC_TYPE_DS1553_YEAR                   0x1fff
+#define TODC_TYPE_DS1553_MONTH                  0x1ffe
+#define TODC_TYPE_DS1553_DOM                    0x1ffd  /* Day of Month */
+#define TODC_TYPE_DS1553_DOW                    0x1ffc  /* Day of Week */
+#define TODC_TYPE_DS1553_HOURS                  0x1ffb
+#define TODC_TYPE_DS1553_MINUTES                0x1ffa
+#define TODC_TYPE_DS1553_SECONDS                0x1ff9
+#define TODC_TYPE_DS1553_CNTL_B                 0x1ff9
+#define TODC_TYPE_DS1553_CNTL_A                 0x1ff8  /* control_a R/W regs */
+#define TODC_TYPE_DS1553_WATCHDOG               0x1ff7
+#define TODC_TYPE_DS1553_INTERRUPTS             0x1ff6
+#define TODC_TYPE_DS1553_ALARM_DATE             0x1ff5
+#define TODC_TYPE_DS1553_ALARM_HOUR             0x1ff4
+#define TODC_TYPE_DS1553_ALARM_MINUTES          0x1ff3
+#define TODC_TYPE_DS1553_ALARM_SECONDS          0x1ff2
+#define TODC_TYPE_DS1553_CENTURY                0x1ff8
+#define TODC_TYPE_DS1553_FLAGS                  0x1ff0
+#define TODC_TYPE_DS1553_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1553_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1557_NVRAM_SIZE             0x7fff0
+#define TODC_TYPE_DS1557_SW_FLAGS               0
+#define TODC_TYPE_DS1557_YEAR                   0x7ffff
+#define TODC_TYPE_DS1557_MONTH                  0x7fffe
+#define TODC_TYPE_DS1557_DOM                    0x7fffd /* Day of Month */
+#define TODC_TYPE_DS1557_DOW                    0x7fffc /* Day of Week */
+#define TODC_TYPE_DS1557_HOURS                  0x7fffb
+#define TODC_TYPE_DS1557_MINUTES                0x7fffa
+#define TODC_TYPE_DS1557_SECONDS                0x7fff9
+#define TODC_TYPE_DS1557_CNTL_B                 0x7fff9
+#define TODC_TYPE_DS1557_CNTL_A                 0x7fff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1557_WATCHDOG               0x7fff7
+#define TODC_TYPE_DS1557_INTERRUPTS             0x7fff6
+#define TODC_TYPE_DS1557_ALARM_DATE             0x7fff5
+#define TODC_TYPE_DS1557_ALARM_HOUR             0x7fff4
+#define TODC_TYPE_DS1557_ALARM_MINUTES          0x7fff3
+#define TODC_TYPE_DS1557_ALARM_SECONDS          0x7fff2
+#define TODC_TYPE_DS1557_CENTURY                0x7fff8
+#define TODC_TYPE_DS1557_FLAGS                  0x7fff0
+#define TODC_TYPE_DS1557_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1557_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1643_NVRAM_SIZE             0x1ff8
+#define TODC_TYPE_DS1643_SW_FLAGS               0
+#define TODC_TYPE_DS1643_YEAR                   0x1fff
+#define TODC_TYPE_DS1643_MONTH                  0x1ffe
+#define TODC_TYPE_DS1643_DOM                    0x1ffd  /* Day of Month */
+#define TODC_TYPE_DS1643_DOW                    0x1ffc  /* Day of Week */
+#define TODC_TYPE_DS1643_HOURS                  0x1ffb
+#define TODC_TYPE_DS1643_MINUTES                0x1ffa
+#define TODC_TYPE_DS1643_SECONDS                0x1ff9
+#define TODC_TYPE_DS1643_CNTL_B                 0x1ff9
+#define TODC_TYPE_DS1643_CNTL_A                 0x1ff8  /* control_a R/W regs */
+#define TODC_TYPE_DS1643_WATCHDOG               0x1fff
+#define TODC_TYPE_DS1643_INTERRUPTS             0x1fff
+#define TODC_TYPE_DS1643_ALARM_DATE             0x1fff
+#define TODC_TYPE_DS1643_ALARM_HOUR             0x1fff
+#define TODC_TYPE_DS1643_ALARM_MINUTES          0x1fff
+#define TODC_TYPE_DS1643_ALARM_SECONDS          0x1fff
+#define TODC_TYPE_DS1643_CENTURY                0x1ff8
+#define TODC_TYPE_DS1643_FLAGS                  0x1fff
+#define TODC_TYPE_DS1643_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1643_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1693_NVRAM_SIZE             0 /* Not handled yet */
+#define TODC_TYPE_DS1693_SW_FLAGS               0
+#define TODC_TYPE_DS1693_YEAR                   0x09
+#define TODC_TYPE_DS1693_MONTH                  0x08
+#define TODC_TYPE_DS1693_DOM                    0x07    /* Day of Month */
+#define TODC_TYPE_DS1693_DOW                    0x06    /* Day of Week */
+#define TODC_TYPE_DS1693_HOURS                  0x04
+#define TODC_TYPE_DS1693_MINUTES                0x02
+#define TODC_TYPE_DS1693_SECONDS                0x00
+#define TODC_TYPE_DS1693_CNTL_B                 0x0b
+#define TODC_TYPE_DS1693_CNTL_A                 0x0a
+#define TODC_TYPE_DS1693_WATCHDOG               0xff
+#define TODC_TYPE_DS1693_INTERRUPTS             0xff
+#define TODC_TYPE_DS1693_ALARM_DATE             0x49
+#define TODC_TYPE_DS1693_ALARM_HOUR             0x05
+#define TODC_TYPE_DS1693_ALARM_MINUTES          0x03
+#define TODC_TYPE_DS1693_ALARM_SECONDS          0x01
+#define TODC_TYPE_DS1693_CENTURY                0x48
+#define TODC_TYPE_DS1693_FLAGS                  0xff
+#define TODC_TYPE_DS1693_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1693_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1743_NVRAM_SIZE             0x1ff8
+#define TODC_TYPE_DS1743_SW_FLAGS               0
+#define TODC_TYPE_DS1743_YEAR                   0x1fff
+#define TODC_TYPE_DS1743_MONTH                  0x1ffe
+#define TODC_TYPE_DS1743_DOM                    0x1ffd  /* Day of Month */
+#define TODC_TYPE_DS1743_DOW                    0x1ffc  /* Day of Week */
+#define TODC_TYPE_DS1743_HOURS                  0x1ffb
+#define TODC_TYPE_DS1743_MINUTES                0x1ffa
+#define TODC_TYPE_DS1743_SECONDS                0x1ff9
+#define TODC_TYPE_DS1743_CNTL_B                 0x1ff9
+#define TODC_TYPE_DS1743_CNTL_A                 0x1ff8  /* control_a R/W regs */
+#define TODC_TYPE_DS1743_WATCHDOG               0x1fff
+#define TODC_TYPE_DS1743_INTERRUPTS             0x1fff
+#define TODC_TYPE_DS1743_ALARM_DATE             0x1fff
+#define TODC_TYPE_DS1743_ALARM_HOUR             0x1fff
+#define TODC_TYPE_DS1743_ALARM_MINUTES          0x1fff
+#define TODC_TYPE_DS1743_ALARM_SECONDS          0x1fff
+#define TODC_TYPE_DS1743_CENTURY                0x1ff8
+#define TODC_TYPE_DS1743_FLAGS                  0x1fff
+#define TODC_TYPE_DS1743_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1743_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1746_NVRAM_SIZE             0x1fff8
+#define TODC_TYPE_DS1746_SW_FLAGS               0
+#define TODC_TYPE_DS1746_YEAR                   0x1ffff
+#define TODC_TYPE_DS1746_MONTH                  0x1fffe
+#define TODC_TYPE_DS1746_DOM                    0x1fffd /* Day of Month */
+#define TODC_TYPE_DS1746_DOW                    0x1fffc /* Day of Week */
+#define TODC_TYPE_DS1746_HOURS                  0x1fffb
+#define TODC_TYPE_DS1746_MINUTES                0x1fffa
+#define TODC_TYPE_DS1746_SECONDS                0x1fff9
+#define TODC_TYPE_DS1746_CNTL_B                 0x1fff9
+#define TODC_TYPE_DS1746_CNTL_A                 0x1fff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1746_WATCHDOG               0x00000
+#define TODC_TYPE_DS1746_INTERRUPTS             0x00000
+#define TODC_TYPE_DS1746_ALARM_DATE             0x00000
+#define TODC_TYPE_DS1746_ALARM_HOUR             0x00000
+#define TODC_TYPE_DS1746_ALARM_MINUTES          0x00000
+#define TODC_TYPE_DS1746_ALARM_SECONDS          0x00000
+#define TODC_TYPE_DS1746_CENTURY                0x00000
+#define TODC_TYPE_DS1746_FLAGS                  0x00000
+#define TODC_TYPE_DS1746_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1746_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS1747_NVRAM_SIZE             0x7fff8
+#define TODC_TYPE_DS1747_SW_FLAGS               0
+#define TODC_TYPE_DS1747_YEAR                   0x7ffff
+#define TODC_TYPE_DS1747_MONTH                  0x7fffe
+#define TODC_TYPE_DS1747_DOM                    0x7fffd /* Day of Month */
+#define TODC_TYPE_DS1747_DOW                    0x7fffc /* Day of Week */
+#define TODC_TYPE_DS1747_HOURS                  0x7fffb
+#define TODC_TYPE_DS1747_MINUTES                0x7fffa
+#define TODC_TYPE_DS1747_SECONDS                0x7fff9
+#define TODC_TYPE_DS1747_CNTL_B                 0x7fff9
+#define TODC_TYPE_DS1747_CNTL_A                 0x7fff8 /* control_a R/W regs */
+#define TODC_TYPE_DS1747_WATCHDOG               0x00000
+#define TODC_TYPE_DS1747_INTERRUPTS             0x00000
+#define TODC_TYPE_DS1747_ALARM_DATE             0x00000
+#define TODC_TYPE_DS1747_ALARM_HOUR             0x00000
+#define TODC_TYPE_DS1747_ALARM_MINUTES          0x00000
+#define TODC_TYPE_DS1747_ALARM_SECONDS          0x00000
+#define TODC_TYPE_DS1747_CENTURY                0x00000
+#define TODC_TYPE_DS1747_FLAGS                  0x00000
+#define TODC_TYPE_DS1747_NVRAM_ADDR_REG         0
+#define TODC_TYPE_DS1747_NVRAM_DATA_REG         0
+
+#define TODC_TYPE_DS17285_NVRAM_SIZE            (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */
+#define TODC_TYPE_DS17285_SW_FLAGS              TODC_FLAG_2_LEVEL_NVRAM
+#define TODC_TYPE_DS17285_SECONDS               (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
+#define TODC_TYPE_DS17285_ALARM_SECONDS         (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
+#define TODC_TYPE_DS17285_MINUTES               (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
+#define TODC_TYPE_DS17285_ALARM_MINUTES         (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
+#define TODC_TYPE_DS17285_HOURS                 (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
+#define TODC_TYPE_DS17285_ALARM_HOUR            (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
+#define TODC_TYPE_DS17285_DOW                   (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
+#define TODC_TYPE_DS17285_DOM                   (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
+#define TODC_TYPE_DS17285_MONTH                 (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
+#define TODC_TYPE_DS17285_YEAR                  (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
+#define TODC_TYPE_DS17285_CNTL_A                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
+#define TODC_TYPE_DS17285_CNTL_B                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
+#define TODC_TYPE_DS17285_CNTL_C                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
+#define TODC_TYPE_DS17285_CNTL_D                (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
+#define TODC_TYPE_DS17285_WATCHDOG              0
+#define TODC_TYPE_DS17285_INTERRUPTS            0
+#define TODC_TYPE_DS17285_ALARM_DATE            0
+#define TODC_TYPE_DS17285_CENTURY               0
+#define TODC_TYPE_DS17285_FLAGS                 0
+#define TODC_TYPE_DS17285_NVRAM_ADDR_REG        0x50
+#define TODC_TYPE_DS17285_NVRAM_DATA_REG        0x53
+
+#define TODC_TYPE_MC146818_NVRAM_SIZE           0       /* XXXX */
+#define TODC_TYPE_MC146818_SW_FLAGS             0
+#define TODC_TYPE_MC146818_YEAR                 0x09
+#define TODC_TYPE_MC146818_MONTH                0x08
+#define TODC_TYPE_MC146818_DOM                  0x07    /* Day of Month */
+#define TODC_TYPE_MC146818_DOW                  0x06    /* Day of Week */
+#define TODC_TYPE_MC146818_HOURS                0x04
+#define TODC_TYPE_MC146818_MINUTES              0x02
+#define TODC_TYPE_MC146818_SECONDS              0x00
+#define TODC_TYPE_MC146818_CNTL_B               0x0a
+#define TODC_TYPE_MC146818_CNTL_A               0x0b    /* control_a R/W regs */
+#define TODC_TYPE_MC146818_WATCHDOG             0
+#define TODC_TYPE_MC146818_INTERRUPTS           0x0c
+#define TODC_TYPE_MC146818_ALARM_DATE           0xff
+#define TODC_TYPE_MC146818_ALARM_HOUR           0x05
+#define TODC_TYPE_MC146818_ALARM_MINUTES        0x03
+#define TODC_TYPE_MC146818_ALARM_SECONDS        0x01
+#define TODC_TYPE_MC146818_CENTURY              0xff
+#define TODC_TYPE_MC146818_FLAGS                0xff
+#define TODC_TYPE_MC146818_NVRAM_ADDR_REG       0
+#define TODC_TYPE_MC146818_NVRAM_DATA_REG       0
+
+#define TODC_TYPE_PC97307_NVRAM_SIZE            0       /* No NVRAM? */
+#define TODC_TYPE_PC97307_SW_FLAGS              0
+#define TODC_TYPE_PC97307_YEAR                  0x09
+#define TODC_TYPE_PC97307_MONTH                 0x08
+#define TODC_TYPE_PC97307_DOM                   0x07    /* Day of Month */
+#define TODC_TYPE_PC97307_DOW                   0x06    /* Day of Week */
+#define TODC_TYPE_PC97307_HOURS                 0x04
+#define TODC_TYPE_PC97307_MINUTES               0x02
+#define TODC_TYPE_PC97307_SECONDS               0x00
+#define TODC_TYPE_PC97307_CNTL_B                0x0a
+#define TODC_TYPE_PC97307_CNTL_A                0x0b    /* control_a R/W regs */
+#define TODC_TYPE_PC97307_WATCHDOG              0x0c
+#define TODC_TYPE_PC97307_INTERRUPTS            0x0d
+#define TODC_TYPE_PC97307_ALARM_DATE            0xff
+#define TODC_TYPE_PC97307_ALARM_HOUR            0x05
+#define TODC_TYPE_PC97307_ALARM_MINUTES         0x03
+#define TODC_TYPE_PC97307_ALARM_SECONDS         0x01
+#define TODC_TYPE_PC97307_CENTURY               0xff
+#define TODC_TYPE_PC97307_FLAGS                 0xff
+#define TODC_TYPE_PC97307_NVRAM_ADDR_REG        0
+#define TODC_TYPE_PC97307_NVRAM_DATA_REG        0
+
+/*
+ * Define macros to allocate and init the todc_info_t table that will
+ * be used by the todc_time.c routines.
+ */
+#define TODC_ALLOC()                                                    \
+        static todc_info_t todc_info_alloc;                             \
+        todc_info_t *todc_info = &todc_info_alloc;
+
+#define TODC_INIT(clock_type, as0, as1, data, bits) {                   \
+        todc_info->rtc_type = clock_type;                               \
+                                                                        \
+        todc_info->nvram_as0 = (unsigned int)(as0);                     \
+        todc_info->nvram_as1 = (unsigned int)(as1);                     \
+        todc_info->nvram_data = (unsigned int)(data);                   \
+                                                                        \
+        todc_info->as0_bits = (bits);                                   \
+                                                                        \
+        todc_info->nvram_size = clock_type ##_NVRAM_SIZE;               \
+        todc_info->sw_flags = clock_type ##_SW_FLAGS;                   \
+                                                                        \
+        todc_info->year = clock_type ##_YEAR;                           \
+        todc_info->month = clock_type ##_MONTH;                         \
+        todc_info->day_of_month = clock_type ##_DOM;                    \
+        todc_info->day_of_week = clock_type ##_DOW;                     \
+        todc_info->hours = clock_type ##_HOURS;                         \
+        todc_info->minutes = clock_type ##_MINUTES;                     \
+        todc_info->seconds = clock_type ##_SECONDS;                     \
+        todc_info->control_b = clock_type ##_CNTL_B;                    \
+        todc_info->control_a = clock_type ##_CNTL_A;                    \
+        todc_info->watchdog = clock_type ##_WATCHDOG;                   \
+        todc_info->interrupts = clock_type ##_INTERRUPTS;               \
+        todc_info->alarm_date = clock_type ##_ALARM_DATE;               \
+        todc_info->alarm_hour = clock_type ##_ALARM_HOUR;               \
+        todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES;         \
+        todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS;         \
+        todc_info->century = clock_type ##_CENTURY;                     \
+        todc_info->flags = clock_type ##_FLAGS;                         \
+                                                                        \
+        todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG;       \
+        todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG;       \
+}
+
+extern todc_info_t *todc_info;
+
+unsigned char todc_direct_read_val(int addr);
+void todc_direct_write_val(int addr, unsigned char val);
+unsigned char todc_m48txx_read_val(int addr);
+void todc_m48txx_write_val(int addr, unsigned char val);
+unsigned char todc_mc146818_read_val(int addr);
+void todc_mc146818_write_val(int addr, unsigned char val);
+
+long todc_time_init(void);
+void todc_get_rtc_time(struct rtc_time *);
+int todc_set_rtc_time(struct rtc_time *);
+void todc_calibrate_decr(void);
+
+#endif                          /* __PPC_KERNEL_TODC_H */
diff --git a/include/asm-powerpc/topology.h b/include/asm-powerpc/topology.h
index 19c575f39164..bbc3844b086f 100644
--- a/include/asm-powerpc/topology.h
+++ b/include/asm-powerpc/topology.h
@@ -31,8 +31,13 @@ static inline int node_to_first_cpu(int node)
 
 int of_node_to_nid(struct device_node *device);
 
-#define pcibus_to_node(node)    (-1)
-#define pcibus_to_cpumask(bus)  (cpu_online_map)
+struct pci_bus;
+extern int pcibus_to_node(struct pci_bus *bus);
+
+#define pcibus_to_cpumask(bus)  (pcibus_to_node(bus) == -1 ? \
+                                        CPU_MASK_ALL : \
+                                        node_to_cpumask(pcibus_to_node(bus)) \
+                                )
 
 /* sched_domains SD_NODE_INIT for PPC64 machines */
 #define SD_NODE_INIT (struct sched_domain) {            \
@@ -88,5 +93,10 @@ static inline void sysfs_remove_device_from_node(struct sys_device *dev,
 
 #endif /* CONFIG_NUMA */
 
+#ifdef CONFIG_SMP
+#include <asm/cputable.h>
+#define smt_capable()           (cpu_has_feature(CPU_FTR_SMT))
+#endif
+
 #endif /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_TOPOLOGY_H */
diff --git a/include/asm-powerpc/tsi108.h b/include/asm-powerpc/tsi108.h
new file mode 100644
index 000000000000..c4c278d72f71
--- /dev/null
+++ b/include/asm-powerpc/tsi108.h
@@ -0,0 +1,109 @@
+/*
+ * include/asm-ppc/tsi108.h
+ *
+ * common routine and memory layout for Tundra TSI108(Grendel) host bridge
+ * memory controller.
+ *
+ * Author: Jacob Pan (jacob.pan@freescale.com)
+ *         Alex Bounine (alexandreb@tundra.com)
+ * 2004 (c) Freescale Semiconductor Inc.  This file is licensed under
+ * the terms of the GNU General Public License version 2.  This program
+ * is licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __PPC_KERNEL_TSI108_H
+#define __PPC_KERNEL_TSI108_H
+
+#include <asm/pci-bridge.h>
+
+/* Size of entire register space */
+#define TSI108_REG_SIZE         (0x10000)
+
+/* Sizes of register spaces for individual blocks */
+#define TSI108_HLP_SIZE         0x1000
+#define TSI108_PCI_SIZE         0x1000
+#define TSI108_CLK_SIZE         0x1000
+#define TSI108_PB_SIZE          0x1000
+#define TSI108_SD_SIZE          0x1000
+#define TSI108_DMA_SIZE         0x1000
+#define TSI108_ETH_SIZE         0x1000
+#define TSI108_I2C_SIZE         0x400
+#define TSI108_MPIC_SIZE        0x400
+#define TSI108_UART0_SIZE       0x200
+#define TSI108_GPIO_SIZE        0x200
+#define TSI108_UART1_SIZE       0x200
+
+/* Offsets within Tsi108(A) CSR space for individual blocks */
+#define TSI108_HLP_OFFSET       0x0000
+#define TSI108_PCI_OFFSET       0x1000
+#define TSI108_CLK_OFFSET       0x2000
+#define TSI108_PB_OFFSET        0x3000
+#define TSI108_SD_OFFSET        0x4000
+#define TSI108_DMA_OFFSET       0x5000
+#define TSI108_ETH_OFFSET       0x6000
+#define TSI108_I2C_OFFSET       0x7000
+#define TSI108_MPIC_OFFSET      0x7400
+#define TSI108_UART0_OFFSET     0x7800
+#define TSI108_GPIO_OFFSET      0x7A00
+#define TSI108_UART1_OFFSET     0x7C00
+
+/* Tsi108 registers used by common code components */
+#define TSI108_PCI_CSR          (0x004)
+#define TSI108_PCI_IRP_CFG_CTL  (0x180)
+#define TSI108_PCI_IRP_STAT     (0x184)
+#define TSI108_PCI_IRP_ENABLE   (0x188)
+#define TSI108_PCI_IRP_INTAD    (0x18C)
+
+#define TSI108_PCI_IRP_STAT_P_INT       (0x00400000)
+#define TSI108_PCI_IRP_ENABLE_P_INT     (0x00400000)
+
+#define TSI108_CG_PWRUP_STATUS  (0x234)
+
+#define TSI108_PB_ISR           (0x00C)
+#define TSI108_PB_ERRCS         (0x404)
+#define TSI108_PB_AERR          (0x408)
+
+#define TSI108_PB_ERRCS_ES              (1 << 1)
+#define TSI108_PB_ISR_PBS_RD_ERR        (1 << 8)
+
+#define TSI108_PCI_CFG_BASE_PHYS        (0xfb000000)
+#define TSI108_PCI_CFG_SIZE             (0x01000000)
+/* Global variables */
+
+extern u32 tsi108_pci_cfg_base;
+/* Exported functions */
+
+extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base);
+extern unsigned long tsi108_get_mem_size(void);
+extern unsigned long tsi108_get_cpu_clk(void);
+extern unsigned long tsi108_get_sdc_clk(void);
+extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
+                                      int offset, int len, u32 val);
+extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
+                                     int offset, int len, u32 * val);
+extern void tsi108_clear_pci_error(u32 pci_cfg_base);
+
+extern phys_addr_t get_csrbase(void);
+
+typedef struct {
+        u32 regs;               /* hw registers base address */
+        u32 phyregs;            /* phy registers base address */
+        u16 phy;                /* phy address */
+        u16 irq_num;            /* irq number */
+        u8 mac_addr[6];         /* phy mac address */
+} hw_info;
+
+extern u32 get_vir_csrbase(void);
+extern u32 tsi108_csr_vir_base;
+
+extern inline u32 tsi108_read_reg(u32 reg_offset)
+{
+        return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
+}
+
+extern inline void tsi108_write_reg(u32 reg_offset, u32 val)
+{
+        out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
+}
+
+#endif                          /* __PPC_KERNEL_TSI108_H */
diff --git a/include/asm-powerpc/udbg.h b/include/asm-powerpc/udbg.h
index 5c4236c342bb..55e57844fa78 100644
--- a/include/asm-powerpc/udbg.h
+++ b/include/asm-powerpc/udbg.h
@@ -23,7 +23,8 @@ extern int udbg_write(const char *s, int n);
 extern int udbg_read(char *buf, int buflen);
 
 extern void register_early_udbg_console(void);
-extern void udbg_printf(const char *fmt, ...);
+extern void udbg_printf(const char *fmt, ...)
+        __attribute__ ((format (printf, 1, 2)));
 extern void udbg_progress(char *s, unsigned short hex);
 
 extern void udbg_init_uart(void __iomem *comport, unsigned int speed,
@@ -41,7 +42,8 @@ extern void __init udbg_init_debug_lpar(void);
 extern void __init udbg_init_pmac_realmode(void);
 extern void __init udbg_init_maple_realmode(void);
 extern void __init udbg_init_iseries(void);
-extern void __init udbg_init_rtas(void);
+extern void __init udbg_init_rtas_panel(void);
+extern void __init udbg_init_rtas_console(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_UDBG_H */
diff --git a/include/asm-powerpc/vga.h b/include/asm-powerpc/vga.h
index eadaf2f3d032..a2eac409c1ec 100644
--- a/include/asm-powerpc/vga.h
+++ b/include/asm-powerpc/vga.h
@@ -41,9 +41,9 @@ static inline u16 scr_readw(volatile const u16 *addr)
 extern unsigned long vgacon_remap_base;
 
 #ifdef __powerpc64__
-#define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0))
+#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap((x), s))
 #else
-#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
+#define VGA_MAP_MEM(x,s) (x + vgacon_remap_base)
 #endif
 
 #define vga_readb(x) (*(x))
diff --git a/include/asm-powerpc/vio.h b/include/asm-powerpc/vio.h
index be14c59846f9..dc9bd101ca14 100644
--- a/include/asm-powerpc/vio.h
+++ b/include/asm-powerpc/vio.h
@@ -63,32 +63,22 @@ struct vio_driver {
         struct device_driver driver;
 };
 
-struct vio_bus_ops {
-        int (*match)(const struct vio_device_id *id, const struct vio_dev *dev);
-        void (*unregister_device)(struct vio_dev *);
-        void (*release_device)(struct device *);
-};
-
 extern struct dma_mapping_ops vio_dma_ops;
 extern struct bus_type vio_bus_type;
-extern struct vio_dev vio_bus_device;
 
 extern int vio_register_driver(struct vio_driver *drv);
 extern void vio_unregister_driver(struct vio_driver *drv);
 
-extern struct vio_dev * __devinit vio_register_device(struct vio_dev *viodev);
 extern void __devinit vio_unregister_device(struct vio_dev *dev);
 
-extern int vio_bus_init(struct vio_bus_ops *);
-
-#ifdef CONFIG_PPC_PSERIES
 struct device_node;
 
 extern struct vio_dev * __devinit vio_register_device_node(
                 struct device_node *node_vdev);
-extern struct vio_dev *vio_find_node(struct device_node *vnode);
-extern const void *vio_get_attribute(struct vio_dev *vdev, void *which,
+extern const void *vio_get_attribute(struct vio_dev *vdev, char *which,
                 int *length);
+#ifdef CONFIG_PPC_PSERIES
+extern struct vio_dev *vio_find_node(struct device_node *vnode);
 extern int vio_enable_interrupts(struct vio_dev *dev);
 extern int vio_disable_interrupts(struct vio_dev *dev);
 #endif