5 files changed, 23 insertions, 7 deletions

diff --git a/include/asm-powerpc/dma-mapping.h b/include/asm-powerpc/dma-mapping.h
index f6bd804d9090..744d6bb24116 100644
--- a/include/asm-powerpc/dma-mapping.h
+++ b/include/asm-powerpc/dma-mapping.h
@@ -95,7 +95,7 @@ static inline int dma_set_mask(struct device *dev, u64 dma_mask)
                 return -EIO;
         if (dma_ops->set_dma_mask != NULL)
                 return dma_ops->set_dma_mask(dev, dma_mask);
-        if (!dev->dma_mask || !dma_supported(dev, *dev->dma_mask))
+        if (!dev->dma_mask || !dma_supported(dev, dma_mask))
                 return -EIO;
         *dev->dma_mask = dma_mask;
         return 0;
diff --git a/include/asm-powerpc/mmu-hash64.h b/include/asm-powerpc/mmu-hash64.h
index 695962f02059..3112ad14ad95 100644
--- a/include/asm-powerpc/mmu-hash64.h
+++ b/include/asm-powerpc/mmu-hash64.h
@@ -262,6 +262,7 @@ extern void slb_initialize(void);
 extern void slb_flush_and_rebolt(void);
 extern void stab_initialize(unsigned long stab);
 
+extern void slb_vmalloc_update(void);
 #endif /* __ASSEMBLY__ */
 
 /*
diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h
index 31cbd3d7fce8..33ae9018fe72 100644
--- a/include/asm-powerpc/pgtable-64k.h
+++ b/include/asm-powerpc/pgtable-64k.h
@@ -49,12 +49,10 @@
 
 /* Shift to put page number into pte.
  *
- * That gives us a max RPN of 32 bits, which means a max of 48 bits
- * of addressable physical space.
- * We could get 3 more bits here by setting PTE_RPN_SHIFT to 29 but
- * 32 makes PTEs more readable for debugging for now :)
+ * That gives us a max RPN of 34 bits, which means a max of 50 bits
+ * of addressable physical space, or 46 bits for the special 4k PFNs.
  */
-#define PTE_RPN_SHIFT   (32)
+#define PTE_RPN_SHIFT   (30)
 #define PTE_RPN_MAX     (1UL << (64 - PTE_RPN_SHIFT))
 #define PTE_RPN_MASK    (~((1UL<<PTE_RPN_SHIFT)-1))
 
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 064405c207bf..8fdc2b47afb9 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -223,7 +223,6 @@
 #define MCSR_ICPERR     0x40000000UL /* I-Cache Parity Error */
 #define MCSR_DCP_PERR   0x20000000UL /* D-Cache Push Parity Error */
 #define MCSR_DCPERR     0x10000000UL /* D-Cache Parity Error */
-#define MCSR_GL_CI      0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
 #define MCSR_BUS_IAERR  0x00000080UL /* Instruction Address Error */
 #define MCSR_BUS_RAERR  0x00000040UL /* Read Address Error */
 #define MCSR_BUS_WAERR  0x00000020UL /* Write Address Error */
@@ -232,6 +231,12 @@
 #define MCSR_BUS_WBERR  0x00000004UL /* Write Data Bus Error */
 #define MCSR_BUS_IPERR  0x00000002UL /* Instruction parity Error */
 #define MCSR_BUS_RPERR  0x00000001UL /* Read parity Error */
+
+/* e500 parts may set unused bits in MCSR; mask these off */
+#define MCSR_MASK       (MCSR_MCP | MCSR_ICPERR | MCSR_DCP_PERR | \
+                        MCSR_DCPERR | MCSR_BUS_IAERR | MCSR_BUS_RAERR | \
+                        MCSR_BUS_WAERR | MCSR_BUS_IBERR | MCSR_BUS_RBERR | \
+                        MCSR_BUS_WBERR | MCSR_BUS_IPERR | MCSR_BUS_RPERR)
 #endif
 #ifdef CONFIG_E200
 #define MCSR_MCP        0x80000000UL /* Machine Check Input Pin */
@@ -243,6 +248,11 @@
 #define MCSR_BUS_DRERR  0x00000008UL /* Read Bus Error on data load */
 #define MCSR_BUS_WRERR  0x00000004UL /* Write Bus Error on buffered
                                         store or cache line push */
+
+/* e200 parts may set unused bits in MCSR; mask these off */
+#define MCSR_MASK       (MCSR_MCP | MCSR_CP_PERR | MCSR_CPERR | \
+                        MCSR_EXCP_ERR | MCSR_BUS_IRERR | MCSR_BUS_DRERR | \
+                        MCSR_BUS_WRERR)
 #endif
 
 /* Bit definitions for the DBSR. */
diff --git a/include/asm-powerpc/spu_priv1.h b/include/asm-powerpc/spu_priv1.h
index 7e78f6a1ab8b..0f37c7c90820 100644
--- a/include/asm-powerpc/spu_priv1.h
+++ b/include/asm-powerpc/spu_priv1.h
@@ -178,6 +178,7 @@ struct spu_management_ops {
         int (*enumerate_spus)(int (*fn)(void *data));
         int (*create_spu)(struct spu *spu, void *data);
         int (*destroy_spu)(struct spu *spu);
+        int (*init_affinity)(void);
 };
 
 extern const struct spu_management_ops* spu_management_ops;
@@ -200,6 +201,12 @@ spu_destroy_spu (struct spu *spu)
         return spu_management_ops->destroy_spu(spu);
 }
 
+static inline int
+spu_init_affinity (void)
+{
+        return spu_management_ops->init_affinity();
+}
+
 /*
  * The declarations folowing are put here for convenience
  * and only intended to be used by the platform setup code.