diff options
Diffstat (limited to 'include/asm-powerpc')
| -rw-r--r-- | include/asm-powerpc/reg.h | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index bd467bf5cf5a..0257189d5017 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h | |||
| @@ -153,7 +153,7 @@ | |||
| 153 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ | 153 | #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */ |
| 154 | #define DABR_TRANSLATION (1UL << 2) | 154 | #define DABR_TRANSLATION (1UL << 2) |
| 155 | #define SPRN_DAR 0x013 /* Data Address Register */ | 155 | #define SPRN_DAR 0x013 /* Data Address Register */ |
| 156 | #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ | 156 | #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */ |
| 157 | #define DSISR_NOHPTE 0x40000000 /* no translation found */ | 157 | #define DSISR_NOHPTE 0x40000000 /* no translation found */ |
| 158 | #define DSISR_PROTFAULT 0x08000000 /* protection fault */ | 158 | #define DSISR_PROTFAULT 0x08000000 /* protection fault */ |
| 159 | #define DSISR_ISSTORE 0x02000000 /* access was a store */ | 159 | #define DSISR_ISSTORE 0x02000000 /* access was a store */ |
| @@ -258,16 +258,16 @@ | |||
| 258 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ | 258 | #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ |
| 259 | #define SPRN_HID4 0x3F4 /* 970 HID4 */ | 259 | #define SPRN_HID4 0x3F4 /* 970 HID4 */ |
| 260 | #define SPRN_HID5 0x3F6 /* 970 HID5 */ | 260 | #define SPRN_HID5 0x3F6 /* 970 HID5 */ |
| 261 | #define SPRN_HID6 0x3F9 /* BE HID 6 */ | 261 | #define SPRN_HID6 0x3F9 /* BE HID 6 */ |
| 262 | #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ | 262 | #define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */ |
| 263 | #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ | 263 | #define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */ |
| 264 | #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ | 264 | #define SPRN_TSC_CELL 0x399 /* Thread switch control on Cell */ |
| 265 | #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ | 265 | #define TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */ |
| 266 | #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ | 266 | #define TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */ |
| 267 | #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ | 267 | #define TSC_CELL_EE_ENABLE 0x100000 /* External Interrupt */ |
| 268 | #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ | 268 | #define TSC_CELL_EE_BOOST 0x080000 /* External Interrupt Boost */ |
| 269 | #define SPRN_TSC 0x3FD /* Thread switch control on others */ | 269 | #define SPRN_TSC 0x3FD /* Thread switch control on others */ |
| 270 | #define SPRN_TST 0x3FC /* Thread switch timeout on others */ | 270 | #define SPRN_TST 0x3FC /* Thread switch timeout on others */ |
| 271 | #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) | 271 | #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2) |
| 272 | #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ | 272 | #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ |
| 273 | #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ | 273 | #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ |
| @@ -362,7 +362,7 @@ | |||
| 362 | #endif | 362 | #endif |
| 363 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ | 363 | #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ |
| 364 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ | 364 | #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ |
| 365 | #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ | 365 | #define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */ |
| 366 | #define SPRN_PVR 0x11F /* Processor Version Register */ | 366 | #define SPRN_PVR 0x11F /* Processor Version Register */ |
| 367 | #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ | 367 | #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ |
| 368 | #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ | 368 | #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ |
| @@ -559,20 +559,20 @@ | |||
| 559 | 559 | ||
| 560 | /* 64-bit processors */ | 560 | /* 64-bit processors */ |
| 561 | /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */ | 561 | /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */ |
| 562 | #define PV_NORTHSTAR 0x0033 | 562 | #define PV_NORTHSTAR 0x0033 |
| 563 | #define PV_PULSAR 0x0034 | 563 | #define PV_PULSAR 0x0034 |
| 564 | #define PV_POWER4 0x0035 | 564 | #define PV_POWER4 0x0035 |
| 565 | #define PV_ICESTAR 0x0036 | 565 | #define PV_ICESTAR 0x0036 |
| 566 | #define PV_SSTAR 0x0037 | 566 | #define PV_SSTAR 0x0037 |
| 567 | #define PV_POWER4p 0x0038 | 567 | #define PV_POWER4p 0x0038 |
| 568 | #define PV_970 0x0039 | 568 | #define PV_970 0x0039 |
| 569 | #define PV_POWER5 0x003A | 569 | #define PV_POWER5 0x003A |
| 570 | #define PV_POWER5p 0x003B | 570 | #define PV_POWER5p 0x003B |
| 571 | #define PV_970FX 0x003C | 571 | #define PV_970FX 0x003C |
| 572 | #define PV_630 0x0040 | 572 | #define PV_630 0x0040 |
| 573 | #define PV_630p 0x0041 | 573 | #define PV_630p 0x0041 |
| 574 | #define PV_970MP 0x0044 | 574 | #define PV_970MP 0x0044 |
| 575 | #define PV_BE 0x0070 | 575 | #define PV_BE 0x0070 |
| 576 | 576 | ||
| 577 | /* | 577 | /* |
| 578 | * Number of entries in the SLB. If this ever changes we should handle | 578 | * Number of entries in the SLB. If this ever changes we should handle |