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-rw-r--r--include/asm-powerpc/cpm.h1
-rw-r--r--include/asm-powerpc/immap_86xx.h25
-rw-r--r--include/asm-powerpc/ipic.h12
-rw-r--r--include/asm-powerpc/qe.h95
-rw-r--r--include/asm-powerpc/reg_booke.h13
5 files changed, 91 insertions, 55 deletions
diff --git a/include/asm-powerpc/cpm.h b/include/asm-powerpc/cpm.h
index 48df9f330e76..fae83b137337 100644
--- a/include/asm-powerpc/cpm.h
+++ b/include/asm-powerpc/cpm.h
@@ -10,5 +10,6 @@ int cpm_muram_free(unsigned long offset);
10unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); 10unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
11void __iomem *cpm_muram_addr(unsigned long offset); 11void __iomem *cpm_muram_addr(unsigned long offset);
12dma_addr_t cpm_muram_dma(void __iomem *addr); 12dma_addr_t cpm_muram_dma(void __iomem *addr);
13int cpm_command(u32 command, u8 opcode);
13 14
14#endif 15#endif
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h
index 0ad4e653d464..0f165e59c326 100644
--- a/include/asm-powerpc/immap_86xx.h
+++ b/include/asm-powerpc/immap_86xx.h
@@ -89,14 +89,14 @@ struct ccsr_guts {
89 * them. 89 * them.
90 * 90 *
91 * guts: Pointer to GUTS structure 91 * guts: Pointer to GUTS structure
92 * co: The DMA controller (1 or 2) 92 * co: The DMA controller (0 or 1)
93 * ch: The channel on the DMA controller (0, 1, 2, or 3) 93 * ch: The channel on the DMA controller (0, 1, 2, or 3)
94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) 94 * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx)
95 */ 95 */
96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, 96static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
97 unsigned int co, unsigned int ch, unsigned int device) 97 unsigned int co, unsigned int ch, unsigned int device)
98{ 98{
99 unsigned int shift = 16 + (8 * (2 - co) + 2 * (3 - ch)); 99 unsigned int shift = 16 + (8 * (1 - co) + 2 * (3 - ch));
100 100
101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); 101 clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift);
102} 102}
@@ -118,6 +118,27 @@ static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts,
118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 118#define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002
119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 119#define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001
120 120
121/*
122 * Set the DMA external control bits in the GUTS
123 *
124 * The DMA external control bits in the PMUXCR are only meaningful for
125 * channels 0 and 3. Any other channels are ignored.
126 *
127 * guts: Pointer to GUTS structure
128 * co: The DMA controller (0 or 1)
129 * ch: The channel on the DMA controller (0, 1, 2, or 3)
130 * value: the new value for the bit (0 or 1)
131 */
132static inline void guts_set_pmuxcr_dma(struct ccsr_guts __iomem *guts,
133 unsigned int co, unsigned int ch, unsigned int value)
134{
135 if ((ch == 0) || (ch == 3)) {
136 unsigned int shift = 2 * (co + 1) - (ch & 1) - 1;
137
138 clrsetbits_be32(&guts->pmuxcr, 1 << shift, value << shift);
139 }
140}
141
121#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 142#define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000
122#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 143#define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000
123#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 144#define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000
diff --git a/include/asm-powerpc/ipic.h b/include/asm-powerpc/ipic.h
index edec79dcb7c1..8ff08be00146 100644
--- a/include/asm-powerpc/ipic.h
+++ b/include/asm-powerpc/ipic.h
@@ -20,11 +20,13 @@
20 20
21/* Flags when we init the IPIC */ 21/* Flags when we init the IPIC */
22#define IPIC_SPREADMODE_GRP_A 0x00000001 22#define IPIC_SPREADMODE_GRP_A 0x00000001
23#define IPIC_SPREADMODE_GRP_D 0x00000002 23#define IPIC_SPREADMODE_GRP_B 0x00000002
24#define IPIC_SPREADMODE_MIX_A 0x00000004 24#define IPIC_SPREADMODE_GRP_C 0x00000004
25#define IPIC_SPREADMODE_MIX_B 0x00000008 25#define IPIC_SPREADMODE_GRP_D 0x00000008
26#define IPIC_DISABLE_MCP_OUT 0x00000010 26#define IPIC_SPREADMODE_MIX_A 0x00000010
27#define IPIC_IRQ0_MCP 0x00000020 27#define IPIC_SPREADMODE_MIX_B 0x00000020
28#define IPIC_DISABLE_MCP_OUT 0x00000040
29#define IPIC_IRQ0_MCP 0x00000080
28 30
29/* IPIC registers offsets */ 31/* IPIC registers offsets */
30#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */ 32#define IPIC_SICFR 0x00 /* System Global Interrupt Configuration Register */
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 0dabe46a29d2..a24b7b14958f 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -28,6 +28,52 @@
28#define MEM_PART_SECONDARY 1 28#define MEM_PART_SECONDARY 1
29#define MEM_PART_MURAM 2 29#define MEM_PART_MURAM 2
30 30
31/* Clocks and BRGs */
32enum qe_clock {
33 QE_CLK_NONE = 0,
34 QE_BRG1, /* Baud Rate Generator 1 */
35 QE_BRG2, /* Baud Rate Generator 2 */
36 QE_BRG3, /* Baud Rate Generator 3 */
37 QE_BRG4, /* Baud Rate Generator 4 */
38 QE_BRG5, /* Baud Rate Generator 5 */
39 QE_BRG6, /* Baud Rate Generator 6 */
40 QE_BRG7, /* Baud Rate Generator 7 */
41 QE_BRG8, /* Baud Rate Generator 8 */
42 QE_BRG9, /* Baud Rate Generator 9 */
43 QE_BRG10, /* Baud Rate Generator 10 */
44 QE_BRG11, /* Baud Rate Generator 11 */
45 QE_BRG12, /* Baud Rate Generator 12 */
46 QE_BRG13, /* Baud Rate Generator 13 */
47 QE_BRG14, /* Baud Rate Generator 14 */
48 QE_BRG15, /* Baud Rate Generator 15 */
49 QE_BRG16, /* Baud Rate Generator 16 */
50 QE_CLK1, /* Clock 1 */
51 QE_CLK2, /* Clock 2 */
52 QE_CLK3, /* Clock 3 */
53 QE_CLK4, /* Clock 4 */
54 QE_CLK5, /* Clock 5 */
55 QE_CLK6, /* Clock 6 */
56 QE_CLK7, /* Clock 7 */
57 QE_CLK8, /* Clock 8 */
58 QE_CLK9, /* Clock 9 */
59 QE_CLK10, /* Clock 10 */
60 QE_CLK11, /* Clock 11 */
61 QE_CLK12, /* Clock 12 */
62 QE_CLK13, /* Clock 13 */
63 QE_CLK14, /* Clock 14 */
64 QE_CLK15, /* Clock 15 */
65 QE_CLK16, /* Clock 16 */
66 QE_CLK17, /* Clock 17 */
67 QE_CLK18, /* Clock 18 */
68 QE_CLK19, /* Clock 19 */
69 QE_CLK20, /* Clock 20 */
70 QE_CLK21, /* Clock 21 */
71 QE_CLK22, /* Clock 22 */
72 QE_CLK23, /* Clock 23 */
73 QE_CLK24, /* Clock 24 */
74 QE_CLK_DUMMY
75};
76
31/* Export QE common operations */ 77/* Export QE common operations */
32extern void qe_reset(void); 78extern void qe_reset(void);
33extern int par_io_init(struct device_node *np); 79extern int par_io_init(struct device_node *np);
@@ -38,7 +84,8 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
38 84
39/* QE internal API */ 85/* QE internal API */
40int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 86int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
41void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier); 87enum qe_clock qe_clock_source(const char *source);
88int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
42int qe_get_snum(void); 89int qe_get_snum(void);
43void qe_put_snum(u8 snum); 90void qe_put_snum(u8 snum);
44unsigned long qe_muram_alloc(int size, int align); 91unsigned long qe_muram_alloc(int size, int align);
@@ -129,52 +176,6 @@ enum comm_dir {
129 COMM_DIR_RX_AND_TX = 3 176 COMM_DIR_RX_AND_TX = 3
130}; 177};
131 178
132/* Clocks and BRGs */
133enum qe_clock {
134 QE_CLK_NONE = 0,
135 QE_BRG1, /* Baud Rate Generator 1 */
136 QE_BRG2, /* Baud Rate Generator 2 */
137 QE_BRG3, /* Baud Rate Generator 3 */
138 QE_BRG4, /* Baud Rate Generator 4 */
139 QE_BRG5, /* Baud Rate Generator 5 */
140 QE_BRG6, /* Baud Rate Generator 6 */
141 QE_BRG7, /* Baud Rate Generator 7 */
142 QE_BRG8, /* Baud Rate Generator 8 */
143 QE_BRG9, /* Baud Rate Generator 9 */
144 QE_BRG10, /* Baud Rate Generator 10 */
145 QE_BRG11, /* Baud Rate Generator 11 */
146 QE_BRG12, /* Baud Rate Generator 12 */
147 QE_BRG13, /* Baud Rate Generator 13 */
148 QE_BRG14, /* Baud Rate Generator 14 */
149 QE_BRG15, /* Baud Rate Generator 15 */
150 QE_BRG16, /* Baud Rate Generator 16 */
151 QE_CLK1, /* Clock 1 */
152 QE_CLK2, /* Clock 2 */
153 QE_CLK3, /* Clock 3 */
154 QE_CLK4, /* Clock 4 */
155 QE_CLK5, /* Clock 5 */
156 QE_CLK6, /* Clock 6 */
157 QE_CLK7, /* Clock 7 */
158 QE_CLK8, /* Clock 8 */
159 QE_CLK9, /* Clock 9 */
160 QE_CLK10, /* Clock 10 */
161 QE_CLK11, /* Clock 11 */
162 QE_CLK12, /* Clock 12 */
163 QE_CLK13, /* Clock 13 */
164 QE_CLK14, /* Clock 14 */
165 QE_CLK15, /* Clock 15 */
166 QE_CLK16, /* Clock 16 */
167 QE_CLK17, /* Clock 17 */
168 QE_CLK18, /* Clock 18 */
169 QE_CLK19, /* Clock 19 */
170 QE_CLK20, /* Clock 20 */
171 QE_CLK21, /* Clock 21 */
172 QE_CLK22, /* Clock 22 */
173 QE_CLK23, /* Clock 23 */
174 QE_CLK24, /* Clock 24 */
175 QE_CLK_DUMMY,
176};
177
178/* QE CMXUCR Registers. 179/* QE CMXUCR Registers.
179 * There are two UCCs represented in each of the four CMXUCR registers. 180 * There are two UCCs represented in each of the four CMXUCR registers.
180 * These values are for the UCC in the LSBs 181 * These values are for the UCC in the LSBs
diff --git a/include/asm-powerpc/reg_booke.h b/include/asm-powerpc/reg_booke.h
index 8fdc2b47afb9..98350f0f92c9 100644
--- a/include/asm-powerpc/reg_booke.h
+++ b/include/asm-powerpc/reg_booke.h
@@ -123,16 +123,23 @@
123#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */ 123#define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
124#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */ 124#define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
125#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */ 125#define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
126#define SPRN_ATB 0x20E /* Alternate Time Base */
127#define SPRN_ATBL 0x20E /* Alternate Time Base Lower */
128#define SPRN_ATBU 0x20F /* Alternate Time Base Upper */
126#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */ 129#define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
127#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */ 130#define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
128#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */ 131#define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
129#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */ 132#define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
133#define SPRN_IVOR36 0x214 /* Interrupt Vector Offset Register 36 */
134#define SPRN_IVOR37 0x215 /* Interrupt Vector Offset Register 37 */
130#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */ 135#define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
131#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */ 136#define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
132#define SPRN_MCSR 0x23C /* Machine Check Status Register */ 137#define SPRN_MCSR 0x23C /* Machine Check Status Register */
133#define SPRN_MCAR 0x23D /* Machine Check Address Register */ 138#define SPRN_MCAR 0x23D /* Machine Check Address Register */
134#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */ 139#define SPRN_DSRR0 0x23E /* Debug Save and Restore Register 0 */
135#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */ 140#define SPRN_DSRR1 0x23F /* Debug Save and Restore Register 1 */
141#define SPRN_SPRG8 0x25C /* Special Purpose Register General 8 */
142#define SPRN_SPRG9 0x25D /* Special Purpose Register General 9 */
136#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */ 143#define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
137#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */ 144#define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
138#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */ 145#define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
@@ -140,15 +147,18 @@
140#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */ 147#define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
141#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */ 148#define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
142#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */ 149#define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
143#define SPRN_MAS7 0x3b0 /* MMU Assist Register 7 */
144#define SPRN_PID1 0x279 /* Process ID Register 1 */ 150#define SPRN_PID1 0x279 /* Process ID Register 1 */
145#define SPRN_PID2 0x27A /* Process ID Register 2 */ 151#define SPRN_PID2 0x27A /* Process ID Register 2 */
146#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */ 152#define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
147#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */ 153#define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
154#define SPRN_EPR 0x2BE /* External Proxy Register */
148#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */ 155#define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
149#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */ 156#define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
157#define SPRN_MAS7 0x3B0 /* MMU Assist Register 7 */
150#define SPRN_MMUCR 0x3B2 /* MMU Control Register */ 158#define SPRN_MMUCR 0x3B2 /* MMU Control Register */
151#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */ 159#define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
160#define SPRN_EPLC 0x3B3 /* External Process ID Load Context */
161#define SPRN_EPSC 0x3B4 /* External Process ID Store Context */
152#define SPRN_SGR 0x3B9 /* Storage Guarded Register */ 162#define SPRN_SGR 0x3B9 /* Storage Guarded Register */
153#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */ 163#define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
154#define SPRN_SLER 0x3BB /* Little-endian real mode */ 164#define SPRN_SLER 0x3BB /* Little-endian real mode */
@@ -159,6 +169,7 @@
159#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */ 169#define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
160#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */ 170#define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
161#define SPRN_PIT 0x3DB /* Programmable Interval Timer */ 171#define SPRN_PIT 0x3DB /* Programmable Interval Timer */
172#define SPRN_BUCSR 0x3F5 /* Branch Unit Control and Status */
162#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ 173#define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
163#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */ 174#define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
164#define SPRN_SVR 0x3FF /* System Version Register */ 175#define SPRN_SVR 0x3FF /* System Version Register */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-01 01:55:34 -0500