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-rw-r--r--include/asm-powerpc/a.out.h36
-rw-r--r--include/asm-powerpc/atomic.h209
-rw-r--r--include/asm-powerpc/auxvec.h21
-rw-r--r--include/asm-powerpc/backlight.h31
-rw-r--r--include/asm-powerpc/bug.h81
-rw-r--r--include/asm-powerpc/byteorder.h89
-rw-r--r--include/asm-powerpc/cputable.h427
-rw-r--r--include/asm-powerpc/dbdma.h102
-rw-r--r--include/asm-powerpc/dma.h390
-rw-r--r--include/asm-powerpc/elf.h411
-rw-r--r--include/asm-powerpc/hardirq.h27
-rw-r--r--include/asm-powerpc/heathrow.h62
-rw-r--r--include/asm-powerpc/hw_irq.h114
-rw-r--r--include/asm-powerpc/i8259.h11
-rw-r--r--include/asm-powerpc/iommu.h113
-rw-r--r--include/asm-powerpc/irq.h502
-rw-r--r--include/asm-powerpc/kdebug.h42
-rw-r--r--include/asm-powerpc/keylargo.h248
-rw-r--r--include/asm-powerpc/kmap_types.h33
-rw-r--r--include/asm-powerpc/kprobes.h66
-rw-r--r--include/asm-powerpc/lmb.h81
-rw-r--r--include/asm-powerpc/machdep.h284
-rw-r--r--include/asm-powerpc/macio.h140
-rw-r--r--include/asm-powerpc/mediabay.h31
-rw-r--r--include/asm-powerpc/mpic.h287
-rw-r--r--include/asm-powerpc/of_device.h64
-rw-r--r--include/asm-powerpc/ohare.h48
-rw-r--r--include/asm-powerpc/oprofile_impl.h123
-rw-r--r--include/asm-powerpc/pSeries_reconfig.h25
-rw-r--r--include/asm-powerpc/pmac_feature.h380
-rw-r--r--include/asm-powerpc/pmac_low_i2c.h43
-rw-r--r--include/asm-powerpc/pmc.h46
-rw-r--r--include/asm-powerpc/posix_types.h129
-rw-r--r--include/asm-powerpc/ppc-pci.h54
-rw-r--r--include/asm-powerpc/ppc_asm.h502
-rw-r--r--include/asm-powerpc/processor.h280
-rw-r--r--include/asm-powerpc/prom.h219
-rw-r--r--include/asm-powerpc/reg.h611
-rw-r--r--include/asm-powerpc/rtas.h249
-rw-r--r--include/asm-powerpc/rtc.h78
-rw-r--r--include/asm-powerpc/rwsem.h163
-rw-r--r--include/asm-powerpc/seccomp.h16
-rw-r--r--include/asm-powerpc/sections.h20
-rw-r--r--include/asm-powerpc/semaphore.h98
-rw-r--r--include/asm-powerpc/smu.h379
-rw-r--r--include/asm-powerpc/spinlock_types.h20
-rw-r--r--include/asm-powerpc/statfs.h60
-rw-r--r--include/asm-powerpc/synch.h51
-rw-r--r--include/asm-powerpc/system.h362
-rw-r--r--include/asm-powerpc/thread_info.h135
-rw-r--r--include/asm-powerpc/time.h214
-rw-r--r--include/asm-powerpc/types.h104
-rw-r--r--include/asm-powerpc/uninorth.h229
-rw-r--r--include/asm-powerpc/unistd.h510
-rw-r--r--include/asm-powerpc/vga.h54
-rw-r--r--include/asm-powerpc/xmon.h12
56 files changed, 9116 insertions, 0 deletions
diff --git a/include/asm-powerpc/a.out.h b/include/asm-powerpc/a.out.h
new file mode 100644
index 000000000000..c7393a977364
--- /dev/null
+++ b/include/asm-powerpc/a.out.h
@@ -0,0 +1,36 @@
1#ifndef _ASM_POWERPC_A_OUT_H
2#define _ASM_POWERPC_A_OUT_H
3
4struct exec
5{
6 unsigned long a_info; /* Use macros N_MAGIC, etc for access */
7 unsigned a_text; /* length of text, in bytes */
8 unsigned a_data; /* length of data, in bytes */
9 unsigned a_bss; /* length of uninitialized data area for file, in bytes */
10 unsigned a_syms; /* length of symbol table data in file, in bytes */
11 unsigned a_entry; /* start address */
12 unsigned a_trsize; /* length of relocation info for text, in bytes */
13 unsigned a_drsize; /* length of relocation info for data, in bytes */
14};
15
16#define N_TRSIZE(a) ((a).a_trsize)
17#define N_DRSIZE(a) ((a).a_drsize)
18#define N_SYMSIZE(a) ((a).a_syms)
19
20#ifdef __KERNEL__
21#ifdef __powerpc64__
22
23#define STACK_TOP_USER64 TASK_SIZE_USER64
24#define STACK_TOP_USER32 TASK_SIZE_USER32
25
26#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
27 STACK_TOP_USER32 : STACK_TOP_USER64)
28
29#else /* __powerpc64__ */
30
31#define STACK_TOP TASK_SIZE
32
33#endif /* __powerpc64__ */
34#endif /* __KERNEL__ */
35
36#endif /* _ASM_POWERPC_A_OUT_H */
diff --git a/include/asm-powerpc/atomic.h b/include/asm-powerpc/atomic.h
new file mode 100644
index 000000000000..ed4b345ed75d
--- /dev/null
+++ b/include/asm-powerpc/atomic.h
@@ -0,0 +1,209 @@
1#ifndef _ASM_POWERPC_ATOMIC_H_
2#define _ASM_POWERPC_ATOMIC_H_
3
4/*
5 * PowerPC atomic operations
6 */
7
8typedef struct { volatile int counter; } atomic_t;
9
10#ifdef __KERNEL__
11#include <asm/synch.h>
12
13#define ATOMIC_INIT(i) { (i) }
14
15#define atomic_read(v) ((v)->counter)
16#define atomic_set(v,i) (((v)->counter) = (i))
17
18/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
19 * The old ATOMIC_SYNC_FIX covered some but not all of this.
20 */
21#ifdef CONFIG_IBM405_ERR77
22#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";"
23#else
24#define PPC405_ERR77(ra,rb)
25#endif
26
27static __inline__ void atomic_add(int a, atomic_t *v)
28{
29 int t;
30
31 __asm__ __volatile__(
32"1: lwarx %0,0,%3 # atomic_add\n\
33 add %0,%2,%0\n"
34 PPC405_ERR77(0,%3)
35" stwcx. %0,0,%3 \n\
36 bne- 1b"
37 : "=&r" (t), "=m" (v->counter)
38 : "r" (a), "r" (&v->counter), "m" (v->counter)
39 : "cc");
40}
41
42static __inline__ int atomic_add_return(int a, atomic_t *v)
43{
44 int t;
45
46 __asm__ __volatile__(
47 EIEIO_ON_SMP
48"1: lwarx %0,0,%2 # atomic_add_return\n\
49 add %0,%1,%0\n"
50 PPC405_ERR77(0,%2)
51" stwcx. %0,0,%2 \n\
52 bne- 1b"
53 ISYNC_ON_SMP
54 : "=&r" (t)
55 : "r" (a), "r" (&v->counter)
56 : "cc", "memory");
57
58 return t;
59}
60
61#define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
62
63static __inline__ void atomic_sub(int a, atomic_t *v)
64{
65 int t;
66
67 __asm__ __volatile__(
68"1: lwarx %0,0,%3 # atomic_sub\n\
69 subf %0,%2,%0\n"
70 PPC405_ERR77(0,%3)
71" stwcx. %0,0,%3 \n\
72 bne- 1b"
73 : "=&r" (t), "=m" (v->counter)
74 : "r" (a), "r" (&v->counter), "m" (v->counter)
75 : "cc");
76}
77
78static __inline__ int atomic_sub_return(int a, atomic_t *v)
79{
80 int t;
81
82 __asm__ __volatile__(
83 EIEIO_ON_SMP
84"1: lwarx %0,0,%2 # atomic_sub_return\n\
85 subf %0,%1,%0\n"
86 PPC405_ERR77(0,%2)
87" stwcx. %0,0,%2 \n\
88 bne- 1b"
89 ISYNC_ON_SMP
90 : "=&r" (t)
91 : "r" (a), "r" (&v->counter)
92 : "cc", "memory");
93
94 return t;
95}
96
97static __inline__ void atomic_inc(atomic_t *v)
98{
99 int t;
100
101 __asm__ __volatile__(
102"1: lwarx %0,0,%2 # atomic_inc\n\
103 addic %0,%0,1\n"
104 PPC405_ERR77(0,%2)
105" stwcx. %0,0,%2 \n\
106 bne- 1b"
107 : "=&r" (t), "=m" (v->counter)
108 : "r" (&v->counter), "m" (v->counter)
109 : "cc");
110}
111
112static __inline__ int atomic_inc_return(atomic_t *v)
113{
114 int t;
115
116 __asm__ __volatile__(
117 EIEIO_ON_SMP
118"1: lwarx %0,0,%1 # atomic_inc_return\n\
119 addic %0,%0,1\n"
120 PPC405_ERR77(0,%1)
121" stwcx. %0,0,%1 \n\
122 bne- 1b"
123 ISYNC_ON_SMP
124 : "=&r" (t)
125 : "r" (&v->counter)
126 : "cc", "memory");
127
128 return t;
129}
130
131/*
132 * atomic_inc_and_test - increment and test
133 * @v: pointer of type atomic_t
134 *
135 * Atomically increments @v by 1
136 * and returns true if the result is zero, or false for all
137 * other cases.
138 */
139#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
140
141static __inline__ void atomic_dec(atomic_t *v)
142{
143 int t;
144
145 __asm__ __volatile__(
146"1: lwarx %0,0,%2 # atomic_dec\n\
147 addic %0,%0,-1\n"
148 PPC405_ERR77(0,%2)\
149" stwcx. %0,0,%2\n\
150 bne- 1b"
151 : "=&r" (t), "=m" (v->counter)
152 : "r" (&v->counter), "m" (v->counter)
153 : "cc");
154}
155
156static __inline__ int atomic_dec_return(atomic_t *v)
157{
158 int t;
159
160 __asm__ __volatile__(
161 EIEIO_ON_SMP
162"1: lwarx %0,0,%1 # atomic_dec_return\n\
163 addic %0,%0,-1\n"
164 PPC405_ERR77(0,%1)
165" stwcx. %0,0,%1\n\
166 bne- 1b"
167 ISYNC_ON_SMP
168 : "=&r" (t)
169 : "r" (&v->counter)
170 : "cc", "memory");
171
172 return t;
173}
174
175#define atomic_sub_and_test(a, v) (atomic_sub_return((a), (v)) == 0)
176#define atomic_dec_and_test(v) (atomic_dec_return((v)) == 0)
177
178/*
179 * Atomically test *v and decrement if it is greater than 0.
180 * The function returns the old value of *v minus 1.
181 */
182static __inline__ int atomic_dec_if_positive(atomic_t *v)
183{
184 int t;
185
186 __asm__ __volatile__(
187 EIEIO_ON_SMP
188"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
189 addic. %0,%0,-1\n\
190 blt- 2f\n"
191 PPC405_ERR77(0,%1)
192" stwcx. %0,0,%1\n\
193 bne- 1b"
194 ISYNC_ON_SMP
195 "\n\
1962:" : "=&r" (t)
197 : "r" (&v->counter)
198 : "cc", "memory");
199
200 return t;
201}
202
203#define smp_mb__before_atomic_dec() smp_mb()
204#define smp_mb__after_atomic_dec() smp_mb()
205#define smp_mb__before_atomic_inc() smp_mb()
206#define smp_mb__after_atomic_inc() smp_mb()
207
208#endif /* __KERNEL__ */
209#endif /* _ASM_POWERPC_ATOMIC_H_ */
diff --git a/include/asm-powerpc/auxvec.h b/include/asm-powerpc/auxvec.h
new file mode 100644
index 000000000000..79d8c4732309
--- /dev/null
+++ b/include/asm-powerpc/auxvec.h
@@ -0,0 +1,21 @@
1#ifndef _ASM_POWERPC_AUXVEC_H
2#define _ASM_POWERPC_AUXVEC_H
3
4/*
5 * We need to put in some extra aux table entries to tell glibc what
6 * the cache block size is, so it can use the dcbz instruction safely.
7 */
8#define AT_DCACHEBSIZE 19
9#define AT_ICACHEBSIZE 20
10#define AT_UCACHEBSIZE 21
11/* A special ignored type value for PPC, for glibc compatibility. */
12#define AT_IGNOREPPC 22
13
14/* The vDSO location. We have to use the same value as x86 for glibc's
15 * sake :-)
16 */
17#ifdef __powerpc64__
18#define AT_SYSINFO_EHDR 33
19#endif
20
21#endif
diff --git a/include/asm-powerpc/backlight.h b/include/asm-powerpc/backlight.h
new file mode 100644
index 000000000000..1ba1f27a0b63
--- /dev/null
+++ b/include/asm-powerpc/backlight.h
@@ -0,0 +1,31 @@
1/*
2 * Routines for handling backlight control on PowerBooks
3 *
4 * For now, implementation resides in
5 * arch/powerpc/platforms/powermac/pmac_support.c
6 *
7 */
8#ifndef __ASM_POWERPC_BACKLIGHT_H
9#define __ASM_POWERPC_BACKLIGHT_H
10#ifdef __KERNEL__
11
12/* Abstract values */
13#define BACKLIGHT_OFF 0
14#define BACKLIGHT_MIN 1
15#define BACKLIGHT_MAX 0xf
16
17struct backlight_controller {
18 int (*set_enable)(int enable, int level, void *data);
19 int (*set_level)(int level, void *data);
20};
21
22extern void register_backlight_controller(struct backlight_controller *ctrler, void *data, char *type);
23extern void unregister_backlight_controller(struct backlight_controller *ctrler, void *data);
24
25extern int set_backlight_enable(int enable);
26extern int get_backlight_enable(void);
27extern int set_backlight_level(int level);
28extern int get_backlight_level(void);
29
30#endif /* __KERNEL__ */
31#endif
diff --git a/include/asm-powerpc/bug.h b/include/asm-powerpc/bug.h
new file mode 100644
index 000000000000..e4d028e87020
--- /dev/null
+++ b/include/asm-powerpc/bug.h
@@ -0,0 +1,81 @@
1#ifndef _ASM_POWERPC_BUG_H
2#define _ASM_POWERPC_BUG_H
3
4/*
5 * Define an illegal instr to trap on the bug.
6 * We don't use 0 because that marks the end of a function
7 * in the ELF ABI. That's "Boo Boo" in case you wonder...
8 */
9#define BUG_OPCODE .long 0x00b00b00 /* For asm */
10#define BUG_ILLEGAL_INSTR "0x00b00b00" /* For BUG macro */
11
12#ifndef __ASSEMBLY__
13
14#ifdef __powerpc64__
15#define BUG_TABLE_ENTRY(label, line, file, func) \
16 ".llong " #label "\n .long " #line "\n .llong " #file ", " #func "\n"
17#define TRAP_OP(ra, rb) "1: tdnei " #ra ", " #rb "\n"
18#define DATA_TYPE long long
19#else
20#define BUG_TABLE_ENTRY(label, line, file, func) \
21 ".long " #label ", " #line ", " #file ", " #func "\n"
22#define TRAP_OP(ra, rb) "1: twnei " #ra ", " #rb "\n"
23#define DATA_TYPE int
24#endif /* __powerpc64__ */
25
26struct bug_entry {
27 unsigned long bug_addr;
28 int line;
29 const char *file;
30 const char *function;
31};
32
33struct bug_entry *find_bug(unsigned long bugaddr);
34
35/*
36 * If this bit is set in the line number it means that the trap
37 * is for WARN_ON rather than BUG or BUG_ON.
38 */
39#define BUG_WARNING_TRAP 0x1000000
40
41#ifdef CONFIG_BUG
42
43#define BUG() do { \
44 __asm__ __volatile__( \
45 "1: twi 31,0,0\n" \
46 ".section __bug_table,\"a\"\n\t" \
47 BUG_TABLE_ENTRY(1b,%0,%1,%2) \
48 ".previous" \
49 : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
50} while (0)
51
52#define BUG_ON(x) do { \
53 __asm__ __volatile__( \
54 TRAP_OP(%0,0) \
55 ".section __bug_table,\"a\"\n\t" \
56 BUG_TABLE_ENTRY(1b,%1,%2,%3) \
57 ".previous" \
58 : : "r" ((DATA_TYPE)(x)), "i" (__LINE__), \
59 "i" (__FILE__), "i" (__FUNCTION__)); \
60} while (0)
61
62#define WARN_ON(x) do { \
63 __asm__ __volatile__( \
64 TRAP_OP(%0,0) \
65 ".section __bug_table,\"a\"\n\t" \
66 BUG_TABLE_ENTRY(1b,%1,%2,%3) \
67 ".previous" \
68 : : "r" ((DATA_TYPE)(x)), \
69 "i" (__LINE__ + BUG_WARNING_TRAP), \
70 "i" (__FILE__), "i" (__FUNCTION__)); \
71} while (0)
72
73#define HAVE_ARCH_BUG
74#define HAVE_ARCH_BUG_ON
75#define HAVE_ARCH_WARN_ON
76#endif /* CONFIG_BUG */
77#endif /* __ASSEMBLY __ */
78
79#include <asm-generic/bug.h>
80
81#endif /* _ASM_POWERPC_BUG_H */
diff --git a/include/asm-powerpc/byteorder.h b/include/asm-powerpc/byteorder.h
new file mode 100644
index 000000000000..b37752214a16
--- /dev/null
+++ b/include/asm-powerpc/byteorder.h
@@ -0,0 +1,89 @@
1#ifndef _ASM_POWERPC_BYTEORDER_H
2#define _ASM_POWERPC_BYTEORDER_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11#include <asm/types.h>
12#include <linux/compiler.h>
13
14#ifdef __GNUC__
15#ifdef __KERNEL__
16
17static __inline__ __u16 ld_le16(const volatile __u16 *addr)
18{
19 __u16 val;
20
21 __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
22 return val;
23}
24
25static __inline__ void st_le16(volatile __u16 *addr, const __u16 val)
26{
27 __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
28}
29
30static __inline__ __u32 ld_le32(const volatile __u32 *addr)
31{
32 __u32 val;
33
34 __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (addr), "m" (*addr));
35 return val;
36}
37
38static __inline__ void st_le32(volatile __u32 *addr, const __u32 val)
39{
40 __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr));
41}
42
43static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 value)
44{
45 __u16 result;
46
47 __asm__("rlwimi %0,%1,8,16,23"
48 : "=r" (result)
49 : "r" (value), "0" (value >> 8));
50 return result;
51}
52
53static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 value)
54{
55 __u32 result;
56
57 __asm__("rlwimi %0,%1,24,16,23\n\t"
58 "rlwimi %0,%1,8,8,15\n\t"
59 "rlwimi %0,%1,24,0,7"
60 : "=r" (result)
61 : "r" (value), "0" (value >> 24));
62 return result;
63}
64
65#define __arch__swab16(x) ___arch__swab16(x)
66#define __arch__swab32(x) ___arch__swab32(x)
67
68/* The same, but returns converted value from the location pointer by addr. */
69#define __arch__swab16p(addr) ld_le16(addr)
70#define __arch__swab32p(addr) ld_le32(addr)
71
72/* The same, but do the conversion in situ, ie. put the value back to addr. */
73#define __arch__swab16s(addr) st_le16(addr,*addr)
74#define __arch__swab32s(addr) st_le32(addr,*addr)
75
76#endif /* __KERNEL__ */
77
78#ifndef __STRICT_ANSI__
79#define __BYTEORDER_HAS_U64__
80#ifndef __powerpc64__
81#define __SWAB_64_THRU_32__
82#endif /* __powerpc64__ */
83#endif /* __STRICT_ANSI__ */
84
85#endif /* __GNUC__ */
86
87#include <linux/byteorder/big_endian.h>
88
89#endif /* _ASM_POWERPC_BYTEORDER_H */
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
new file mode 100644
index 000000000000..c019501daceb
--- /dev/null
+++ b/include/asm-powerpc/cputable.h
@@ -0,0 +1,427 @@
1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
4#include <linux/config.h>
5#include <asm/ppc_asm.h> /* for ASM_CONST */
6
7#define PPC_FEATURE_32 0x80000000
8#define PPC_FEATURE_64 0x40000000
9#define PPC_FEATURE_601_INSTR 0x20000000
10#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
11#define PPC_FEATURE_HAS_FPU 0x08000000
12#define PPC_FEATURE_HAS_MMU 0x04000000
13#define PPC_FEATURE_HAS_4xxMAC 0x02000000
14#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
15#define PPC_FEATURE_HAS_SPE 0x00800000
16#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
17#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
18#define PPC_FEATURE_NO_TB 0x00100000
19
20#ifdef __KERNEL__
21#ifndef __ASSEMBLY__
22
23/* This structure can grow, it's real size is used by head.S code
24 * via the mkdefs mechanism.
25 */
26struct cpu_spec;
27struct op_powerpc_model;
28
29typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
30
31struct cpu_spec {
32 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
33 unsigned int pvr_mask;
34 unsigned int pvr_value;
35
36 char *cpu_name;
37 unsigned long cpu_features; /* Kernel features */
38 unsigned int cpu_user_features; /* Userland features */
39
40 /* cache line sizes */
41 unsigned int icache_bsize;
42 unsigned int dcache_bsize;
43
44 /* number of performance monitor counters */
45 unsigned int num_pmcs;
46
47 /* this is called to initialize various CPU bits like L1 cache,
48 * BHT, SPD, etc... from head.S before branching to identify_machine
49 */
50 cpu_setup_t cpu_setup;
51
52 /* Used by oprofile userspace to select the right counters */
53 char *oprofile_cpu_type;
54
55 /* Processor specific oprofile operations */
56 struct op_powerpc_model *oprofile_model;
57};
58
59extern struct cpu_spec *cur_cpu_spec;
60
61extern void identify_cpu(unsigned long offset, unsigned long cpu);
62extern void do_cpu_ftr_fixups(unsigned long offset);
63
64#endif /* __ASSEMBLY__ */
65
66/* CPU kernel features */
67
68/* Retain the 32b definitions all use bottom half of word */
69#define CPU_FTR_SPLIT_ID_CACHE ASM_CONST(0x0000000000000001)
70#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
71#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
72#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
73#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
74#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
75#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
76#define CPU_FTR_604_PERF_MON ASM_CONST(0x0000000000000080)
77#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
78#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
79#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
80#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
81#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
82#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
83#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
84#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
85#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
86#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
87#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
88#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
89
90#ifdef __powerpc64__
91/* Add the 64b processor unique features in the top half of the word */
92#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
93#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
94#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
95#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
96#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000001000000000)
97#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
98#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
99#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
100#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
101#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
102#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
103#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0000080000000000)
104#else
105/* ensure on 32b processors the flags are available for compiling but
106 * don't do anything */
107#define CPU_FTR_SLB ASM_CONST(0x0)
108#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
109#define CPU_FTR_TLBIEL ASM_CONST(0x0)
110#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
111#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0)
112#define CPU_FTR_IABR ASM_CONST(0x0)
113#define CPU_FTR_MMCRA ASM_CONST(0x0)
114#define CPU_FTR_CTRL ASM_CONST(0x0)
115#define CPU_FTR_SMT ASM_CONST(0x0)
116#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
117#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
118#define CPU_FTR_MMCRA_SIHV ASM_CONST(0x0)
119#endif
120
121#ifndef __ASSEMBLY__
122
123#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
124 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
125 CPU_FTR_NODSISRALIGN | CPU_FTR_CTRL)
126
127/* iSeries doesn't support large pages */
128#ifdef CONFIG_PPC_ISERIES
129#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE)
130#else
131#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_PPCAS_ARCH_V2_BASE | CPU_FTR_16M_PAGE)
132#endif /* CONFIG_PPC_ISERIES */
133
134/* We only set the altivec features if the kernel was compiled with altivec
135 * support
136 */
137#ifdef CONFIG_ALTIVEC
138#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
139#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
140#else
141#define CPU_FTR_ALTIVEC_COMP 0
142#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
143#endif
144
145/* We need to mark all pages as being coherent if we're SMP or we
146 * have a 74[45]x and an MPC107 host bridge.
147 */
148#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
149#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
150#else
151#define CPU_FTR_COMMON 0
152#endif
153
154/* The powersave features NAP & DOZE seems to confuse BDI when
155 debugging. So if a BDI is used, disable theses
156 */
157#ifndef CONFIG_BDI_SWITCH
158#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
159#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
160#else
161#define CPU_FTR_MAYBE_CAN_DOZE 0
162#define CPU_FTR_MAYBE_CAN_NAP 0
163#endif
164
165#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
166 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
167 !defined(CONFIG_BOOKE))
168
169enum {
170 CPU_FTRS_PPC601 = CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE,
171 CPU_FTRS_603 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
172 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
173 CPU_FTR_MAYBE_CAN_NAP,
174 CPU_FTRS_604 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
175 CPU_FTR_USE_TB | CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
176 CPU_FTRS_740_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
177 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
178 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
179 CPU_FTRS_740 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
180 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
181 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
182 CPU_FTRS_750 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
183 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
184 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
185 CPU_FTRS_750FX1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
186 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
187 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
188 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
189 CPU_FTRS_750FX2 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
190 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
191 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
192 CPU_FTR_NO_DPM,
193 CPU_FTRS_750FX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
194 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
195 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
196 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
197 CPU_FTRS_750GX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
198 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
199 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
200 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
201 CPU_FTRS_7400_NOTAU = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
202 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
203 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
204 CPU_FTR_MAYBE_CAN_NAP,
205 CPU_FTRS_7400 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
206 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR |
207 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
208 CPU_FTR_MAYBE_CAN_NAP,
209 CPU_FTRS_7450_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
210 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
211 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
212 CPU_FTR_NEED_COHERENT,
213 CPU_FTRS_7450_21 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
214 CPU_FTR_USE_TB |
215 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
216 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
217 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
218 CPU_FTR_NEED_COHERENT,
219 CPU_FTRS_7450_23 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
220 CPU_FTR_USE_TB |
221 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
222 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
223 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
224 CPU_FTRS_7455_1 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
225 CPU_FTR_USE_TB |
226 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
227 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS |
228 CPU_FTR_NEED_COHERENT,
229 CPU_FTRS_7455_20 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
230 CPU_FTR_USE_TB |
231 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
232 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
233 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
234 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
235 CPU_FTRS_7455 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
236 CPU_FTR_USE_TB |
237 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
238 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
239 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
240 CPU_FTR_NEED_COHERENT,
241 CPU_FTRS_7447_10 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
242 CPU_FTR_USE_TB |
243 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
244 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
245 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
246 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
247 CPU_FTRS_7447 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
248 CPU_FTR_USE_TB |
249 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
250 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
251 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
252 CPU_FTR_NEED_COHERENT,
253 CPU_FTRS_7447A = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
254 CPU_FTR_USE_TB |
255 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
256 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
257 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
258 CPU_FTR_NEED_COHERENT,
259 CPU_FTRS_82XX = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
260 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB,
261 CPU_FTRS_G2_LE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
262 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
263 CPU_FTRS_E300 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
264 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
265 CPU_FTRS_CLASSIC32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
266 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
267 CPU_FTRS_POWER3_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
268 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
269 CPU_FTRS_POWER4_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
270 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE,
271 CPU_FTRS_970_32 = CPU_FTR_COMMON | CPU_FTR_SPLIT_ID_CACHE |
272 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_ALTIVEC_COMP |
273 CPU_FTR_MAYBE_CAN_NAP,
274 CPU_FTRS_8XX = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
275 CPU_FTRS_40X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
276 CPU_FTRS_44X = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
277 CPU_FTRS_E200 = CPU_FTR_USE_TB,
278 CPU_FTRS_E500 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB,
279 CPU_FTRS_E500_2 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
280 CPU_FTR_BIG_PHYS,
281 CPU_FTRS_GENERIC_32 = CPU_FTR_COMMON,
282#ifdef __powerpc64__
283 CPU_FTRS_POWER3 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
284 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
285 CPU_FTRS_RS64 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
286 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
287 CPU_FTR_MMCRA | CPU_FTR_CTRL,
288 CPU_FTRS_POWER4 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
289 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
290 CPU_FTRS_PPC970 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
291 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
292 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
293 CPU_FTRS_POWER5 = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
294 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
295 CPU_FTR_MMCRA | CPU_FTR_SMT |
296 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
297 CPU_FTR_MMCRA_SIHV,
298 CPU_FTRS_CELL = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
299 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 |
300 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT,
301 CPU_FTRS_COMPATIBLE = CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
302 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2,
303#endif
304
305 CPU_FTRS_POSSIBLE =
306#if CLASSIC_PPC
307 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
308 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
309 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
310 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
311 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
312 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
313 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
314 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_CLASSIC32 |
315#else
316 CPU_FTRS_GENERIC_32 |
317#endif
318#ifdef CONFIG_PPC64BRIDGE
319 CPU_FTRS_POWER3_32 |
320#endif
321#ifdef CONFIG_POWER4
322 CPU_FTRS_POWER4_32 | CPU_FTRS_970_32 |
323#endif
324#ifdef CONFIG_8xx
325 CPU_FTRS_8XX |
326#endif
327#ifdef CONFIG_40x
328 CPU_FTRS_40X |
329#endif
330#ifdef CONFIG_44x
331 CPU_FTRS_44X |
332#endif
333#ifdef CONFIG_E200
334 CPU_FTRS_E200 |
335#endif
336#ifdef CONFIG_E500
337 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
338#endif
339#ifdef __powerpc64__
340 CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 |
341 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL |
342#endif
343 0,
344
345 CPU_FTRS_ALWAYS =
346#if CLASSIC_PPC
347 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
348 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
349 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
350 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
351 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
352 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
353 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
354 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_CLASSIC32 &
355#else
356 CPU_FTRS_GENERIC_32 &
357#endif
358#ifdef CONFIG_PPC64BRIDGE
359 CPU_FTRS_POWER3_32 &
360#endif
361#ifdef CONFIG_POWER4
362 CPU_FTRS_POWER4_32 & CPU_FTRS_970_32 &
363#endif
364#ifdef CONFIG_8xx
365 CPU_FTRS_8XX &
366#endif
367#ifdef CONFIG_40x
368 CPU_FTRS_40X &
369#endif
370#ifdef CONFIG_44x
371 CPU_FTRS_44X &
372#endif
373#ifdef CONFIG_E200
374 CPU_FTRS_E200 &
375#endif
376#ifdef CONFIG_E500
377 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
378#endif
379#ifdef __powerpc64__
380 CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 &
381 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL &
382#endif
383 CPU_FTRS_POSSIBLE,
384};
385
386static inline int cpu_has_feature(unsigned long feature)
387{
388 return (CPU_FTRS_ALWAYS & feature) ||
389 (CPU_FTRS_POSSIBLE
390 & cur_cpu_spec->cpu_features
391 & feature);
392}
393
394#endif /* !__ASSEMBLY__ */
395
396#ifdef __ASSEMBLY__
397
398#define BEGIN_FTR_SECTION 98:
399
400#ifndef __powerpc64__
401#define END_FTR_SECTION(msk, val) \
40299: \
403 .section __ftr_fixup,"a"; \
404 .align 2; \
405 .long msk; \
406 .long val; \
407 .long 98b; \
408 .long 99b; \
409 .previous
410#else /* __powerpc64__ */
411#define END_FTR_SECTION(msk, val) \
41299: \
413 .section __ftr_fixup,"a"; \
414 .align 3; \
415 .llong msk; \
416 .llong val; \
417 .llong 98b; \
418 .llong 99b; \
419 .previous
420#endif /* __powerpc64__ */
421
422#define END_FTR_SECTION_IFSET(msk) END_FTR_SECTION((msk), (msk))
423#define END_FTR_SECTION_IFCLR(msk) END_FTR_SECTION((msk), 0)
424#endif /* __ASSEMBLY__ */
425
426#endif /* __KERNEL__ */
427#endif /* __ASM_POWERPC_CPUTABLE_H */
diff --git a/include/asm-powerpc/dbdma.h b/include/asm-powerpc/dbdma.h
new file mode 100644
index 000000000000..8973565f95d3
--- /dev/null
+++ b/include/asm-powerpc/dbdma.h
@@ -0,0 +1,102 @@
1/*
2 * Definitions for using the Apple Descriptor-Based DMA controller
3 * in Power Macintosh computers.
4 *
5 * Copyright (C) 1996 Paul Mackerras.
6 */
7
8#ifdef __KERNEL__
9#ifndef _ASM_DBDMA_H_
10#define _ASM_DBDMA_H_
11/*
12 * DBDMA control/status registers. All little-endian.
13 */
14struct dbdma_regs {
15 unsigned int control; /* lets you change bits in status */
16 unsigned int status; /* DMA and device status bits (see below) */
17 unsigned int cmdptr_hi; /* upper 32 bits of command address */
18 unsigned int cmdptr; /* (lower 32 bits of) command address (phys) */
19 unsigned int intr_sel; /* select interrupt condition bit */
20 unsigned int br_sel; /* select branch condition bit */
21 unsigned int wait_sel; /* select wait condition bit */
22 unsigned int xfer_mode;
23 unsigned int data2ptr_hi;
24 unsigned int data2ptr;
25 unsigned int res1;
26 unsigned int address_hi;
27 unsigned int br_addr_hi;
28 unsigned int res2[3];
29};
30
31/* Bits in control and status registers */
32#define RUN 0x8000
33#define PAUSE 0x4000
34#define FLUSH 0x2000
35#define WAKE 0x1000
36#define DEAD 0x0800
37#define ACTIVE 0x0400
38#define BT 0x0100
39#define DEVSTAT 0x00ff
40
41/*
42 * DBDMA command structure. These fields are all little-endian!
43 */
44struct dbdma_cmd {
45 unsigned short req_count; /* requested byte transfer count */
46 unsigned short command; /* command word (has bit-fields) */
47 unsigned int phy_addr; /* physical data address */
48 unsigned int cmd_dep; /* command-dependent field */
49 unsigned short res_count; /* residual count after completion */
50 unsigned short xfer_status; /* transfer status */
51};
52
53/* DBDMA command values in command field */
54#define OUTPUT_MORE 0 /* transfer memory data to stream */
55#define OUTPUT_LAST 0x1000 /* ditto followed by end marker */
56#define INPUT_MORE 0x2000 /* transfer stream data to memory */
57#define INPUT_LAST 0x3000 /* ditto, expect end marker */
58#define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */
59#define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */
60#define DBDMA_NOP 0x6000 /* do nothing */
61#define DBDMA_STOP 0x7000 /* suspend processing */
62
63/* Key values in command field */
64#define KEY_STREAM0 0 /* usual data stream */
65#define KEY_STREAM1 0x100 /* control/status stream */
66#define KEY_STREAM2 0x200 /* device-dependent stream */
67#define KEY_STREAM3 0x300 /* device-dependent stream */
68#define KEY_REGS 0x500 /* device register space */
69#define KEY_SYSTEM 0x600 /* system memory-mapped space */
70#define KEY_DEVICE 0x700 /* device memory-mapped space */
71
72/* Interrupt control values in command field */
73#define INTR_NEVER 0 /* don't interrupt */
74#define INTR_IFSET 0x10 /* intr if condition bit is 1 */
75#define INTR_IFCLR 0x20 /* intr if condition bit is 0 */
76#define INTR_ALWAYS 0x30 /* always interrupt */
77
78/* Branch control values in command field */
79#define BR_NEVER 0 /* don't branch */
80#define BR_IFSET 0x4 /* branch if condition bit is 1 */
81#define BR_IFCLR 0x8 /* branch if condition bit is 0 */
82#define BR_ALWAYS 0xc /* always branch */
83
84/* Wait control values in command field */
85#define WAIT_NEVER 0 /* don't wait */
86#define WAIT_IFSET 1 /* wait if condition bit is 1 */
87#define WAIT_IFCLR 2 /* wait if condition bit is 0 */
88#define WAIT_ALWAYS 3 /* always wait */
89
90/* Align an address for a DBDMA command structure */
91#define DBDMA_ALIGN(x) (((unsigned long)(x) + sizeof(struct dbdma_cmd) - 1) \
92 & -sizeof(struct dbdma_cmd))
93
94/* Useful macros */
95#define DBDMA_DO_STOP(regs) do { \
96 out_le32(&((regs)->control), (RUN|FLUSH)<<16); \
97 while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \
98 ; \
99} while(0)
100
101#endif /* _ASM_DBDMA_H_ */
102#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/dma.h b/include/asm-powerpc/dma.h
new file mode 100644
index 000000000000..926378d2cd94
--- /dev/null
+++ b/include/asm-powerpc/dma.h
@@ -0,0 +1,390 @@
1#ifndef _ASM_POWERPC_DMA_H
2#define _ASM_POWERPC_DMA_H
3
4/*
5 * Defines for using and allocating dma channels.
6 * Written by Hennus Bergman, 1992.
7 * High DMA channel support & info by Hannu Savolainen
8 * and John Boyd, Nov. 1992.
9 * Changes for ppc sound by Christoph Nadig
10 */
11
12/*
13 * Note: Adapted for PowerPC by Gary Thomas
14 * Modified by Cort Dougan <cort@cs.nmt.edu>
15 *
16 * None of this really applies for Power Macintoshes. There is
17 * basically just enough here to get kernel/dma.c to compile.
18 *
19 * There may be some comments or restrictions made here which are
20 * not valid for the PReP platform. Take what you read
21 * with a grain of salt.
22 */
23
24#include <linux/config.h>
25#include <asm/io.h>
26#include <linux/spinlock.h>
27#include <asm/system.h>
28
29#ifndef MAX_DMA_CHANNELS
30#define MAX_DMA_CHANNELS 8
31#endif
32
33/* The maximum address that we can perform a DMA transfer to on this platform */
34/* Doesn't really apply... */
35#define MAX_DMA_ADDRESS (~0UL)
36
37#if !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI)
38
39#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
40#define dma_outb outb_p
41#else
42#define dma_outb outb
43#endif
44
45#define dma_inb inb
46
47/*
48 * NOTES about DMA transfers:
49 *
50 * controller 1: channels 0-3, byte operations, ports 00-1F
51 * controller 2: channels 4-7, word operations, ports C0-DF
52 *
53 * - ALL registers are 8 bits only, regardless of transfer size
54 * - channel 4 is not used - cascades 1 into 2.
55 * - channels 0-3 are byte - addresses/counts are for physical bytes
56 * - channels 5-7 are word - addresses/counts are for physical words
57 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
58 * - transfer count loaded to registers is 1 less than actual count
59 * - controller 2 offsets are all even (2x offsets for controller 1)
60 * - page registers for 5-7 don't use data bit 0, represent 128K pages
61 * - page registers for 0-3 use bit 0, represent 64K pages
62 *
63 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
64 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
65 * Note that addresses loaded into registers must be _physical_ addresses,
66 * not logical addresses (which may differ if paging is active).
67 *
68 * Address mapping for channels 0-3:
69 *
70 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
71 * | ... | | ... | | ... |
72 * | ... | | ... | | ... |
73 * | ... | | ... | | ... |
74 * P7 ... P0 A7 ... A0 A7 ... A0
75 * | Page | Addr MSB | Addr LSB | (DMA registers)
76 *
77 * Address mapping for channels 5-7:
78 *
79 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
80 * | ... | \ \ ... \ \ \ ... \ \
81 * | ... | \ \ ... \ \ \ ... \ (not used)
82 * | ... | \ \ ... \ \ \ ... \
83 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
84 * | Page | Addr MSB | Addr LSB | (DMA registers)
85 *
86 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
87 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
88 * the hardware level, so odd-byte transfers aren't possible).
89 *
90 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
91 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
92 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
93 *
94 */
95
96/* see prep_setup_arch() for detailed informations */
97#if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_PPC_PREP)
98extern long ppc_cs4232_dma, ppc_cs4232_dma2;
99#define SND_DMA1 ppc_cs4232_dma
100#define SND_DMA2 ppc_cs4232_dma2
101#else
102#define SND_DMA1 -1
103#define SND_DMA2 -1
104#endif
105
106/* 8237 DMA controllers */
107#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
108#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
109
110/* DMA controller registers */
111#define DMA1_CMD_REG 0x08 /* command register (w) */
112#define DMA1_STAT_REG 0x08 /* status register (r) */
113#define DMA1_REQ_REG 0x09 /* request register (w) */
114#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
115#define DMA1_MODE_REG 0x0B /* mode register (w) */
116#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
117#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
118#define DMA1_RESET_REG 0x0D /* Master Clear (w) */
119#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
120#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
121
122#define DMA2_CMD_REG 0xD0 /* command register (w) */
123#define DMA2_STAT_REG 0xD0 /* status register (r) */
124#define DMA2_REQ_REG 0xD2 /* request register (w) */
125#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
126#define DMA2_MODE_REG 0xD6 /* mode register (w) */
127#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
128#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
129#define DMA2_RESET_REG 0xDA /* Master Clear (w) */
130#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
131#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
132
133#define DMA_ADDR_0 0x00 /* DMA address registers */
134#define DMA_ADDR_1 0x02
135#define DMA_ADDR_2 0x04
136#define DMA_ADDR_3 0x06
137#define DMA_ADDR_4 0xC0
138#define DMA_ADDR_5 0xC4
139#define DMA_ADDR_6 0xC8
140#define DMA_ADDR_7 0xCC
141
142#define DMA_CNT_0 0x01 /* DMA count registers */
143#define DMA_CNT_1 0x03
144#define DMA_CNT_2 0x05
145#define DMA_CNT_3 0x07
146#define DMA_CNT_4 0xC2
147#define DMA_CNT_5 0xC6
148#define DMA_CNT_6 0xCA
149#define DMA_CNT_7 0xCE
150
151#define DMA_LO_PAGE_0 0x87 /* DMA page registers */
152#define DMA_LO_PAGE_1 0x83
153#define DMA_LO_PAGE_2 0x81
154#define DMA_LO_PAGE_3 0x82
155#define DMA_LO_PAGE_5 0x8B
156#define DMA_LO_PAGE_6 0x89
157#define DMA_LO_PAGE_7 0x8A
158
159#define DMA_HI_PAGE_0 0x487 /* DMA page registers */
160#define DMA_HI_PAGE_1 0x483
161#define DMA_HI_PAGE_2 0x481
162#define DMA_HI_PAGE_3 0x482
163#define DMA_HI_PAGE_5 0x48B
164#define DMA_HI_PAGE_6 0x489
165#define DMA_HI_PAGE_7 0x48A
166
167#define DMA1_EXT_REG 0x40B
168#define DMA2_EXT_REG 0x4D6
169
170#ifndef __powerpc64__
171 /* in arch/ppc/kernel/setup.c -- Cort */
172 extern unsigned int DMA_MODE_WRITE;
173 extern unsigned int DMA_MODE_READ;
174 extern unsigned long ISA_DMA_THRESHOLD;
175#else
176 #define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */
177 #define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */
178#endif
179
180#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
181
182#define DMA_AUTOINIT 0x10
183
184extern spinlock_t dma_spin_lock;
185
186static __inline__ unsigned long claim_dma_lock(void)
187{
188 unsigned long flags;
189 spin_lock_irqsave(&dma_spin_lock, flags);
190 return flags;
191}
192
193static __inline__ void release_dma_lock(unsigned long flags)
194{
195 spin_unlock_irqrestore(&dma_spin_lock, flags);
196}
197
198/* enable/disable a specific DMA channel */
199static __inline__ void enable_dma(unsigned int dmanr)
200{
201 unsigned char ucDmaCmd = 0x00;
202
203 if (dmanr != 4) {
204 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
205 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
206 }
207 if (dmanr <= 3) {
208 dma_outb(dmanr, DMA1_MASK_REG);
209 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
210 } else {
211 dma_outb(dmanr & 3, DMA2_MASK_REG);
212 }
213}
214
215static __inline__ void disable_dma(unsigned int dmanr)
216{
217 if (dmanr <= 3)
218 dma_outb(dmanr | 4, DMA1_MASK_REG);
219 else
220 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
221}
222
223/* Clear the 'DMA Pointer Flip Flop'.
224 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
225 * Use this once to initialize the FF to a known state.
226 * After that, keep track of it. :-)
227 * --- In order to do that, the DMA routines below should ---
228 * --- only be used while interrupts are disabled! ---
229 */
230static __inline__ void clear_dma_ff(unsigned int dmanr)
231{
232 if (dmanr <= 3)
233 dma_outb(0, DMA1_CLEAR_FF_REG);
234 else
235 dma_outb(0, DMA2_CLEAR_FF_REG);
236}
237
238/* set mode (above) for a specific DMA channel */
239static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
240{
241 if (dmanr <= 3)
242 dma_outb(mode | dmanr, DMA1_MODE_REG);
243 else
244 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
245}
246
247/* Set only the page register bits of the transfer address.
248 * This is used for successive transfers when we know the contents of
249 * the lower 16 bits of the DMA current address register, but a 64k boundary
250 * may have been crossed.
251 */
252static __inline__ void set_dma_page(unsigned int dmanr, int pagenr)
253{
254 switch (dmanr) {
255 case 0:
256 dma_outb(pagenr, DMA_LO_PAGE_0);
257 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
258 break;
259 case 1:
260 dma_outb(pagenr, DMA_LO_PAGE_1);
261 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
262 break;
263 case 2:
264 dma_outb(pagenr, DMA_LO_PAGE_2);
265 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
266 break;
267 case 3:
268 dma_outb(pagenr, DMA_LO_PAGE_3);
269 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
270 break;
271 case 5:
272 if (SND_DMA1 == 5 || SND_DMA2 == 5)
273 dma_outb(pagenr, DMA_LO_PAGE_5);
274 else
275 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
276 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
277 break;
278 case 6:
279 if (SND_DMA1 == 6 || SND_DMA2 == 6)
280 dma_outb(pagenr, DMA_LO_PAGE_6);
281 else
282 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
283 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
284 break;
285 case 7:
286 if (SND_DMA1 == 7 || SND_DMA2 == 7)
287 dma_outb(pagenr, DMA_LO_PAGE_7);
288 else
289 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
290 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
291 break;
292 }
293}
294
295/* Set transfer address & page bits for specific DMA channel.
296 * Assumes dma flipflop is clear.
297 */
298static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys)
299{
300 if (dmanr <= 3) {
301 dma_outb(phys & 0xff,
302 ((dmanr & 3) << 1) + IO_DMA1_BASE);
303 dma_outb((phys >> 8) & 0xff,
304 ((dmanr & 3) << 1) + IO_DMA1_BASE);
305 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
306 dma_outb(phys & 0xff,
307 ((dmanr & 3) << 2) + IO_DMA2_BASE);
308 dma_outb((phys >> 8) & 0xff,
309 ((dmanr & 3) << 2) + IO_DMA2_BASE);
310 dma_outb((dmanr & 3), DMA2_EXT_REG);
311 } else {
312 dma_outb((phys >> 1) & 0xff,
313 ((dmanr & 3) << 2) + IO_DMA2_BASE);
314 dma_outb((phys >> 9) & 0xff,
315 ((dmanr & 3) << 2) + IO_DMA2_BASE);
316 }
317 set_dma_page(dmanr, phys >> 16);
318}
319
320
321/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
322 * a specific DMA channel.
323 * You must ensure the parameters are valid.
324 * NOTE: from a manual: "the number of transfers is one more
325 * than the initial word count"! This is taken into account.
326 * Assumes dma flip-flop is clear.
327 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
328 */
329static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
330{
331 count--;
332 if (dmanr <= 3) {
333 dma_outb(count & 0xff,
334 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
335 dma_outb((count >> 8) & 0xff,
336 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
337 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
338 dma_outb(count & 0xff,
339 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
340 dma_outb((count >> 8) & 0xff,
341 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
342 } else {
343 dma_outb((count >> 1) & 0xff,
344 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
345 dma_outb((count >> 9) & 0xff,
346 ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
347 }
348}
349
350
351/* Get DMA residue count. After a DMA transfer, this
352 * should return zero. Reading this while a DMA transfer is
353 * still in progress will return unpredictable results.
354 * If called before the channel has been used, it may return 1.
355 * Otherwise, it returns the number of _bytes_ left to transfer.
356 *
357 * Assumes DMA flip-flop is clear.
358 */
359static __inline__ int get_dma_residue(unsigned int dmanr)
360{
361 unsigned int io_port = (dmanr <= 3)
362 ? ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
363 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
364
365 /* using short to get 16-bit wrap around */
366 unsigned short count;
367
368 count = 1 + dma_inb(io_port);
369 count += dma_inb(io_port) << 8;
370
371 return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
372 ? count : (count << 1);
373}
374
375/* These are in kernel/dma.c: */
376
377/* reserve a DMA channel */
378extern int request_dma(unsigned int dmanr, const char *device_id);
379/* release it again */
380extern void free_dma(unsigned int dmanr);
381
382#ifdef CONFIG_PCI
383extern int isa_dma_bridge_buggy;
384#else
385#define isa_dma_bridge_buggy (0)
386#endif
387
388#endif /* !defined(CONFIG_PPC_ISERIES) || defined(CONFIG_PCI) */
389
390#endif /* _ASM_POWERPC_DMA_H */
diff --git a/include/asm-powerpc/elf.h b/include/asm-powerpc/elf.h
new file mode 100644
index 000000000000..d22b10021b5d
--- /dev/null
+++ b/include/asm-powerpc/elf.h
@@ -0,0 +1,411 @@
1#ifndef _ASM_POWERPC_ELF_H
2#define _ASM_POWERPC_ELF_H
3
4#include <asm/types.h>
5#include <asm/ptrace.h>
6#include <asm/cputable.h>
7#include <asm/auxvec.h>
8#include <asm/page.h>
9
10/* PowerPC relocations defined by the ABIs */
11#define R_PPC_NONE 0
12#define R_PPC_ADDR32 1 /* 32bit absolute address */
13#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */
14#define R_PPC_ADDR16 3 /* 16bit absolute address */
15#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */
16#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */
17#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */
18#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */
19#define R_PPC_ADDR14_BRTAKEN 8
20#define R_PPC_ADDR14_BRNTAKEN 9
21#define R_PPC_REL24 10 /* PC relative 26 bit */
22#define R_PPC_REL14 11 /* PC relative 16 bit */
23#define R_PPC_REL14_BRTAKEN 12
24#define R_PPC_REL14_BRNTAKEN 13
25#define R_PPC_GOT16 14
26#define R_PPC_GOT16_LO 15
27#define R_PPC_GOT16_HI 16
28#define R_PPC_GOT16_HA 17
29#define R_PPC_PLTREL24 18
30#define R_PPC_COPY 19
31#define R_PPC_GLOB_DAT 20
32#define R_PPC_JMP_SLOT 21
33#define R_PPC_RELATIVE 22
34#define R_PPC_LOCAL24PC 23
35#define R_PPC_UADDR32 24
36#define R_PPC_UADDR16 25
37#define R_PPC_REL32 26
38#define R_PPC_PLT32 27
39#define R_PPC_PLTREL32 28
40#define R_PPC_PLT16_LO 29
41#define R_PPC_PLT16_HI 30
42#define R_PPC_PLT16_HA 31
43#define R_PPC_SDAREL16 32
44#define R_PPC_SECTOFF 33
45#define R_PPC_SECTOFF_LO 34
46#define R_PPC_SECTOFF_HI 35
47#define R_PPC_SECTOFF_HA 36
48
49/* PowerPC relocations defined for the TLS access ABI. */
50#define R_PPC_TLS 67 /* none (sym+add)@tls */
51#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */
52#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */
53#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
54#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
55#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
56#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */
57#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */
58#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
59#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
60#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
61#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */
62#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
63#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
64#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
65#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
66#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
67#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
68#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
69#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
70#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */
71#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */
72#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
73#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
74#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */
75#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */
76#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */
77#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */
78
79/* keep this the last entry. */
80#define R_PPC_NUM 95
81
82/*
83 * ELF register definitions..
84 *
85 * This program is free software; you can redistribute it and/or
86 * modify it under the terms of the GNU General Public License
87 * as published by the Free Software Foundation; either version
88 * 2 of the License, or (at your option) any later version.
89 */
90#include <asm/ptrace.h>
91
92#define ELF_NGREG 48 /* includes nip, msr, lr, etc. */
93#define ELF_NFPREG 33 /* includes fpscr */
94
95typedef unsigned long elf_greg_t64;
96typedef elf_greg_t64 elf_gregset_t64[ELF_NGREG];
97
98typedef unsigned int elf_greg_t32;
99typedef elf_greg_t32 elf_gregset_t32[ELF_NGREG];
100
101/*
102 * ELF_ARCH, CLASS, and DATA are used to set parameters in the core dumps.
103 */
104#ifdef __powerpc64__
105# define ELF_NVRREG32 33 /* includes vscr & vrsave stuffed together */
106# define ELF_NVRREG 34 /* includes vscr & vrsave in split vectors */
107# define ELF_GREG_TYPE elf_greg_t64
108#else
109# define ELF_NEVRREG 34 /* includes acc (as 2) */
110# define ELF_NVRREG 33 /* includes vscr */
111# define ELF_GREG_TYPE elf_greg_t32
112# define ELF_ARCH EM_PPC
113# define ELF_CLASS ELFCLASS32
114# define ELF_DATA ELFDATA2MSB
115#endif /* __powerpc64__ */
116
117#ifndef ELF_ARCH
118# define ELF_ARCH EM_PPC64
119# define ELF_CLASS ELFCLASS64
120# define ELF_DATA ELFDATA2MSB
121 typedef elf_greg_t64 elf_greg_t;
122 typedef elf_gregset_t64 elf_gregset_t;
123# define elf_addr_t unsigned long
124#else
125 /* Assumption: ELF_ARCH == EM_PPC and ELF_CLASS == ELFCLASS32 */
126 typedef elf_greg_t32 elf_greg_t;
127 typedef elf_gregset_t32 elf_gregset_t;
128# define elf_addr_t u32
129#endif /* ELF_ARCH */
130
131/* Floating point registers */
132typedef double elf_fpreg_t;
133typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
134
135/* Altivec registers */
136/*
137 * The entries with indexes 0-31 contain the corresponding vector registers.
138 * The entry with index 32 contains the vscr as the last word (offset 12)
139 * within the quadword. This allows the vscr to be stored as either a
140 * quadword (since it must be copied via a vector register to/from storage)
141 * or as a word.
142 *
143 * 64-bit kernel notes: The entry at index 33 contains the vrsave as the first
144 * word (offset 0) within the quadword.
145 *
146 * This definition of the VMX state is compatible with the current PPC32
147 * ptrace interface. This allows signal handling and ptrace to use the same
148 * structures. This also simplifies the implementation of a bi-arch
149 * (combined (32- and 64-bit) gdb.
150 *
151 * Note that it's _not_ compatible with 32 bits ucontext which stuffs the
152 * vrsave along with vscr and so only uses 33 vectors for the register set
153 */
154typedef __vector128 elf_vrreg_t;
155typedef elf_vrreg_t elf_vrregset_t[ELF_NVRREG];
156#ifdef __powerpc64__
157typedef elf_vrreg_t elf_vrregset_t32[ELF_NVRREG32];
158#endif
159
160/*
161 * This is used to ensure we don't load something for the wrong architecture.
162 */
163#define elf_check_arch(x) ((x)->e_machine == ELF_ARCH)
164
165#define USE_ELF_CORE_DUMP
166#define ELF_EXEC_PAGESIZE PAGE_SIZE
167
168/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
169 use of this is to invoke "./ld.so someprog" to test out a new version of
170 the loader. We need to make sure that it is out of the way of the program
171 that it will "exec", and that there is sufficient room for the brk. */
172
173#define ELF_ET_DYN_BASE (0x08000000)
174
175#ifdef __KERNEL__
176
177/* Common routine for both 32-bit and 64-bit processes */
178static inline void ppc_elf_core_copy_regs(elf_gregset_t elf_regs,
179 struct pt_regs *regs)
180{
181 int i;
182 int gprs = sizeof(struct pt_regs)/sizeof(ELF_GREG_TYPE);
183
184 if (gprs > ELF_NGREG)
185 gprs = ELF_NGREG;
186
187 for (i=0; i < gprs; i++)
188 elf_regs[i] = (elf_greg_t)((ELF_GREG_TYPE *)regs)[i];
189
190 memset((char *)(elf_regs) + sizeof(struct pt_regs), 0, \
191 sizeof(elf_gregset_t) - sizeof(struct pt_regs));
192
193}
194#define ELF_CORE_COPY_REGS(gregs, regs) ppc_elf_core_copy_regs(gregs, regs);
195
196static inline int dump_task_regs(struct task_struct *tsk,
197 elf_gregset_t *elf_regs)
198{
199 struct pt_regs *regs = tsk->thread.regs;
200 if (regs)
201 ppc_elf_core_copy_regs(*elf_regs, regs);
202
203 return 1;
204}
205#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
206
207extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
208#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) dump_task_fpu(tsk, elf_fpregs)
209
210#endif /* __KERNEL__ */
211
212/* ELF_HWCAP yields a mask that user programs can use to figure out what
213 instruction set this cpu supports. This could be done in userspace,
214 but it's not easy, and we've already done it here. */
215# define ELF_HWCAP (cur_cpu_spec->cpu_user_features)
216#ifdef __powerpc64__
217# define ELF_PLAT_INIT(_r, load_addr) do { \
218 _r->gpr[2] = load_addr; \
219} while (0)
220#endif /* __powerpc64__ */
221
222/* This yields a string that ld.so will use to load implementation
223 specific libraries for optimization. This is more specific in
224 intent than poking at uname or /proc/cpuinfo.
225
226 For the moment, we have only optimizations for the Intel generations,
227 but that could change... */
228
229#define ELF_PLATFORM (NULL)
230
231#ifdef __KERNEL__
232
233#ifdef __powerpc64__
234# define SET_PERSONALITY(ex, ibcs2) \
235do { \
236 unsigned long new_flags = 0; \
237 if ((ex).e_ident[EI_CLASS] == ELFCLASS32) \
238 new_flags = _TIF_32BIT; \
239 if ((current_thread_info()->flags & _TIF_32BIT) \
240 != new_flags) \
241 set_thread_flag(TIF_ABI_PENDING); \
242 else \
243 clear_thread_flag(TIF_ABI_PENDING); \
244 if (personality(current->personality) != PER_LINUX32) \
245 set_personality(PER_LINUX); \
246} while (0)
247/*
248 * An executable for which elf_read_implies_exec() returns TRUE will
249 * have the READ_IMPLIES_EXEC personality flag set automatically. This
250 * is only required to work around bugs in old 32bit toolchains. Since
251 * the 64bit ABI has never had these issues dont enable the workaround
252 * even if we have an executable stack.
253 */
254# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
255 (exec_stk != EXSTACK_DISABLE_X) : 0)
256#else
257# define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
258#endif /* __powerpc64__ */
259
260#endif /* __KERNEL__ */
261
262extern int dcache_bsize;
263extern int icache_bsize;
264extern int ucache_bsize;
265
266#ifdef __powerpc64__
267struct linux_binprm;
268#define ARCH_HAS_SETUP_ADDITIONAL_PAGES /* vDSO has arch_setup_additional_pages */
269extern int arch_setup_additional_pages(struct linux_binprm *bprm, int executable_stack);
270#define VDSO_AUX_ENT(a,b) NEW_AUX_ENT(a,b);
271#else
272#define VDSO_AUX_ENT(a,b)
273#endif /* __powerpc64__ */
274
275/*
276 * The requirements here are:
277 * - keep the final alignment of sp (sp & 0xf)
278 * - make sure the 32-bit value at the first 16 byte aligned position of
279 * AUXV is greater than 16 for glibc compatibility.
280 * AT_IGNOREPPC is used for that.
281 * - for compatibility with glibc ARCH_DLINFO must always be defined on PPC,
282 * even if DLINFO_ARCH_ITEMS goes to zero or is undefined.
283 */
284#define ARCH_DLINFO \
285do { \
286 /* Handle glibc compatibility. */ \
287 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
288 NEW_AUX_ENT(AT_IGNOREPPC, AT_IGNOREPPC); \
289 /* Cache size items */ \
290 NEW_AUX_ENT(AT_DCACHEBSIZE, dcache_bsize); \
291 NEW_AUX_ENT(AT_ICACHEBSIZE, icache_bsize); \
292 NEW_AUX_ENT(AT_UCACHEBSIZE, ucache_bsize); \
293 VDSO_AUX_ENT(AT_SYSINFO_EHDR, current->thread.vdso_base) \
294} while (0)
295
296/* PowerPC64 relocations defined by the ABIs */
297#define R_PPC64_NONE R_PPC_NONE
298#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address. */
299#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned. */
300#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address. */
301#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of abs. address. */
302#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of abs. address. */
303#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */
304#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned. */
305#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN
306#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN
307#define R_PPC64_REL24 R_PPC_REL24 /* PC relative 26 bit, word aligned. */
308#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit. */
309#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN
310#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN
311#define R_PPC64_GOT16 R_PPC_GOT16
312#define R_PPC64_GOT16_LO R_PPC_GOT16_LO
313#define R_PPC64_GOT16_HI R_PPC_GOT16_HI
314#define R_PPC64_GOT16_HA R_PPC_GOT16_HA
315
316#define R_PPC64_COPY R_PPC_COPY
317#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT
318#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT
319#define R_PPC64_RELATIVE R_PPC_RELATIVE
320
321#define R_PPC64_UADDR32 R_PPC_UADDR32
322#define R_PPC64_UADDR16 R_PPC_UADDR16
323#define R_PPC64_REL32 R_PPC_REL32
324#define R_PPC64_PLT32 R_PPC_PLT32
325#define R_PPC64_PLTREL32 R_PPC_PLTREL32
326#define R_PPC64_PLT16_LO R_PPC_PLT16_LO
327#define R_PPC64_PLT16_HI R_PPC_PLT16_HI
328#define R_PPC64_PLT16_HA R_PPC_PLT16_HA
329
330#define R_PPC64_SECTOFF R_PPC_SECTOFF
331#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO
332#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI
333#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA
334#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2. */
335#define R_PPC64_ADDR64 38 /* doubleword64 S + A. */
336#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A). */
337#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A). */
338#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A). */
339#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A). */
340#define R_PPC64_UADDR64 43 /* doubleword64 S + A. */
341#define R_PPC64_REL64 44 /* doubleword64 S + A - P. */
342#define R_PPC64_PLT64 45 /* doubleword64 L + A. */
343#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P. */
344#define R_PPC64_TOC16 47 /* half16* S + A - .TOC. */
345#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.). */
346#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.). */
347#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.). */
348#define R_PPC64_TOC 51 /* doubleword64 .TOC. */
349#define R_PPC64_PLTGOT16 52 /* half16* M + A. */
350#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A). */
351#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A). */
352#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A). */
353
354#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2. */
355#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2. */
356#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2. */
357#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2. */
358#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2. */
359#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2. */
360#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2. */
361#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2. */
362#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2. */
363#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2. */
364#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2. */
365
366/* PowerPC64 relocations defined for the TLS access ABI. */
367#define R_PPC64_TLS 67 /* none (sym+add)@tls */
368#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */
369#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */
370#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */
371#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */
372#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */
373#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */
374#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */
375#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */
376#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */
377#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */
378#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */
379#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */
380#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */
381#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */
382#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */
383#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */
384#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */
385#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */
386#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */
387#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */
388#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */
389#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */
390#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */
391#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */
392#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */
393#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */
394#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */
395#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */
396#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */
397#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */
398#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */
399#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */
400#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */
401#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */
402#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */
403#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */
404#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */
405#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */
406#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */
407
408/* Keep this the last entry. */
409#define R_PPC64_NUM 107
410
411#endif /* _ASM_POWERPC_ELF_H */
diff --git a/include/asm-powerpc/hardirq.h b/include/asm-powerpc/hardirq.h
new file mode 100644
index 000000000000..3b3e3b49ec12
--- /dev/null
+++ b/include/asm-powerpc/hardirq.h
@@ -0,0 +1,27 @@
1#ifndef _ASM_POWERPC_HARDIRQ_H
2#define _ASM_POWERPC_HARDIRQ_H
3
4#include <asm/irq.h>
5#include <asm/bug.h>
6
7/* The __last_jiffy_stamp field is needed to ensure that no decrementer
8 * interrupt is lost on SMP machines. Since on most CPUs it is in the same
9 * cache line as local_irq_count, it is cheap to access and is also used on UP
10 * for uniformity.
11 */
12typedef struct {
13 unsigned int __softirq_pending; /* set_bit is used on this */
14 unsigned int __last_jiffy_stamp;
15} ____cacheline_aligned irq_cpustat_t;
16
17#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
18
19#define last_jiffy_stamp(cpu) __IRQ_STAT((cpu), __last_jiffy_stamp)
20
21static inline void ack_bad_irq(int irq)
22{
23 printk(KERN_CRIT "illegal vector %d received!\n", irq);
24 BUG();
25}
26
27#endif /* _ASM_POWERPC_HARDIRQ_H */
diff --git a/include/asm-powerpc/heathrow.h b/include/asm-powerpc/heathrow.h
new file mode 100644
index 000000000000..22ac179856b9
--- /dev/null
+++ b/include/asm-powerpc/heathrow.h
@@ -0,0 +1,62 @@
1/*
2 * heathrow.h: definitions for using the "Heathrow" I/O controller chip.
3 *
4 * Grabbed from Open Firmware definitions on a PowerBook G3 Series
5 *
6 * Copyright (C) 1997 Paul Mackerras.
7 */
8
9/* Front light color on Yikes/B&W G3. 32 bits */
10#define HEATHROW_FRONT_LIGHT 0x32 /* (set to 0 or 0xffffffff) */
11
12/* Brightness/contrast (gossamer iMac ?). 8 bits */
13#define HEATHROW_BRIGHTNESS_CNTL 0x32
14#define HEATHROW_CONTRAST_CNTL 0x33
15
16/* offset from ohare base for feature control register */
17#define HEATHROW_MBCR 0x34 /* Media bay control */
18#define HEATHROW_FCR 0x38 /* Feature control */
19#define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */
20
21/*
22 * Bits in feature control register.
23 * Bits postfixed with a _N are in inverse logic
24 */
25#define HRW_SCC_TRANS_EN_N 0x00000001 /* Also controls modem power */
26#define HRW_BAY_POWER_N 0x00000002
27#define HRW_BAY_PCI_ENABLE 0x00000004
28#define HRW_BAY_IDE_ENABLE 0x00000008
29#define HRW_BAY_FLOPPY_ENABLE 0x00000010
30#define HRW_IDE0_ENABLE 0x00000020
31#define HRW_IDE0_RESET_N 0x00000040
32#define HRW_BAY_DEV_MASK 0x0000001c
33#define HRW_BAY_RESET_N 0x00000080
34#define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */
35#define HRW_SCC_ENABLE 0x00000200
36#define HRW_MESH_ENABLE 0x00000400
37#define HRW_SWIM_ENABLE 0x00000800
38#define HRW_SOUND_POWER_N 0x00001000
39#define HRW_SOUND_CLK_ENABLE 0x00002000
40#define HRW_SCCA_IO 0x00004000
41#define HRW_SCCB_IO 0x00008000
42#define HRW_PORT_OR_DESK_VIA_N 0x00010000 /* This one is 0 on PowerBook */
43#define HRW_PWM_MON_ID_N 0x00020000 /* ??? (0) */
44#define HRW_HOOK_MB_CNT_N 0x00040000 /* ??? (0) */
45#define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */
46#define HRW_AUD_RUN22 0x00100000 /* ??? (1) */
47#define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */
48#define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */
49#define HRW_IDE1_RESET_N 0x00800000 /* Media bay */
50#define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */
51#define HRW_RESET_SCC 0x02000000
52#define HRW_MFDC_CELL_ENABLE 0x04000000 /* ??? (0) */
53#define HRW_USE_MFDC 0x08000000 /* ??? (0) */
54#define HRW_BMAC_IO_ENABLE 0x60000000 /* two bits, not documented in OF */
55#define HRW_BMAC_RESET 0x80000000 /* not documented in OF */
56
57/* We OR those features at boot on desktop G3s */
58#define HRW_DEFAULTS (HRW_SCCA_IO | HRW_SCCB_IO | HRW_SCC_ENABLE)
59
60/* Looks like Heathrow has some sort of GPIOs as well... */
61#define HRW_GPIO_MODEM_RESET 0x6d
62
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
new file mode 100644
index 000000000000..c37b31b96337
--- /dev/null
+++ b/include/asm-powerpc/hw_irq.h
@@ -0,0 +1,114 @@
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifndef _ASM_POWERPC_HW_IRQ_H
5#define _ASM_POWERPC_HW_IRQ_H
6
7#ifdef __KERNEL__
8
9#include <linux/config.h>
10#include <linux/errno.h>
11#include <asm/ptrace.h>
12#include <asm/processor.h>
13
14extern void timer_interrupt(struct pt_regs *);
15extern void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq);
16
17#ifdef CONFIG_PPC_ISERIES
18
19extern unsigned long local_get_flags(void);
20extern unsigned long local_irq_disable(void);
21extern void local_irq_restore(unsigned long);
22
23#define local_irq_enable() local_irq_restore(1)
24#define local_save_flags(flags) ((flags) = local_get_flags())
25#define local_irq_save(flags) ((flags) = local_irq_disable())
26
27#define irqs_disabled() (local_get_flags() == 0)
28
29#else
30
31#if defined(CONFIG_BOOKE)
32#define SET_MSR_EE(x) mtmsr(x)
33#define local_irq_restore(flags) __asm__ __volatile__("wrtee %0" : : "r" (flags) : "memory")
34#elif defined(__powerpc64__)
35#define SET_MSR_EE(x) __mtmsrd(x, 1)
36#define local_irq_restore(flags) do { \
37 __asm__ __volatile__("": : :"memory"); \
38 __mtmsrd((flags), 1); \
39} while(0)
40#else
41#define SET_MSR_EE(x) mtmsr(x)
42#define local_irq_restore(flags) mtmsr(flags)
43#endif
44
45static inline void local_irq_disable(void)
46{
47#ifdef CONFIG_BOOKE
48 __asm__ __volatile__("wrteei 0": : :"memory");
49#else
50 unsigned long msr;
51 __asm__ __volatile__("": : :"memory");
52 msr = mfmsr();
53 SET_MSR_EE(msr & ~MSR_EE);
54#endif
55}
56
57static inline void local_irq_enable(void)
58{
59#ifdef CONFIG_BOOKE
60 __asm__ __volatile__("wrteei 1": : :"memory");
61#else
62 unsigned long msr;
63 __asm__ __volatile__("": : :"memory");
64 msr = mfmsr();
65 SET_MSR_EE(msr | MSR_EE);
66#endif
67}
68
69static inline void local_irq_save_ptr(unsigned long *flags)
70{
71 unsigned long msr;
72 msr = mfmsr();
73 *flags = msr;
74#ifdef CONFIG_BOOKE
75 __asm__ __volatile__("wrteei 0": : :"memory");
76#else
77 SET_MSR_EE(msr & ~MSR_EE);
78#endif
79 __asm__ __volatile__("": : :"memory");
80}
81
82#define local_save_flags(flags) ((flags) = mfmsr())
83#define local_irq_save(flags) local_irq_save_ptr(&flags)
84#define irqs_disabled() ((mfmsr() & MSR_EE) == 0)
85
86#endif /* CONFIG_PPC_ISERIES */
87
88#define mask_irq(irq) \
89 ({ \
90 irq_desc_t *desc = get_irq_desc(irq); \
91 if (desc->handler && desc->handler->disable) \
92 desc->handler->disable(irq); \
93 })
94#define unmask_irq(irq) \
95 ({ \
96 irq_desc_t *desc = get_irq_desc(irq); \
97 if (desc->handler && desc->handler->enable) \
98 desc->handler->enable(irq); \
99 })
100#define ack_irq(irq) \
101 ({ \
102 irq_desc_t *desc = get_irq_desc(irq); \
103 if (desc->handler && desc->handler->ack) \
104 desc->handler->ack(irq); \
105 })
106
107/* Should we handle this via lost interrupts and IPIs or should we don't care like
108 * we do now ? --BenH.
109 */
110struct hw_interrupt_type;
111static inline void hw_resend_irq(struct hw_interrupt_type *h, unsigned int i) {}
112
113#endif /* __KERNEL__ */
114#endif /* _ASM_POWERPC_HW_IRQ_H */
diff --git a/include/asm-powerpc/i8259.h b/include/asm-powerpc/i8259.h
new file mode 100644
index 000000000000..9521ad47740f
--- /dev/null
+++ b/include/asm-powerpc/i8259.h
@@ -0,0 +1,11 @@
1#ifndef _ASM_POWERPC_I8259_H
2#define _ASM_POWERPC_I8259_H
3
4#include <linux/irq.h>
5
6extern struct hw_interrupt_type i8259_pic;
7
8extern void i8259_init(long intack_addr);
9extern int i8259_irq(struct pt_regs *regs);
10
11#endif /* _ASM_POWERPC_I8259_H */
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
new file mode 100644
index 000000000000..9d91bdd667ae
--- /dev/null
+++ b/include/asm-powerpc/iommu.h
@@ -0,0 +1,113 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 * Rewrite, cleanup:
4 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_IOMMU_H
22#define _ASM_IOMMU_H
23
24#include <linux/config.h>
25#include <asm/types.h>
26#include <linux/spinlock.h>
27#include <linux/device.h>
28#include <linux/dma-mapping.h>
29
30/*
31 * IOMAP_MAX_ORDER defines the largest contiguous block
32 * of dma space we can get. IOMAP_MAX_ORDER = 13
33 * allows up to 2**12 pages (4096 * 4096) = 16 MB
34 */
35#define IOMAP_MAX_ORDER 13
36
37struct iommu_table {
38 unsigned long it_busno; /* Bus number this table belongs to */
39 unsigned long it_size; /* Size of iommu table in entries */
40 unsigned long it_offset; /* Offset into global table */
41 unsigned long it_base; /* mapped address of tce table */
42 unsigned long it_index; /* which iommu table this is */
43 unsigned long it_type; /* type: PCI or Virtual Bus */
44 unsigned long it_blocksize; /* Entries in each block (cacheline) */
45 unsigned long it_hint; /* Hint for next alloc */
46 unsigned long it_largehint; /* Hint for large allocs */
47 unsigned long it_halfpoint; /* Breaking point for small/large allocs */
48 spinlock_t it_lock; /* Protects it_map */
49 unsigned long *it_map; /* A simple allocation bitmap for now */
50};
51
52struct scatterlist;
53struct device_node;
54
55#ifdef CONFIG_PPC_MULTIPLATFORM
56
57/* Walks all buses and creates iommu tables */
58extern void iommu_setup_pSeries(void);
59extern void iommu_setup_u3(void);
60
61/* Frees table for an individual device node */
62extern void iommu_free_table(struct device_node *dn);
63
64#endif /* CONFIG_PPC_MULTIPLATFORM */
65
66#ifdef CONFIG_PPC_PSERIES
67
68/* Creates table for an individual device node */
69extern void iommu_devnode_init_pSeries(struct device_node *dn);
70
71#endif /* CONFIG_PPC_PSERIES */
72
73#ifdef CONFIG_PPC_ISERIES
74
75/* Creates table for an individual device node */
76extern void iommu_devnode_init_iSeries(struct device_node *dn);
77
78#endif /* CONFIG_PPC_ISERIES */
79
80/* Initializes an iommu_table based in values set in the passed-in
81 * structure
82 */
83extern struct iommu_table *iommu_init_table(struct iommu_table * tbl);
84
85extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
86 struct scatterlist *sglist, int nelems,
87 enum dma_data_direction direction);
88extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
89 int nelems, enum dma_data_direction direction);
90
91extern void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
92 dma_addr_t *dma_handle, gfp_t flag);
93extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
94 void *vaddr, dma_addr_t dma_handle);
95extern dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
96 size_t size, enum dma_data_direction direction);
97extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
98 size_t size, enum dma_data_direction direction);
99
100extern void iommu_init_early_pSeries(void);
101extern void iommu_init_early_iSeries(void);
102extern void iommu_init_early_u3(void);
103
104#ifdef CONFIG_PCI
105extern void pci_iommu_init(void);
106extern void pci_direct_iommu_init(void);
107#else
108static inline void pci_iommu_init(void) { }
109#endif
110
111extern void alloc_u3_dart_table(void);
112
113#endif /* _ASM_IOMMU_H */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
new file mode 100644
index 000000000000..07c2b3fc4c66
--- /dev/null
+++ b/include/asm-powerpc/irq.h
@@ -0,0 +1,502 @@
1#ifdef __KERNEL__
2#ifndef _ASM_POWERPC_IRQ_H
3#define _ASM_POWERPC_IRQ_H
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/config.h>
13#include <linux/threads.h>
14
15#include <asm/types.h>
16#include <asm/atomic.h>
17
18/* this number is used when no interrupt has been assigned */
19#define NO_IRQ (-1)
20
21/*
22 * These constants are used for passing information about interrupt
23 * signal polarity and level/edge sensing to the low-level PIC chip
24 * drivers.
25 */
26#define IRQ_SENSE_MASK 0x1
27#define IRQ_SENSE_LEVEL 0x1 /* interrupt on active level */
28#define IRQ_SENSE_EDGE 0x0 /* interrupt triggered by edge */
29
30#define IRQ_POLARITY_MASK 0x2
31#define IRQ_POLARITY_POSITIVE 0x2 /* high level or low->high edge */
32#define IRQ_POLARITY_NEGATIVE 0x0 /* low level or high->low edge */
33
34/*
35 * IRQ line status macro IRQ_PER_CPU is used
36 */
37#define ARCH_HAS_IRQ_PER_CPU
38
39#define get_irq_desc(irq) (&irq_desc[(irq)])
40
41/* Define a way to iterate across irqs. */
42#define for_each_irq(i) \
43 for ((i) = 0; (i) < NR_IRQS; ++(i))
44
45#ifdef CONFIG_PPC64
46
47/*
48 * Maximum number of interrupt sources that we can handle.
49 */
50#define NR_IRQS 512
51
52/* Interrupt numbers are virtual in case they are sparsely
53 * distributed by the hardware.
54 */
55extern unsigned int virt_irq_to_real_map[NR_IRQS];
56
57/* Create a mapping for a real_irq if it doesn't already exist.
58 * Return the virtual irq as a convenience.
59 */
60int virt_irq_create_mapping(unsigned int real_irq);
61void virt_irq_init(void);
62
63static inline unsigned int virt_irq_to_real(unsigned int virt_irq)
64{
65 return virt_irq_to_real_map[virt_irq];
66}
67
68extern unsigned int real_irq_to_virt_slowpath(unsigned int real_irq);
69
70/*
71 * List of interrupt controllers.
72 */
73#define IC_INVALID 0
74#define IC_OPEN_PIC 1
75#define IC_PPC_XIC 2
76#define IC_BPA_IIC 3
77#define IC_ISERIES 4
78
79extern u64 ppc64_interrupt_controller;
80
81#else /* 32-bit */
82
83#if defined(CONFIG_40x)
84#include <asm/ibm4xx.h>
85
86#ifndef NR_BOARD_IRQS
87#define NR_BOARD_IRQS 0
88#endif
89
90#ifndef UIC_WIDTH /* Number of interrupts per device */
91#define UIC_WIDTH 32
92#endif
93
94#ifndef NR_UICS /* number of UIC devices */
95#define NR_UICS 1
96#endif
97
98#if defined (CONFIG_403)
99/*
100 * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has
101 * 32 possible interrupts, a majority of which are not implemented on
102 * all cores. There are six configurable, external interrupt pins and
103 * there are eight internal interrupts for the on-chip serial port
104 * (SPU), DMA controller, and JTAG controller.
105 *
106 */
107
108#define NR_AIC_IRQS 32
109#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS)
110
111#elif !defined (CONFIG_403)
112
113/*
114 * The PowerPC 405 cores' Universal Interrupt Controller (UIC) has 32
115 * possible interrupts as well. There are seven, configurable external
116 * interrupt pins and there are 17 internal interrupts for the on-chip
117 * serial port, DMA controller, on-chip Ethernet controller, PCI, etc.
118 *
119 */
120
121
122#define NR_UIC_IRQS UIC_WIDTH
123#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
124#endif
125
126#elif defined(CONFIG_44x)
127#include <asm/ibm44x.h>
128
129#define NR_UIC_IRQS 32
130#define NR_IRQS ((NR_UIC_IRQS * NR_UICS) + NR_BOARD_IRQS)
131
132#elif defined(CONFIG_8xx)
133
134/* Now include the board configuration specific associations.
135*/
136#include <asm/mpc8xx.h>
137
138/* The MPC8xx cores have 16 possible interrupts. There are eight
139 * possible level sensitive interrupts assigned and generated internally
140 * from such devices as CPM, PCMCIA, RTC, PIT, TimeBase and Decrementer.
141 * There are eight external interrupts (IRQs) that can be configured
142 * as either level or edge sensitive.
143 *
144 * On some implementations, there is also the possibility of an 8259
145 * through the PCI and PCI-ISA bridges.
146 *
147 * We are "flattening" the interrupt vectors of the cascaded CPM
148 * and 8259 interrupt controllers so that we can uniquely identify
149 * any interrupt source with a single integer.
150 */
151#define NR_SIU_INTS 16
152#define NR_CPM_INTS 32
153#ifndef NR_8259_INTS
154#define NR_8259_INTS 0
155#endif
156
157#define SIU_IRQ_OFFSET 0
158#define CPM_IRQ_OFFSET (SIU_IRQ_OFFSET + NR_SIU_INTS)
159#define I8259_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
160
161#define NR_IRQS (NR_SIU_INTS + NR_CPM_INTS + NR_8259_INTS)
162
163/* These values must be zero-based and map 1:1 with the SIU configuration.
164 * They are used throughout the 8xx I/O subsystem to generate
165 * interrupt masks, flags, and other control patterns. This is why the
166 * current kernel assumption of the 8259 as the base controller is such
167 * a pain in the butt.
168 */
169#define SIU_IRQ0 (0) /* Highest priority */
170#define SIU_LEVEL0 (1)
171#define SIU_IRQ1 (2)
172#define SIU_LEVEL1 (3)
173#define SIU_IRQ2 (4)
174#define SIU_LEVEL2 (5)
175#define SIU_IRQ3 (6)
176#define SIU_LEVEL3 (7)
177#define SIU_IRQ4 (8)
178#define SIU_LEVEL4 (9)
179#define SIU_IRQ5 (10)
180#define SIU_LEVEL5 (11)
181#define SIU_IRQ6 (12)
182#define SIU_LEVEL6 (13)
183#define SIU_IRQ7 (14)
184#define SIU_LEVEL7 (15)
185
186#define MPC8xx_INT_FEC1 SIU_LEVEL1
187#define MPC8xx_INT_FEC2 SIU_LEVEL3
188
189#define MPC8xx_INT_SCC1 (CPM_IRQ_OFFSET + CPMVEC_SCC1)
190#define MPC8xx_INT_SCC2 (CPM_IRQ_OFFSET + CPMVEC_SCC2)
191#define MPC8xx_INT_SCC3 (CPM_IRQ_OFFSET + CPMVEC_SCC3)
192#define MPC8xx_INT_SCC4 (CPM_IRQ_OFFSET + CPMVEC_SCC4)
193#define MPC8xx_INT_SMC1 (CPM_IRQ_OFFSET + CPMVEC_SMC1)
194#define MPC8xx_INT_SMC2 (CPM_IRQ_OFFSET + CPMVEC_SMC2)
195
196/* The internal interrupts we can configure as we see fit.
197 * My personal preference is CPM at level 2, which puts it above the
198 * MBX PCI/ISA/IDE interrupts.
199 */
200#ifndef PIT_INTERRUPT
201#define PIT_INTERRUPT SIU_LEVEL0
202#endif
203#ifndef CPM_INTERRUPT
204#define CPM_INTERRUPT SIU_LEVEL2
205#endif
206#ifndef PCMCIA_INTERRUPT
207#define PCMCIA_INTERRUPT SIU_LEVEL6
208#endif
209#ifndef DEC_INTERRUPT
210#define DEC_INTERRUPT SIU_LEVEL7
211#endif
212
213/* Some internal interrupt registers use an 8-bit mask for the interrupt
214 * level instead of a number.
215 */
216#define mk_int_int_mask(IL) (1 << (7 - (IL/2)))
217
218#elif defined(CONFIG_83xx)
219#include <asm/mpc83xx.h>
220
221#define NR_IRQS (NR_IPIC_INTS)
222
223#elif defined(CONFIG_85xx)
224/* Now include the board configuration specific associations.
225*/
226#include <asm/mpc85xx.h>
227
228/* The MPC8548 openpic has 48 internal interrupts and 12 external
229 * interrupts.
230 *
231 * We are "flattening" the interrupt vectors of the cascaded CPM
232 * so that we can uniquely identify any interrupt source with a
233 * single integer.
234 */
235#define NR_CPM_INTS 64
236#define NR_EPIC_INTS 60
237#ifndef NR_8259_INTS
238#define NR_8259_INTS 0
239#endif
240#define NUM_8259_INTERRUPTS NR_8259_INTS
241
242#ifndef CPM_IRQ_OFFSET
243#define CPM_IRQ_OFFSET 0
244#endif
245
246#define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS)
247
248/* Internal IRQs on MPC85xx OpenPIC */
249
250#ifndef MPC85xx_OPENPIC_IRQ_OFFSET
251#ifdef CONFIG_CPM2
252#define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS)
253#else
254#define MPC85xx_OPENPIC_IRQ_OFFSET 0
255#endif
256#endif
257
258/* Not all of these exist on all MPC85xx implementations */
259#define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET)
260#define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET)
261#define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET)
262#define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET)
263#define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET)
264#define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET)
265#define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET)
266#define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET)
267#define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET)
268#define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
269#define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET)
270#define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET)
271#define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET)
272#define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET)
273#define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET)
274#define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET)
275#define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET)
276#define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET)
277#define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET)
278#define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET)
279#define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET)
280#define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET)
281#define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET)
282#define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET)
283#define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET)
284#define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET)
285#define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET)
286#define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET)
287#define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET)
288#define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET)
289#define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET)
290#define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET)
291
292/* The 12 external interrupt lines */
293#define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET)
294#define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET)
295#define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET)
296#define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET)
297#define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET)
298#define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET)
299#define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET)
300#define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET)
301#define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET)
302#define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET)
303#define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET)
304#define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET)
305
306/* CPM related interrupts */
307#define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET)
308#define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET)
309#define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET)
310#define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET)
311#define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET)
312#define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET)
313#define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET)
314#define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET)
315#define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET)
316#define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET)
317#define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET)
318#define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET)
319#define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET)
320#define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET)
321#define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET)
322#define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET)
323#define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET)
324#define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET)
325#define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET)
326#define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET)
327#define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET)
328#define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET)
329#define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET)
330#define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET)
331#define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET)
332#define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET)
333#define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET)
334#define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET)
335#define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET)
336#define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET)
337#define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET)
338#define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET)
339#define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET)
340#define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET)
341#define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET)
342#define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET)
343
344#else /* CONFIG_40x + CONFIG_8xx */
345/*
346 * this is the # irq's for all ppc arch's (pmac/chrp/prep)
347 * so it is the max of them all
348 */
349#define NR_IRQS 256
350#define __DO_IRQ_CANON 1
351
352#ifndef CONFIG_8260
353
354#define NUM_8259_INTERRUPTS 16
355
356#else /* CONFIG_8260 */
357
358/* The 8260 has an internal interrupt controller with a maximum of
359 * 64 IRQs. We will use NR_IRQs from above since it is large enough.
360 * Don't be confused by the 8260 documentation where they list an
361 * "interrupt number" and "interrupt vector". We are only interested
362 * in the interrupt vector. There are "reserved" holes where the
363 * vector number increases, but the interrupt number in the table does not.
364 * (Document errata updates have fixed this...make sure you have up to
365 * date processor documentation -- Dan).
366 */
367
368#ifndef CPM_IRQ_OFFSET
369#define CPM_IRQ_OFFSET 0
370#endif
371
372#define NR_CPM_INTS 64
373
374#define SIU_INT_ERROR ((uint)0x00 + CPM_IRQ_OFFSET)
375#define SIU_INT_I2C ((uint)0x01 + CPM_IRQ_OFFSET)
376#define SIU_INT_SPI ((uint)0x02 + CPM_IRQ_OFFSET)
377#define SIU_INT_RISC ((uint)0x03 + CPM_IRQ_OFFSET)
378#define SIU_INT_SMC1 ((uint)0x04 + CPM_IRQ_OFFSET)
379#define SIU_INT_SMC2 ((uint)0x05 + CPM_IRQ_OFFSET)
380#define SIU_INT_IDMA1 ((uint)0x06 + CPM_IRQ_OFFSET)
381#define SIU_INT_IDMA2 ((uint)0x07 + CPM_IRQ_OFFSET)
382#define SIU_INT_IDMA3 ((uint)0x08 + CPM_IRQ_OFFSET)
383#define SIU_INT_IDMA4 ((uint)0x09 + CPM_IRQ_OFFSET)
384#define SIU_INT_SDMA ((uint)0x0a + CPM_IRQ_OFFSET)
385#define SIU_INT_USB ((uint)0x0b + CPM_IRQ_OFFSET)
386#define SIU_INT_TIMER1 ((uint)0x0c + CPM_IRQ_OFFSET)
387#define SIU_INT_TIMER2 ((uint)0x0d + CPM_IRQ_OFFSET)
388#define SIU_INT_TIMER3 ((uint)0x0e + CPM_IRQ_OFFSET)
389#define SIU_INT_TIMER4 ((uint)0x0f + CPM_IRQ_OFFSET)
390#define SIU_INT_TMCNT ((uint)0x10 + CPM_IRQ_OFFSET)
391#define SIU_INT_PIT ((uint)0x11 + CPM_IRQ_OFFSET)
392#define SIU_INT_IRQ1 ((uint)0x13 + CPM_IRQ_OFFSET)
393#define SIU_INT_IRQ2 ((uint)0x14 + CPM_IRQ_OFFSET)
394#define SIU_INT_IRQ3 ((uint)0x15 + CPM_IRQ_OFFSET)
395#define SIU_INT_IRQ4 ((uint)0x16 + CPM_IRQ_OFFSET)
396#define SIU_INT_IRQ5 ((uint)0x17 + CPM_IRQ_OFFSET)
397#define SIU_INT_IRQ6 ((uint)0x18 + CPM_IRQ_OFFSET)
398#define SIU_INT_IRQ7 ((uint)0x19 + CPM_IRQ_OFFSET)
399#define SIU_INT_FCC1 ((uint)0x20 + CPM_IRQ_OFFSET)
400#define SIU_INT_FCC2 ((uint)0x21 + CPM_IRQ_OFFSET)
401#define SIU_INT_FCC3 ((uint)0x22 + CPM_IRQ_OFFSET)
402#define SIU_INT_MCC1 ((uint)0x24 + CPM_IRQ_OFFSET)
403#define SIU_INT_MCC2 ((uint)0x25 + CPM_IRQ_OFFSET)
404#define SIU_INT_SCC1 ((uint)0x28 + CPM_IRQ_OFFSET)
405#define SIU_INT_SCC2 ((uint)0x29 + CPM_IRQ_OFFSET)
406#define SIU_INT_SCC3 ((uint)0x2a + CPM_IRQ_OFFSET)
407#define SIU_INT_SCC4 ((uint)0x2b + CPM_IRQ_OFFSET)
408#define SIU_INT_PC15 ((uint)0x30 + CPM_IRQ_OFFSET)
409#define SIU_INT_PC14 ((uint)0x31 + CPM_IRQ_OFFSET)
410#define SIU_INT_PC13 ((uint)0x32 + CPM_IRQ_OFFSET)
411#define SIU_INT_PC12 ((uint)0x33 + CPM_IRQ_OFFSET)
412#define SIU_INT_PC11 ((uint)0x34 + CPM_IRQ_OFFSET)
413#define SIU_INT_PC10 ((uint)0x35 + CPM_IRQ_OFFSET)
414#define SIU_INT_PC9 ((uint)0x36 + CPM_IRQ_OFFSET)
415#define SIU_INT_PC8 ((uint)0x37 + CPM_IRQ_OFFSET)
416#define SIU_INT_PC7 ((uint)0x38 + CPM_IRQ_OFFSET)
417#define SIU_INT_PC6 ((uint)0x39 + CPM_IRQ_OFFSET)
418#define SIU_INT_PC5 ((uint)0x3a + CPM_IRQ_OFFSET)
419#define SIU_INT_PC4 ((uint)0x3b + CPM_IRQ_OFFSET)
420#define SIU_INT_PC3 ((uint)0x3c + CPM_IRQ_OFFSET)
421#define SIU_INT_PC2 ((uint)0x3d + CPM_IRQ_OFFSET)
422#define SIU_INT_PC1 ((uint)0x3e + CPM_IRQ_OFFSET)
423#define SIU_INT_PC0 ((uint)0x3f + CPM_IRQ_OFFSET)
424
425#endif /* CONFIG_8260 */
426
427#endif
428
429#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
430/* pedantic: these are long because they are used with set_bit --RR */
431extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
432extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
433extern atomic_t ppc_n_lost_interrupts;
434
435#endif
436
437/*
438 * Because many systems have two overlapping names spaces for
439 * interrupts (ISA and XICS for example), and the ISA interrupts
440 * have historically not been easy to renumber, we allow ISA
441 * interrupts to take values 0 - 15, and shift up the remaining
442 * interrupts by 0x10.
443 */
444#define NUM_ISA_INTERRUPTS 0x10
445extern int __irq_offset_value;
446
447static inline int irq_offset_up(int irq)
448{
449 return(irq + __irq_offset_value);
450}
451
452static inline int irq_offset_down(int irq)
453{
454 return(irq - __irq_offset_value);
455}
456
457static inline int irq_offset_value(void)
458{
459 return __irq_offset_value;
460}
461
462#ifdef __DO_IRQ_CANON
463extern int ppc_do_canonicalize_irqs;
464#else
465#define ppc_do_canonicalize_irqs 0
466#endif
467
468static __inline__ int irq_canonicalize(int irq)
469{
470 if (ppc_do_canonicalize_irqs && irq == 2)
471 irq = 9;
472 return irq;
473}
474
475extern int distribute_irqs;
476
477struct irqaction;
478struct pt_regs;
479
480#ifdef CONFIG_IRQSTACKS
481/*
482 * Per-cpu stacks for handling hard and soft interrupts.
483 */
484extern struct thread_info *hardirq_ctx[NR_CPUS];
485extern struct thread_info *softirq_ctx[NR_CPUS];
486
487extern void irq_ctx_init(void);
488extern void call_do_softirq(struct thread_info *tp);
489extern int call_handle_IRQ_event(int irq, struct pt_regs *regs,
490 struct irqaction *action, struct thread_info *tp);
491
492#define __ARCH_HAS_DO_SOFTIRQ
493
494#else
495#define irq_ctx_init()
496
497#endif /* CONFIG_IRQSTACKS */
498
499extern void do_IRQ(struct pt_regs *regs);
500
501#endif /* _ASM_IRQ_H */
502#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/kdebug.h b/include/asm-powerpc/kdebug.h
new file mode 100644
index 000000000000..9dcbac674811
--- /dev/null
+++ b/include/asm-powerpc/kdebug.h
@@ -0,0 +1,42 @@
1#ifndef _ASM_POWERPC_KDEBUG_H
2#define _ASM_POWERPC_KDEBUG_H
3
4/* nearly identical to x86_64/i386 code */
5
6#include <linux/notifier.h>
7
8struct pt_regs;
9
10struct die_args {
11 struct pt_regs *regs;
12 const char *str;
13 long err;
14 int trapnr;
15 int signr;
16};
17
18/*
19 Note - you should never unregister because that can race with NMIs.
20 If you really want to do it first unregister - then synchronize_sched -
21 then free.
22 */
23int register_die_notifier(struct notifier_block *nb);
24extern struct notifier_block *powerpc_die_chain;
25
26/* Grossly misnamed. */
27enum die_val {
28 DIE_OOPS = 1,
29 DIE_IABR_MATCH,
30 DIE_DABR_MATCH,
31 DIE_BPT,
32 DIE_SSTEP,
33 DIE_PAGE_FAULT,
34};
35
36static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,long err,int trap, int sig)
37{
38 struct die_args args = { .regs=regs, .str=str, .err=err, .trapnr=trap,.signr=sig };
39 return notifier_call_chain(&powerpc_die_chain, val, &args);
40}
41
42#endif /* _ASM_POWERPC_KDEBUG_H */
diff --git a/include/asm-powerpc/keylargo.h b/include/asm-powerpc/keylargo.h
new file mode 100644
index 000000000000..a669a3f0f5a2
--- /dev/null
+++ b/include/asm-powerpc/keylargo.h
@@ -0,0 +1,248 @@
1/*
2 * keylargo.h: definitions for using the "KeyLargo" I/O controller chip.
3 *
4 */
5
6/* "Pangea" chipset has keylargo device-id 0x25 while core99
7 * has device-id 0x22. The rev. of the pangea one is 0, so we
8 * fake an artificial rev. in keylargo_rev by oring 0x100
9 */
10#define KL_PANGEA_REV 0x100
11
12/* offset from base for feature control registers */
13#define KEYLARGO_MBCR 0x34 /* KL Only, Media bay control/status */
14#define KEYLARGO_FCR0 0x38
15#define KEYLARGO_FCR1 0x3c
16#define KEYLARGO_FCR2 0x40
17#define KEYLARGO_FCR3 0x44
18#define KEYLARGO_FCR4 0x48
19#define KEYLARGO_FCR5 0x4c /* Pangea only */
20
21/* K2 aditional FCRs */
22#define K2_FCR6 0x34
23#define K2_FCR7 0x30
24#define K2_FCR8 0x2c
25#define K2_FCR9 0x28
26#define K2_FCR10 0x24
27
28/* GPIO registers */
29#define KEYLARGO_GPIO_LEVELS0 0x50
30#define KEYLARGO_GPIO_LEVELS1 0x54
31#define KEYLARGO_GPIO_EXTINT_0 0x58
32#define KEYLARGO_GPIO_EXTINT_CNT 18
33#define KEYLARGO_GPIO_0 0x6A
34#define KEYLARGO_GPIO_CNT 17
35#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80
36#define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04
37#define KEYLARGO_GPIO_OUTOUT_DATA 0x01
38#define KEYLARGO_GPIO_INPUT_DATA 0x02
39
40/* K2 does only extint GPIOs and does 51 of them */
41#define K2_GPIO_EXTINT_0 0x58
42#define K2_GPIO_EXTINT_CNT 51
43
44/* Specific GPIO regs */
45
46#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03)
47#define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */
48
49#define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05)
50
51/* Hrm... this one is only to be used on Pismo. It seeem to also
52 * control the timebase enable on other machines. Still to be
53 * experimented... --BenH.
54 */
55#define KL_GPIO_FW_CABLE_POWER (KEYLARGO_GPIO_0+0x09)
56#define KL_GPIO_TB_ENABLE (KEYLARGO_GPIO_0+0x09)
57
58#define KL_GPIO_ETH_PHY_RESET (KEYLARGO_GPIO_0+0x10)
59
60#define KL_GPIO_EXTINT_CPU1 (KEYLARGO_GPIO_0+0x0a)
61#define KL_GPIO_EXTINT_CPU1_ASSERT 0x04
62#define KL_GPIO_EXTINT_CPU1_RELEASE 0x38
63
64#define KL_GPIO_RESET_CPU0 (KEYLARGO_GPIO_EXTINT_0+0x03)
65#define KL_GPIO_RESET_CPU1 (KEYLARGO_GPIO_EXTINT_0+0x04)
66#define KL_GPIO_RESET_CPU2 (KEYLARGO_GPIO_EXTINT_0+0x0f)
67#define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10)
68
69#define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09)
70#define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA
71
72#define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e)
73
74#define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a)
75#define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d)
76#define KL_GPIO_AIRPORT_2 (KEYLARGO_GPIO_0+0x0d)
77#define KL_GPIO_AIRPORT_3 (KEYLARGO_GPIO_0+0x0e)
78#define KL_GPIO_AIRPORT_4 (KEYLARGO_GPIO_0+0x0f)
79
80/*
81 * Bits in feature control register. Those bits different for K2 are
82 * listed separately
83 */
84#define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */
85#define KL_MBCR_MB0_IDE_ENABLE 0x00001000
86#define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */
87#define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */
88#define KL_MBCR_MB0_DEV_MASK 0x00007800
89#define KL_MBCR_MB0_DEV_POWER 0x00000400
90#define KL_MBCR_MB0_DEV_RESET 0x00000200
91#define KL_MBCR_MB0_ENABLE 0x00000100
92#define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */
93#define KL_MBCR_MB1_IDE_ENABLE 0x10000000
94#define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */
95#define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */
96#define KL_MBCR_MB1_DEV_MASK 0x78000000
97#define KL_MBCR_MB1_DEV_POWER 0x04000000
98#define KL_MBCR_MB1_DEV_RESET 0x02000000
99#define KL_MBCR_MB1_ENABLE 0x01000000
100
101#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* (KL Only) */
102#define KL0_SCC_A_INTF_ENABLE 0x00000002
103#define KL0_SCC_SLOWPCLK 0x00000004
104#define KL0_SCC_RESET 0x00000008
105#define KL0_SCCA_ENABLE 0x00000010
106#define KL0_SCCB_ENABLE 0x00000020
107#define KL0_SCC_CELL_ENABLE 0x00000040
108#define KL0_IRDA_HIGH_BAND 0x00000100 /* (KL Only) */
109#define KL0_IRDA_SOURCE2_SEL 0x00000200 /* (KL Only) */
110#define KL0_IRDA_SOURCE1_SEL 0x00000400 /* (KL Only) */
111#define KL0_PG_USB0_PMI_ENABLE 0x00000400 /* (Pangea/Intrepid Only) */
112#define KL0_IRDA_RESET 0x00000800 /* (KL Only) */
113#define KL0_PG_USB0_REF_SUSPEND_SEL 0x00000800 /* (Pangea/Intrepid Only) */
114#define KL0_IRDA_DEFAULT1 0x00001000 /* (KL Only) */
115#define KL0_PG_USB0_REF_SUSPEND 0x00001000 /* (Pangea/Intrepid Only) */
116#define KL0_IRDA_DEFAULT0 0x00002000 /* (KL Only) */
117#define KL0_PG_USB0_PAD_SUSPEND 0x00002000 /* (Pangea/Intrepid Only) */
118#define KL0_IRDA_FAST_CONNECT 0x00004000 /* (KL Only) */
119#define KL0_PG_USB1_PMI_ENABLE 0x00004000 /* (Pangea/Intrepid Only) */
120#define KL0_IRDA_ENABLE 0x00008000 /* (KL Only) */
121#define KL0_PG_USB1_REF_SUSPEND_SEL 0x00008000 /* (Pangea/Intrepid Only) */
122#define KL0_IRDA_CLK32_ENABLE 0x00010000 /* (KL Only) */
123#define KL0_PG_USB1_REF_SUSPEND 0x00010000 /* (Pangea/Intrepid Only) */
124#define KL0_IRDA_CLK19_ENABLE 0x00020000 /* (KL Only) */
125#define KL0_PG_USB1_PAD_SUSPEND 0x00020000 /* (Pangea/Intrepid Only) */
126#define KL0_USB0_PAD_SUSPEND0 0x00040000
127#define KL0_USB0_PAD_SUSPEND1 0x00080000
128#define KL0_USB0_CELL_ENABLE 0x00100000
129#define KL0_USB1_PAD_SUSPEND0 0x00400000
130#define KL0_USB1_PAD_SUSPEND1 0x00800000
131#define KL0_USB1_CELL_ENABLE 0x01000000
132#define KL0_USB_REF_SUSPEND 0x10000000 /* (KL Only) */
133
134#define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \
135 KL0_SCC_SLOWPCLK | \
136 KL0_SCC_CELL_ENABLE | KL0_SCCA_ENABLE)
137
138#define KL1_USB2_PMI_ENABLE 0x00000001 /* Intrepid only */
139#define KL1_AUDIO_SEL_22MCLK 0x00000002 /* KL/Pangea only */
140#define KL1_USB2_REF_SUSPEND_SEL 0x00000002 /* Intrepid only */
141#define KL1_USB2_REF_SUSPEND 0x00000004 /* Intrepid only */
142#define KL1_AUDIO_CLK_ENABLE_BIT 0x00000008 /* KL/Pangea only */
143#define KL1_USB2_PAD_SUSPEND_SEL 0x00000008 /* Intrepid only */
144#define KL1_USB2_PAD_SUSPEND0 0x00000010 /* Intrepid only */
145#define KL1_AUDIO_CLK_OUT_ENABLE 0x00000020 /* KL/Pangea only */
146#define KL1_USB2_PAD_SUSPEND1 0x00000020 /* Intrepid only */
147#define KL1_AUDIO_CELL_ENABLE 0x00000040 /* KL/Pangea only */
148#define KL1_USB2_CELL_ENABLE 0x00000040 /* Intrepid only */
149#define KL1_AUDIO_CHOOSE 0x00000080 /* KL/Pangea only */
150#define KL1_I2S0_CHOOSE 0x00000200 /* KL Only */
151#define KL1_I2S0_CELL_ENABLE 0x00000400
152#define KL1_I2S0_CLK_ENABLE_BIT 0x00001000
153#define KL1_I2S0_ENABLE 0x00002000
154#define KL1_I2S1_CELL_ENABLE 0x00020000
155#define KL1_I2S1_CLK_ENABLE_BIT 0x00080000
156#define KL1_I2S1_ENABLE 0x00100000
157#define KL1_EIDE0_ENABLE 0x00800000 /* KL/Intrepid Only */
158#define KL1_EIDE0_RESET_N 0x01000000 /* KL/Intrepid Only */
159#define KL1_EIDE1_ENABLE 0x04000000 /* KL Only */
160#define KL1_EIDE1_RESET_N 0x08000000 /* KL Only */
161#define KL1_UIDE_ENABLE 0x20000000 /* KL/Pangea Only */
162#define KL1_UIDE_RESET_N 0x40000000 /* KL/Pangea Only */
163
164#define KL2_IOBUS_ENABLE 0x00000002
165#define KL2_SLEEP_STATE_BIT 0x00000100 /* KL Only */
166#define KL2_PG_STOP_ALL_CLOCKS 0x00000100 /* Pangea Only */
167#define KL2_MPIC_ENABLE 0x00020000
168#define KL2_CARDSLOT_RESET 0x00040000 /* Pangea/Intrepid Only */
169#define KL2_ALT_DATA_OUT 0x02000000 /* KL Only ??? */
170#define KL2_MEM_IS_BIG 0x04000000
171#define KL2_CARDSEL_16 0x08000000
172
173#define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 /* KL/Pangea only */
174#define KL3_SHUTDOWN_PLLKW6 0x00000002 /* KL/Pangea only */
175#define KL3_IT_SHUTDOWN_PLL3 0x00000002 /* Intrepid only */
176#define KL3_SHUTDOWN_PLLKW4 0x00000004 /* KL/Pangea only */
177#define KL3_IT_SHUTDOWN_PLL2 0x00000004 /* Intrepid only */
178#define KL3_SHUTDOWN_PLLKW35 0x00000008 /* KL/Pangea only */
179#define KL3_IT_SHUTDOWN_PLL1 0x00000008 /* Intrepid only */
180#define KL3_SHUTDOWN_PLLKW12 0x00000010 /* KL Only */
181#define KL3_IT_ENABLE_PLL3_SHUTDOWN 0x00000010 /* Intrepid only */
182#define KL3_PLL_RESET 0x00000020 /* KL/Pangea only */
183#define KL3_IT_ENABLE_PLL2_SHUTDOWN 0x00000020 /* Intrepid only */
184#define KL3_IT_ENABLE_PLL1_SHUTDOWN 0x00000010 /* Intrepid only */
185#define KL3_SHUTDOWN_PLL2X 0x00000080 /* KL Only */
186#define KL3_CLK66_ENABLE 0x00000100 /* KL Only */
187#define KL3_CLK49_ENABLE 0x00000200
188#define KL3_CLK45_ENABLE 0x00000400
189#define KL3_CLK31_ENABLE 0x00000800 /* KL/Pangea only */
190#define KL3_TIMER_CLK18_ENABLE 0x00001000
191#define KL3_I2S1_CLK18_ENABLE 0x00002000
192#define KL3_I2S0_CLK18_ENABLE 0x00004000
193#define KL3_VIA_CLK16_ENABLE 0x00008000 /* KL/Pangea only */
194#define KL3_IT_VIA_CLK32_ENABLE 0x00008000 /* Intrepid only */
195#define KL3_STOPPING33_ENABLED 0x00080000 /* KL Only */
196#define KL3_PG_PLL_ENABLE_TEST 0x00080000 /* Pangea Only */
197
198/* Intrepid USB bus 2, port 0,1 */
199#define KL3_IT_PORT_WAKEUP_ENABLE(p) (0x00080000 << ((p)<<3))
200#define KL3_IT_PORT_RESUME_WAKE_EN(p) (0x00040000 << ((p)<<3))
201#define KL3_IT_PORT_CONNECT_WAKE_EN(p) (0x00020000 << ((p)<<3))
202#define KL3_IT_PORT_DISCONNECT_WAKE_EN(p) (0x00010000 << ((p)<<3))
203#define KL3_IT_PORT_RESUME_STAT(p) (0x00300000 << ((p)<<3))
204#define KL3_IT_PORT_CONNECT_STAT(p) (0x00200000 << ((p)<<3))
205#define KL3_IT_PORT_DISCONNECT_STAT(p) (0x00100000 << ((p)<<3))
206
207/* Port 0,1 : bus 0, port 2,3 : bus 1 */
208#define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3))
209#define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3))
210#define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3))
211#define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3))
212#define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3))
213#define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3))
214#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3))
215
216/* Pangea and Intrepid only */
217#define KL5_VIA_USE_CLK31 0000000001 /* Pangea Only */
218#define KL5_SCC_USE_CLK31 0x00000002 /* Pangea Only */
219#define KL5_PWM_CLK32_EN 0x00000004
220#define KL5_CLK3_68_EN 0x00000010
221#define KL5_CLK32_EN 0x00000020
222
223
224/* K2 definitions */
225#define K2_FCR0_USB0_SWRESET 0x00200000
226#define K2_FCR0_USB1_SWRESET 0x02000000
227#define K2_FCR0_RING_PME_DISABLE 0x08000000
228
229#define K2_FCR1_PCI1_BUS_RESET_N 0x00000010
230#define K2_FCR1_PCI1_SLEEP_RESET_EN 0x00000020
231#define K2_FCR1_I2S0_CELL_ENABLE 0x00000400
232#define K2_FCR1_I2S0_RESET 0x00000800
233#define K2_FCR1_I2S0_CLK_ENABLE_BIT 0x00001000
234#define K2_FCR1_I2S0_ENABLE 0x00002000
235
236#define K2_FCR1_PCI1_CLK_ENABLE 0x00004000
237#define K2_FCR1_FW_CLK_ENABLE 0x00008000
238#define K2_FCR1_FW_RESET_N 0x00010000
239#define K2_FCR1_GMAC_CLK_ENABLE 0x00400000
240#define K2_FCR1_GMAC_POWER_DOWN 0x00800000
241#define K2_FCR1_GMAC_RESET_N 0x01000000
242#define K2_FCR1_SATA_CLK_ENABLE 0x02000000
243#define K2_FCR1_SATA_POWER_DOWN 0x04000000
244#define K2_FCR1_SATA_RESET_N 0x08000000
245#define K2_FCR1_UATA_CLK_ENABLE 0x10000000
246#define K2_FCR1_UATA_RESET_N 0x40000000
247#define K2_FCR1_UATA_CHOOSE_CLK66 0x80000000
248
diff --git a/include/asm-powerpc/kmap_types.h b/include/asm-powerpc/kmap_types.h
new file mode 100644
index 000000000000..b6bac6f61c16
--- /dev/null
+++ b/include/asm-powerpc/kmap_types.h
@@ -0,0 +1,33 @@
1#ifndef _ASM_POWERPC_KMAP_TYPES_H
2#define _ASM_POWERPC_KMAP_TYPES_H
3
4#ifdef __KERNEL__
5
6/*
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13enum km_type {
14 KM_BOUNCE_READ,
15 KM_SKB_SUNRPC_DATA,
16 KM_SKB_DATA_SOFTIRQ,
17 KM_USER0,
18 KM_USER1,
19 KM_BIO_SRC_IRQ,
20 KM_BIO_DST_IRQ,
21 KM_PTE0,
22 KM_PTE1,
23 KM_IRQ0,
24 KM_IRQ1,
25 KM_SOFTIRQ0,
26 KM_SOFTIRQ1,
27 KM_PPC_SYNC_PAGE,
28 KM_PPC_SYNC_ICACHE,
29 KM_TYPE_NR
30};
31
32#endif /* __KERNEL__ */
33#endif /* _ASM_POWERPC_KMAP_TYPES_H */
diff --git a/include/asm-powerpc/kprobes.h b/include/asm-powerpc/kprobes.h
new file mode 100644
index 000000000000..b2f09f17fbe0
--- /dev/null
+++ b/include/asm-powerpc/kprobes.h
@@ -0,0 +1,66 @@
1#ifndef _ASM_POWERPC_KPROBES_H
2#define _ASM_POWERPC_KPROBES_H
3/*
4 * Kernel Probes (KProbes)
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 *
20 * Copyright (C) IBM Corporation, 2002, 2004
21 *
22 * 2002-Oct Created by Vamsi Krishna S <vamsi_krishna@in.ibm.com> Kernel
23 * Probes initial implementation ( includes suggestions from
24 * Rusty Russell).
25 * 2004-Nov Modified for PPC64 by Ananth N Mavinakayanahalli
26 * <ananth@in.ibm.com>
27 */
28#include <linux/types.h>
29#include <linux/ptrace.h>
30
31struct pt_regs;
32
33typedef unsigned int kprobe_opcode_t;
34#define BREAKPOINT_INSTRUCTION 0x7fe00008 /* trap */
35#define MAX_INSN_SIZE 1
36
37#define IS_TW(instr) (((instr) & 0xfc0007fe) == 0x7c000008)
38#define IS_TD(instr) (((instr) & 0xfc0007fe) == 0x7c000088)
39#define IS_TDI(instr) (((instr) & 0xfc000000) == 0x08000000)
40#define IS_TWI(instr) (((instr) & 0xfc000000) == 0x0c000000)
41
42#define JPROBE_ENTRY(pentry) (kprobe_opcode_t *)((func_descr_t *)pentry)
43
44#define is_trap(instr) (IS_TW(instr) || IS_TD(instr) || \
45 IS_TWI(instr) || IS_TDI(instr))
46
47#define ARCH_SUPPORTS_KRETPROBES
48void kretprobe_trampoline(void);
49
50/* Architecture specific copy of original instruction */
51struct arch_specific_insn {
52 /* copy of original instruction */
53 kprobe_opcode_t *insn;
54};
55
56#ifdef CONFIG_KPROBES
57extern int kprobe_exceptions_notify(struct notifier_block *self,
58 unsigned long val, void *data);
59#else /* !CONFIG_KPROBES */
60static inline int kprobe_exceptions_notify(struct notifier_block *self,
61 unsigned long val, void *data)
62{
63 return 0;
64}
65#endif
66#endif /* _ASM_POWERPC_KPROBES_H */
diff --git a/include/asm-powerpc/lmb.h b/include/asm-powerpc/lmb.h
new file mode 100644
index 000000000000..ea0afe343545
--- /dev/null
+++ b/include/asm-powerpc/lmb.h
@@ -0,0 +1,81 @@
1#ifndef _PPC64_LMB_H
2#define _PPC64_LMB_H
3
4/*
5 * Definitions for talking to the Open Firmware PROM on
6 * Power Macintosh computers.
7 *
8 * Copyright (C) 2001 Peter Bergner, IBM Corp.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15
16#include <linux/init.h>
17#include <asm/prom.h>
18
19#define MAX_LMB_REGIONS 128
20
21#define LMB_ALLOC_ANYWHERE 0
22
23struct lmb_property {
24 unsigned long base;
25 unsigned long size;
26};
27
28struct lmb_region {
29 unsigned long cnt;
30 unsigned long size;
31 struct lmb_property region[MAX_LMB_REGIONS+1];
32};
33
34struct lmb {
35 unsigned long debug;
36 unsigned long rmo_size;
37 struct lmb_region memory;
38 struct lmb_region reserved;
39};
40
41extern struct lmb lmb;
42
43extern void __init lmb_init(void);
44extern void __init lmb_analyze(void);
45extern long __init lmb_add(unsigned long, unsigned long);
46extern long __init lmb_reserve(unsigned long, unsigned long);
47extern unsigned long __init lmb_alloc(unsigned long, unsigned long);
48extern unsigned long __init lmb_alloc_base(unsigned long, unsigned long,
49 unsigned long);
50extern unsigned long __init lmb_phys_mem_size(void);
51extern unsigned long __init lmb_end_of_DRAM(void);
52extern unsigned long __init lmb_abs_to_phys(unsigned long);
53extern void __init lmb_enforce_memory_limit(unsigned long);
54
55extern void lmb_dump_all(void);
56
57extern unsigned long io_hole_start;
58
59static inline unsigned long
60lmb_size_bytes(struct lmb_region *type, unsigned long region_nr)
61{
62 return type->region[region_nr].size;
63}
64static inline unsigned long
65lmb_size_pages(struct lmb_region *type, unsigned long region_nr)
66{
67 return lmb_size_bytes(type, region_nr) >> PAGE_SHIFT;
68}
69static inline unsigned long
70lmb_start_pfn(struct lmb_region *type, unsigned long region_nr)
71{
72 return type->region[region_nr].base >> PAGE_SHIFT;
73}
74static inline unsigned long
75lmb_end_pfn(struct lmb_region *type, unsigned long region_nr)
76{
77 return lmb_start_pfn(type, region_nr) +
78 lmb_size_pages(type, region_nr);
79}
80
81#endif /* _PPC64_LMB_H */
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
new file mode 100644
index 000000000000..b3a93b476d97
--- /dev/null
+++ b/include/asm-powerpc/machdep.h
@@ -0,0 +1,284 @@
1#ifndef _PPC64_MACHDEP_H
2#define _PPC64_MACHDEP_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/config.h>
13#include <linux/seq_file.h>
14#include <linux/init.h>
15#include <linux/dma-mapping.h>
16
17#include <asm/setup.h>
18
19/* We export this macro for external modules like Alsa to know if
20 * ppc_md.feature_call is implemented or not
21 */
22#define CONFIG_PPC_HAS_FEATURE_CALLS
23
24struct pt_regs;
25struct pci_bus;
26struct device_node;
27struct iommu_table;
28struct rtc_time;
29struct file;
30
31#ifdef CONFIG_SMP
32struct smp_ops_t {
33 void (*message_pass)(int target, int msg);
34 int (*probe)(void);
35 void (*kick_cpu)(int nr);
36 void (*setup_cpu)(int nr);
37 void (*take_timebase)(void);
38 void (*give_timebase)(void);
39 int (*cpu_enable)(unsigned int nr);
40 int (*cpu_disable)(void);
41 void (*cpu_die)(unsigned int nr);
42 int (*cpu_bootable)(unsigned int nr);
43};
44#endif
45
46struct machdep_calls {
47#ifdef CONFIG_PPC64
48 void (*hpte_invalidate)(unsigned long slot,
49 unsigned long va,
50 int large,
51 int local);
52 long (*hpte_updatepp)(unsigned long slot,
53 unsigned long newpp,
54 unsigned long va,
55 int large,
56 int local);
57 void (*hpte_updateboltedpp)(unsigned long newpp,
58 unsigned long ea);
59 long (*hpte_insert)(unsigned long hpte_group,
60 unsigned long va,
61 unsigned long prpn,
62 unsigned long vflags,
63 unsigned long rflags);
64 long (*hpte_remove)(unsigned long hpte_group);
65 void (*flush_hash_range)(unsigned long number, int local);
66
67 /* special for kexec, to be called in real mode, linar mapping is
68 * destroyed as well */
69 void (*hpte_clear_all)(void);
70
71 void (*tce_build)(struct iommu_table * tbl,
72 long index,
73 long npages,
74 unsigned long uaddr,
75 enum dma_data_direction direction);
76 void (*tce_free)(struct iommu_table *tbl,
77 long index,
78 long npages);
79 void (*tce_flush)(struct iommu_table *tbl);
80 void (*iommu_dev_setup)(struct pci_dev *dev);
81 void (*iommu_bus_setup)(struct pci_bus *bus);
82 void (*irq_bus_setup)(struct pci_bus *bus);
83#endif
84
85 int (*probe)(int platform);
86 void (*setup_arch)(void);
87 void (*init_early)(void);
88 /* Optional, may be NULL. */
89 void (*show_cpuinfo)(struct seq_file *m);
90 void (*show_percpuinfo)(struct seq_file *m, int i);
91
92 void (*init_IRQ)(void);
93 int (*get_irq)(struct pt_regs *);
94 void (*cpu_irq_down)(int secondary);
95
96 /* PCI stuff */
97 /* Called after scanning the bus, before allocating resources */
98 void (*pcibios_fixup)(void);
99 int (*pci_probe_mode)(struct pci_bus *);
100
101 void (*restart)(char *cmd);
102 void (*power_off)(void);
103 void (*halt)(void);
104 void (*panic)(char *str);
105 void (*cpu_die)(void);
106
107 long (*time_init)(void); /* Optional, may be NULL */
108
109 int (*set_rtc_time)(struct rtc_time *);
110 void (*get_rtc_time)(struct rtc_time *);
111 unsigned long (*get_boot_time)(void);
112 unsigned char (*rtc_read_val)(int addr);
113 void (*rtc_write_val)(int addr, unsigned char val);
114
115 void (*calibrate_decr)(void);
116
117 void (*progress)(char *, unsigned short);
118
119 /* Interface for platform error logging */
120 void (*log_error)(char *buf, unsigned int err_type, int fatal);
121
122 unsigned char (*nvram_read_val)(int addr);
123 void (*nvram_write_val)(int addr, unsigned char val);
124 ssize_t (*nvram_write)(char *buf, size_t count, loff_t *index);
125 ssize_t (*nvram_read)(char *buf, size_t count, loff_t *index);
126 ssize_t (*nvram_size)(void);
127 void (*nvram_sync)(void);
128
129 /* Exception handlers */
130 void (*system_reset_exception)(struct pt_regs *regs);
131 int (*machine_check_exception)(struct pt_regs *regs);
132
133 /* Motherboard/chipset features. This is a kind of general purpose
134 * hook used to control some machine specific features (like reset
135 * lines, chip power control, etc...).
136 */
137 long (*feature_call)(unsigned int feature, ...);
138
139 /* Check availability of legacy devices like i8042 */
140 int (*check_legacy_ioport)(unsigned int baseport);
141
142 /* Get legacy PCI/IDE interrupt mapping */
143 int (*pci_get_legacy_ide_irq)(struct pci_dev *dev, int channel);
144
145 /* Get access protection for /dev/mem */
146 pgprot_t (*phys_mem_access_prot)(struct file *file,
147 unsigned long offset,
148 unsigned long size,
149 pgprot_t vma_prot);
150
151 /* Idle loop for this platform, leave empty for default idle loop */
152 void (*idle_loop)(void);
153
154 /* Function to enable performance monitor counters for this
155 platform, called once per cpu. */
156 void (*enable_pmcs)(void);
157
158#ifdef CONFIG_PPC32 /* XXX for now */
159 /* A general init function, called by ppc_init in init/main.c.
160 May be NULL. */
161 void (*init)(void);
162
163 void (*idle)(void);
164 void (*power_save)(void);
165
166 void (*heartbeat)(void);
167 unsigned long heartbeat_reset;
168 unsigned long heartbeat_count;
169
170 void (*setup_io_mappings)(void);
171
172 void (*early_serial_map)(void);
173 void (*kgdb_map_scc)(void);
174
175 /*
176 * optional PCI "hooks"
177 */
178
179 /* Called after PPC generic resource fixup to perform
180 machine specific fixups */
181 void (*pcibios_fixup_resources)(struct pci_dev *);
182
183 /* Called for each PCI bus in the system when it's probed */
184 void (*pcibios_fixup_bus)(struct pci_bus *);
185
186 /* Called when pci_enable_device() is called (initial=0) or
187 * when a device with no assigned resource is found (initial=1).
188 * Returns 0 to allow assignment/enabling of the device. */
189 int (*pcibios_enable_device_hook)(struct pci_dev *, int initial);
190
191 /* For interrupt routing */
192 unsigned char (*pci_swizzle)(struct pci_dev *, unsigned char *);
193 int (*pci_map_irq)(struct pci_dev *, unsigned char, unsigned char);
194
195 /* Called in indirect_* to avoid touching devices */
196 int (*pci_exclude_device)(unsigned char, unsigned char);
197
198 /* Called at then very end of pcibios_init() */
199 void (*pcibios_after_init)(void);
200
201 /* this is for modules, since _machine can be a define -- Cort */
202 int ppc_machine;
203
204#ifdef CONFIG_KEXEC
205 /* Called to shutdown machine specific hardware not already controlled
206 * by other drivers.
207 * XXX Should we move this one out of kexec scope?
208 */
209 void (*machine_shutdown)(void);
210
211 /* Called to do the minimal shutdown needed to run a kexec'd kernel
212 * to run successfully.
213 * XXX Should we move this one out of kexec scope?
214 */
215 void (*machine_crash_shutdown)(void);
216
217 /* Called to do what every setup is needed on image and the
218 * reboot code buffer. Returns 0 on success.
219 * Provide your own (maybe dummy) implementation if your platform
220 * claims to support kexec.
221 */
222 int (*machine_kexec_prepare)(struct kimage *image);
223
224 /* Called to handle any machine specific cleanup on image */
225 void (*machine_kexec_cleanup)(struct kimage *image);
226
227 /* Called to perform the _real_ kexec.
228 * Do NOT allocate memory or fail here. We are past the point of
229 * no return.
230 */
231 void (*machine_kexec)(struct kimage *image);
232#endif /* CONFIG_KEXEC */
233#endif /* CONFIG_PPC32 */
234};
235
236extern void default_idle(void);
237extern void native_idle(void);
238
239extern struct machdep_calls ppc_md;
240extern char cmd_line[COMMAND_LINE_SIZE];
241
242#ifdef CONFIG_PPC_PMAC
243/*
244 * Power macintoshes have either a CUDA, PMU or SMU controlling
245 * system reset, power, NVRAM, RTC.
246 */
247typedef enum sys_ctrler_kind {
248 SYS_CTRLER_UNKNOWN = 0,
249 SYS_CTRLER_CUDA = 1,
250 SYS_CTRLER_PMU = 2,
251 SYS_CTRLER_SMU = 3,
252} sys_ctrler_t;
253extern sys_ctrler_t sys_ctrler;
254
255#endif /* CONFIG_PPC_PMAC */
256
257extern void setup_pci_ptrs(void);
258
259#ifdef CONFIG_SMP
260/* Poor default implementations */
261extern void __devinit smp_generic_give_timebase(void);
262extern void __devinit smp_generic_take_timebase(void);
263#endif /* CONFIG_SMP */
264
265
266/* Functions to produce codes on the leds.
267 * The SRC code should be unique for the message category and should
268 * be limited to the lower 24 bits (the upper 8 are set by these funcs),
269 * and (for boot & dump) should be sorted numerically in the order
270 * the events occur.
271 */
272/* Print a boot progress message. */
273void ppc64_boot_msg(unsigned int src, const char *msg);
274/* Print a termination message (print only -- does not stop the kernel) */
275void ppc64_terminate_msg(unsigned int src, const char *msg);
276
277static inline void log_error(char *buf, unsigned int err_type, int fatal)
278{
279 if (ppc_md.log_error)
280 ppc_md.log_error(buf, err_type, fatal);
281}
282
283#endif /* __KERNEL__ */
284#endif /* _PPC64_MACHDEP_H */
diff --git a/include/asm-powerpc/macio.h b/include/asm-powerpc/macio.h
new file mode 100644
index 000000000000..b553dd4b139e
--- /dev/null
+++ b/include/asm-powerpc/macio.h
@@ -0,0 +1,140 @@
1#ifndef __MACIO_ASIC_H__
2#define __MACIO_ASIC_H__
3
4#include <asm/of_device.h>
5
6extern struct bus_type macio_bus_type;
7
8/* MacIO device driver is defined later */
9struct macio_driver;
10struct macio_chip;
11
12#define MACIO_DEV_COUNT_RESOURCES 8
13#define MACIO_DEV_COUNT_IRQS 8
14
15/*
16 * the macio_bus structure is used to describe a "virtual" bus
17 * within a MacIO ASIC. It's typically provided by a macio_pci_asic
18 * PCI device, but could be provided differently as well (nubus
19 * machines using a fake OF tree).
20 *
21 * The pdev field can be NULL on non-PCI machines
22 */
23struct macio_bus
24{
25 struct macio_chip *chip; /* macio_chip (private use) */
26 int index; /* macio chip index in system */
27#ifdef CONFIG_PCI
28 struct pci_dev *pdev; /* PCI device hosting this bus */
29#endif
30};
31
32/*
33 * the macio_dev structure is used to describe a device
34 * within an Apple MacIO ASIC.
35 */
36struct macio_dev
37{
38 struct macio_bus *bus; /* macio bus this device is on */
39 struct macio_dev *media_bay; /* Device is part of a media bay */
40 struct of_device ofdev;
41 int n_resources;
42 struct resource resource[MACIO_DEV_COUNT_RESOURCES];
43 int n_interrupts;
44 struct resource interrupt[MACIO_DEV_COUNT_IRQS];
45};
46#define to_macio_device(d) container_of(d, struct macio_dev, ofdev.dev)
47#define of_to_macio_device(d) container_of(d, struct macio_dev, ofdev)
48
49extern struct macio_dev *macio_dev_get(struct macio_dev *dev);
50extern void macio_dev_put(struct macio_dev *dev);
51
52/*
53 * Accessors to resources & interrupts and other device
54 * fields
55 */
56
57static inline int macio_resource_count(struct macio_dev *dev)
58{
59 return dev->n_resources;
60}
61
62static inline unsigned long macio_resource_start(struct macio_dev *dev, int resource_no)
63{
64 return dev->resource[resource_no].start;
65}
66
67static inline unsigned long macio_resource_end(struct macio_dev *dev, int resource_no)
68{
69 return dev->resource[resource_no].end;
70}
71
72static inline unsigned long macio_resource_len(struct macio_dev *dev, int resource_no)
73{
74 struct resource *res = &dev->resource[resource_no];
75 if (res->start == 0 || res->end == 0 || res->end < res->start)
76 return 0;
77 return res->end - res->start + 1;
78}
79
80extern int macio_request_resource(struct macio_dev *dev, int resource_no, const char *name);
81extern void macio_release_resource(struct macio_dev *dev, int resource_no);
82extern int macio_request_resources(struct macio_dev *dev, const char *name);
83extern void macio_release_resources(struct macio_dev *dev);
84
85static inline int macio_irq_count(struct macio_dev *dev)
86{
87 return dev->n_interrupts;
88}
89
90static inline int macio_irq(struct macio_dev *dev, int irq_no)
91{
92 return dev->interrupt[irq_no].start;
93}
94
95static inline void macio_set_drvdata(struct macio_dev *dev, void *data)
96{
97 dev_set_drvdata(&dev->ofdev.dev, data);
98}
99
100static inline void* macio_get_drvdata(struct macio_dev *dev)
101{
102 return dev_get_drvdata(&dev->ofdev.dev);
103}
104
105static inline struct device_node *macio_get_of_node(struct macio_dev *mdev)
106{
107 return mdev->ofdev.node;
108}
109
110#ifdef CONFIG_PCI
111static inline struct pci_dev *macio_get_pci_dev(struct macio_dev *mdev)
112{
113 return mdev->bus->pdev;
114}
115#endif
116
117/*
118 * A driver for a mac-io chip based device
119 */
120struct macio_driver
121{
122 char *name;
123 struct of_device_id *match_table;
124 struct module *owner;
125
126 int (*probe)(struct macio_dev* dev, const struct of_device_id *match);
127 int (*remove)(struct macio_dev* dev);
128
129 int (*suspend)(struct macio_dev* dev, pm_message_t state);
130 int (*resume)(struct macio_dev* dev);
131 int (*shutdown)(struct macio_dev* dev);
132
133 struct device_driver driver;
134};
135#define to_macio_driver(drv) container_of(drv,struct macio_driver, driver)
136
137extern int macio_register_driver(struct macio_driver *);
138extern void macio_unregister_driver(struct macio_driver *);
139
140#endif /* __MACIO_ASIC_H__ */
diff --git a/include/asm-powerpc/mediabay.h b/include/asm-powerpc/mediabay.h
new file mode 100644
index 000000000000..9daa3252d7b6
--- /dev/null
+++ b/include/asm-powerpc/mediabay.h
@@ -0,0 +1,31 @@
1/*
2 * mediabay.h: definitions for using the media bay
3 * on PowerBook 3400 and similar computers.
4 *
5 * Copyright (C) 1997 Paul Mackerras.
6 */
7#ifndef _PPC_MEDIABAY_H
8#define _PPC_MEDIABAY_H
9
10#ifdef __KERNEL__
11
12#define MB_FD 0 /* media bay contains floppy drive (automatic eject ?) */
13#define MB_FD1 1 /* media bay contains floppy drive (manual eject ?) */
14#define MB_SOUND 2 /* sound device ? */
15#define MB_CD 3 /* media bay contains ATA drive such as CD or ZIP */
16#define MB_PCI 5 /* media bay contains a PCI device */
17#define MB_POWER 6 /* media bay contains a Power device (???) */
18#define MB_NO 7 /* media bay contains nothing */
19
20int check_media_bay(struct device_node *which_bay, int what);
21int check_media_bay_by_base(unsigned long base, int what);
22
23/* Number of bays in the machine or 0 */
24extern int media_bay_count;
25
26/* called by pmac-ide.c to register IDE controller for media bay */
27extern int media_bay_set_ide_infos(struct device_node* which_bay,
28 unsigned long base, int irq, int index);
29
30#endif /* __KERNEL__ */
31#endif /* _PPC_MEDIABAY_H */
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
new file mode 100644
index 000000000000..7083d1f74260
--- /dev/null
+++ b/include/asm-powerpc/mpic.h
@@ -0,0 +1,287 @@
1#ifndef _ASM_POWERPC_MPIC_H
2#define _ASM_POWERPC_MPIC_H
3
4#include <linux/irq.h>
5
6/*
7 * Global registers
8 */
9
10#define MPIC_GREG_BASE 0x01000
11
12#define MPIC_GREG_FEATURE_0 0x00000
13#define MPIC_GREG_FEATURE_LAST_SRC_MASK 0x07ff0000
14#define MPIC_GREG_FEATURE_LAST_SRC_SHIFT 16
15#define MPIC_GREG_FEATURE_LAST_CPU_MASK 0x00001f00
16#define MPIC_GREG_FEATURE_LAST_CPU_SHIFT 8
17#define MPIC_GREG_FEATURE_VERSION_MASK 0xff
18#define MPIC_GREG_FEATURE_1 0x00010
19#define MPIC_GREG_GLOBAL_CONF_0 0x00020
20#define MPIC_GREG_GCONF_RESET 0x80000000
21#define MPIC_GREG_GCONF_8259_PTHROU_DIS 0x20000000
22#define MPIC_GREG_GCONF_BASE_MASK 0x000fffff
23#define MPIC_GREG_GLOBAL_CONF_1 0x00030
24#define MPIC_GREG_VENDOR_0 0x00040
25#define MPIC_GREG_VENDOR_1 0x00050
26#define MPIC_GREG_VENDOR_2 0x00060
27#define MPIC_GREG_VENDOR_3 0x00070
28#define MPIC_GREG_VENDOR_ID 0x00080
29#define MPIC_GREG_VENDOR_ID_STEPPING_MASK 0x00ff0000
30#define MPIC_GREG_VENDOR_ID_STEPPING_SHIFT 16
31#define MPIC_GREG_VENDOR_ID_DEVICE_ID_MASK 0x0000ff00
32#define MPIC_GREG_VENDOR_ID_DEVICE_ID_SHIFT 8
33#define MPIC_GREG_VENDOR_ID_VENDOR_ID_MASK 0x000000ff
34#define MPIC_GREG_PROCESSOR_INIT 0x00090
35#define MPIC_GREG_IPI_VECTOR_PRI_0 0x000a0
36#define MPIC_GREG_IPI_VECTOR_PRI_1 0x000b0
37#define MPIC_GREG_IPI_VECTOR_PRI_2 0x000c0
38#define MPIC_GREG_IPI_VECTOR_PRI_3 0x000d0
39#define MPIC_GREG_SPURIOUS 0x000e0
40#define MPIC_GREG_TIMER_FREQ 0x000f0
41
42/*
43 *
44 * Timer registers
45 */
46#define MPIC_TIMER_BASE 0x01100
47#define MPIC_TIMER_STRIDE 0x40
48
49#define MPIC_TIMER_CURRENT_CNT 0x00000
50#define MPIC_TIMER_BASE_CNT 0x00010
51#define MPIC_TIMER_VECTOR_PRI 0x00020
52#define MPIC_TIMER_DESTINATION 0x00030
53
54/*
55 * Per-Processor registers
56 */
57
58#define MPIC_CPU_THISBASE 0x00000
59#define MPIC_CPU_BASE 0x20000
60#define MPIC_CPU_STRIDE 0x01000
61
62#define MPIC_CPU_IPI_DISPATCH_0 0x00040
63#define MPIC_CPU_IPI_DISPATCH_1 0x00050
64#define MPIC_CPU_IPI_DISPATCH_2 0x00060
65#define MPIC_CPU_IPI_DISPATCH_3 0x00070
66#define MPIC_CPU_CURRENT_TASK_PRI 0x00080
67#define MPIC_CPU_TASKPRI_MASK 0x0000000f
68#define MPIC_CPU_WHOAMI 0x00090
69#define MPIC_CPU_WHOAMI_MASK 0x0000001f
70#define MPIC_CPU_INTACK 0x000a0
71#define MPIC_CPU_EOI 0x000b0
72
73/*
74 * Per-source registers
75 */
76
77#define MPIC_IRQ_BASE 0x10000
78#define MPIC_IRQ_STRIDE 0x00020
79#define MPIC_IRQ_VECTOR_PRI 0x00000
80#define MPIC_VECPRI_MASK 0x80000000
81#define MPIC_VECPRI_ACTIVITY 0x40000000 /* Read Only */
82#define MPIC_VECPRI_PRIORITY_MASK 0x000f0000
83#define MPIC_VECPRI_PRIORITY_SHIFT 16
84#define MPIC_VECPRI_VECTOR_MASK 0x000007ff
85#define MPIC_VECPRI_POLARITY_POSITIVE 0x00800000
86#define MPIC_VECPRI_POLARITY_NEGATIVE 0x00000000
87#define MPIC_VECPRI_POLARITY_MASK 0x00800000
88#define MPIC_VECPRI_SENSE_LEVEL 0x00400000
89#define MPIC_VECPRI_SENSE_EDGE 0x00000000
90#define MPIC_VECPRI_SENSE_MASK 0x00400000
91#define MPIC_IRQ_DESTINATION 0x00010
92
93#define MPIC_MAX_IRQ_SOURCES 2048
94#define MPIC_MAX_CPUS 32
95#define MPIC_MAX_ISU 32
96
97/*
98 * Special vector numbers (internal use only)
99 */
100#define MPIC_VEC_SPURRIOUS 255
101#define MPIC_VEC_IPI_3 254
102#define MPIC_VEC_IPI_2 253
103#define MPIC_VEC_IPI_1 252
104#define MPIC_VEC_IPI_0 251
105
106/* unused */
107#define MPIC_VEC_TIMER_3 250
108#define MPIC_VEC_TIMER_2 249
109#define MPIC_VEC_TIMER_1 248
110#define MPIC_VEC_TIMER_0 247
111
112/* Type definition of the cascade handler */
113typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data);
114
115#ifdef CONFIG_MPIC_BROKEN_U3
116/* Fixup table entry */
117struct mpic_irq_fixup
118{
119 u8 __iomem *base;
120 unsigned int irq;
121};
122#endif /* CONFIG_MPIC_BROKEN_U3 */
123
124
125/* The instance data of a given MPIC */
126struct mpic
127{
128 /* The "linux" controller struct */
129 hw_irq_controller hc_irq;
130#ifdef CONFIG_SMP
131 hw_irq_controller hc_ipi;
132#endif
133 const char *name;
134 /* Flags */
135 unsigned int flags;
136 /* How many irq sources in a given ISU */
137 unsigned int isu_size;
138 unsigned int isu_shift;
139 unsigned int isu_mask;
140 /* Offset of irq vector numbers */
141 unsigned int irq_offset;
142 unsigned int irq_count;
143 /* Offset of ipi vector numbers */
144 unsigned int ipi_offset;
145 /* Number of sources */
146 unsigned int num_sources;
147 /* Number of CPUs */
148 unsigned int num_cpus;
149 /* cascade handler */
150 mpic_cascade_t cascade;
151 void *cascade_data;
152 unsigned int cascade_vec;
153 /* senses array */
154 unsigned char *senses;
155 unsigned int senses_count;
156
157#ifdef CONFIG_MPIC_BROKEN_U3
158 /* The fixup table */
159 struct mpic_irq_fixup *fixups;
160 spinlock_t fixup_lock;
161#endif
162
163 /* The various ioremap'ed bases */
164 volatile u32 __iomem *gregs;
165 volatile u32 __iomem *tmregs;
166 volatile u32 __iomem *cpuregs[MPIC_MAX_CPUS];
167 volatile u32 __iomem *isus[MPIC_MAX_ISU];
168
169 /* link */
170 struct mpic *next;
171};
172
173/* This is the primary controller, only that one has IPIs and
174 * has afinity control. A non-primary MPIC always uses CPU0
175 * registers only
176 */
177#define MPIC_PRIMARY 0x00000001
178/* Set this for a big-endian MPIC */
179#define MPIC_BIG_ENDIAN 0x00000002
180/* Broken U3 MPIC */
181#define MPIC_BROKEN_U3 0x00000004
182/* Broken IPI registers (autodetected) */
183#define MPIC_BROKEN_IPI 0x00000008
184/* MPIC wants a reset */
185#define MPIC_WANTS_RESET 0x00000010
186
187/* Allocate the controller structure and setup the linux irq descs
188 * for the range if interrupts passed in. No HW initialization is
189 * actually performed.
190 *
191 * @phys_addr: physial base address of the MPIC
192 * @flags: flags, see constants above
193 * @isu_size: number of interrupts in an ISU. Use 0 to use a
194 * standard ISU-less setup (aka powermac)
195 * @irq_offset: first irq number to assign to this mpic
196 * @irq_count: number of irqs to use with this mpic IRQ sources. Pass 0
197 * to match the number of sources
198 * @ipi_offset: first irq number to assign to this mpic IPI sources,
199 * used only on primary mpic
200 * @senses: array of sense values
201 * @senses_num: number of entries in the array
202 *
203 * Note about the sense array. If none is passed, all interrupts are
204 * setup to be level negative unless MPIC_BROKEN_U3 is set in which
205 * case they are edge positive (and the array is ignored anyway).
206 * The values in the array start at the first source of the MPIC,
207 * that is senses[0] correspond to linux irq "irq_offset".
208 */
209extern struct mpic *mpic_alloc(unsigned long phys_addr,
210 unsigned int flags,
211 unsigned int isu_size,
212 unsigned int irq_offset,
213 unsigned int irq_count,
214 unsigned int ipi_offset,
215 unsigned char *senses,
216 unsigned int senses_num,
217 const char *name);
218
219/* Assign ISUs, to call before mpic_init()
220 *
221 * @mpic: controller structure as returned by mpic_alloc()
222 * @isu_num: ISU number
223 * @phys_addr: physical address of the ISU
224 */
225extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
226 unsigned long phys_addr);
227
228/* Initialize the controller. After this has been called, none of the above
229 * should be called again for this mpic
230 */
231extern void mpic_init(struct mpic *mpic);
232
233/* Setup a cascade. Currently, only one cascade is supported this
234 * way, though you can always do a normal request_irq() and add
235 * other cascades this way. You should call this _after_ having
236 * added all the ISUs
237 *
238 * @irq_no: "linux" irq number of the cascade (that is offset'ed vector)
239 * @handler: cascade handler function
240 */
241extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder,
242 void *data);
243
244/*
245 * All of the following functions must only be used after the
246 * ISUs have been assigned and the controller fully initialized
247 * with mpic_init()
248 */
249
250
251/* Change/Read the priority of an interrupt. Default is 8 for irqs and
252 * 10 for IPIs. You can call this on both IPIs and IRQ numbers, but the
253 * IPI number is then the offset'ed (linux irq number mapped to the IPI)
254 */
255extern void mpic_irq_set_priority(unsigned int irq, unsigned int pri);
256extern unsigned int mpic_irq_get_priority(unsigned int irq);
257
258/* Setup a non-boot CPU */
259extern void mpic_setup_this_cpu(void);
260
261/* Clean up for kexec (or cpu offline or ...) */
262extern void mpic_teardown_this_cpu(int secondary);
263
264/* Get the current cpu priority for this cpu (0..15) */
265extern int mpic_cpu_get_priority(void);
266
267/* Set the current cpu priority for this cpu */
268extern void mpic_cpu_set_priority(int prio);
269
270/* Request IPIs on primary mpic */
271extern void mpic_request_ipis(void);
272
273/* Send an IPI (non offseted number 0..3) */
274extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask);
275
276/* Send a message (IPI) to a given target (cpu number or MSG_*) */
277void smp_mpic_message_pass(int target, int msg);
278
279/* Fetch interrupt from a given mpic */
280extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs);
281/* This one gets to the primary mpic */
282extern int mpic_get_irq(struct pt_regs *regs);
283
284/* global mpic for pSeries */
285extern struct mpic *pSeries_mpic;
286
287#endif /* _ASM_POWERPC_MPIC_H */
diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h
new file mode 100644
index 000000000000..ddb16aae0bd6
--- /dev/null
+++ b/include/asm-powerpc/of_device.h
@@ -0,0 +1,64 @@
1#ifndef _ASM_POWERPC_OF_DEVICE_H
2#define _ASM_POWERPC_OF_DEVICE_H
3
4#include <linux/device.h>
5#include <linux/mod_devicetable.h>
6#include <asm/prom.h>
7
8/*
9 * The of_platform_bus_type is a bus type used by drivers that do not
10 * attach to a macio or similar bus but still use OF probing
11 * mecanism
12 */
13extern struct bus_type of_platform_bus_type;
14
15/*
16 * The of_device is a kind of "base class" that is a superset of
17 * struct device for use by devices attached to an OF node and
18 * probed using OF properties
19 */
20struct of_device
21{
22 struct device_node *node; /* OF device node */
23 u64 dma_mask; /* DMA mask */
24 struct device dev; /* Generic device interface */
25};
26#define to_of_device(d) container_of(d, struct of_device, dev)
27
28extern const struct of_device_id *of_match_device(
29 const struct of_device_id *matches, const struct of_device *dev);
30
31extern struct of_device *of_dev_get(struct of_device *dev);
32extern void of_dev_put(struct of_device *dev);
33
34/*
35 * An of_platform_driver driver is attached to a basic of_device on
36 * the "platform bus" (of_platform_bus_type)
37 */
38struct of_platform_driver
39{
40 char *name;
41 struct of_device_id *match_table;
42 struct module *owner;
43
44 int (*probe)(struct of_device* dev, const struct of_device_id *match);
45 int (*remove)(struct of_device* dev);
46
47 int (*suspend)(struct of_device* dev, pm_message_t state);
48 int (*resume)(struct of_device* dev);
49 int (*shutdown)(struct of_device* dev);
50
51 struct device_driver driver;
52};
53#define to_of_platform_driver(drv) container_of(drv,struct of_platform_driver, driver)
54
55extern int of_register_driver(struct of_platform_driver *drv);
56extern void of_unregister_driver(struct of_platform_driver *drv);
57extern int of_device_register(struct of_device *ofdev);
58extern void of_device_unregister(struct of_device *ofdev);
59extern struct of_device *of_platform_device_create(struct device_node *np,
60 const char *bus_id,
61 struct device *parent);
62extern void of_release_dev(struct device *dev);
63
64#endif /* _ASM_POWERPC_OF_DEVICE_H */
diff --git a/include/asm-powerpc/ohare.h b/include/asm-powerpc/ohare.h
new file mode 100644
index 000000000000..023b59772231
--- /dev/null
+++ b/include/asm-powerpc/ohare.h
@@ -0,0 +1,48 @@
1/*
2 * ohare.h: definitions for using the "O'Hare" I/O controller chip.
3 *
4 * Copyright (C) 1997 Paul Mackerras.
5 *
6 * BenH: Changed to match those of heathrow (but not all of them). Please
7 * check if I didn't break anything (especially the media bay).
8 */
9
10/* offset from ohare base for feature control register */
11#define OHARE_MBCR 0x34
12#define OHARE_FCR 0x38
13
14/*
15 * Bits in feature control register.
16 * These were mostly derived by experiment on a powerbook 3400
17 * and may differ for other machines.
18 */
19#define OH_SCC_RESET 1
20#define OH_BAY_POWER_N 2 /* a guess */
21#define OH_BAY_PCI_ENABLE 4 /* a guess */
22#define OH_BAY_IDE_ENABLE 8
23#define OH_BAY_FLOPPY_ENABLE 0x10
24#define OH_IDE0_ENABLE 0x20
25#define OH_IDE0_RESET_N 0x40 /* a guess */
26#define OH_BAY_DEV_MASK 0x1c
27#define OH_BAY_RESET_N 0x80
28#define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */
29#define OH_SCC_ENABLE 0x200
30#define OH_MESH_ENABLE 0x400
31#define OH_FLOPPY_ENABLE 0x800
32#define OH_SCCA_IO 0x4000
33#define OH_SCCB_IO 0x8000
34#define OH_VIA_ENABLE 0x10000 /* Is apparently wrong, to be verified */
35#define OH_IDE1_RESET_N 0x800000
36
37/*
38 * Bits to set in the feature control register on PowerBooks.
39 */
40#define PBOOK_FEATURES (OH_IDE_ENABLE | OH_SCC_ENABLE | \
41 OH_MESH_ENABLE | OH_SCCA_IO | OH_SCCB_IO)
42
43/*
44 * A magic value to put into the feature control register of the
45 * "ohare" I/O controller on Starmaxes to enable the IDE CD interface.
46 * Contributed by Harry Eaton.
47 */
48#define STARMAX_FEATURES 0xbeff7a
diff --git a/include/asm-powerpc/oprofile_impl.h b/include/asm-powerpc/oprofile_impl.h
new file mode 100644
index 000000000000..8013cd273ced
--- /dev/null
+++ b/include/asm-powerpc/oprofile_impl.h
@@ -0,0 +1,123 @@
1/*
2 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
3 *
4 * Based on alpha version.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#ifndef _ASM_POWERPC_OPROFILE_IMPL_H
13#define _ASM_POWERPC_OPROFILE_IMPL_H
14
15#define OP_MAX_COUNTER 8
16
17/* Per-counter configuration as set via oprofilefs. */
18struct op_counter_config {
19#ifdef __powerpc64__
20 unsigned long valid;
21#endif
22 unsigned long enabled;
23 unsigned long event;
24 unsigned long count;
25 unsigned long kernel;
26#ifdef __powerpc64__
27 /* We dont support per counter user/kernel selection */
28#endif
29 unsigned long user;
30 unsigned long unit_mask;
31};
32
33/* System-wide configuration as set via oprofilefs. */
34struct op_system_config {
35#ifdef __powerpc64__
36 unsigned long mmcr0;
37 unsigned long mmcr1;
38 unsigned long mmcra;
39#endif
40 unsigned long enable_kernel;
41 unsigned long enable_user;
42#ifdef __powerpc64__
43 unsigned long backtrace_spinlocks;
44#endif
45};
46
47/* Per-arch configuration */
48struct op_powerpc_model {
49 void (*reg_setup) (struct op_counter_config *,
50 struct op_system_config *,
51 int num_counters);
52#ifdef __powerpc64__
53 void (*cpu_setup) (void *);
54#endif
55 void (*start) (struct op_counter_config *);
56 void (*stop) (void);
57 void (*handle_interrupt) (struct pt_regs *,
58 struct op_counter_config *);
59 int num_counters;
60};
61
62#ifdef __powerpc64__
63extern struct op_powerpc_model op_model_rs64;
64extern struct op_powerpc_model op_model_power4;
65
66static inline unsigned int ctr_read(unsigned int i)
67{
68 switch(i) {
69 case 0:
70 return mfspr(SPRN_PMC1);
71 case 1:
72 return mfspr(SPRN_PMC2);
73 case 2:
74 return mfspr(SPRN_PMC3);
75 case 3:
76 return mfspr(SPRN_PMC4);
77 case 4:
78 return mfspr(SPRN_PMC5);
79 case 5:
80 return mfspr(SPRN_PMC6);
81 case 6:
82 return mfspr(SPRN_PMC7);
83 case 7:
84 return mfspr(SPRN_PMC8);
85 default:
86 return 0;
87 }
88}
89
90static inline void ctr_write(unsigned int i, unsigned int val)
91{
92 switch(i) {
93 case 0:
94 mtspr(SPRN_PMC1, val);
95 break;
96 case 1:
97 mtspr(SPRN_PMC2, val);
98 break;
99 case 2:
100 mtspr(SPRN_PMC3, val);
101 break;
102 case 3:
103 mtspr(SPRN_PMC4, val);
104 break;
105 case 4:
106 mtspr(SPRN_PMC5, val);
107 break;
108 case 5:
109 mtspr(SPRN_PMC6, val);
110 break;
111 case 6:
112 mtspr(SPRN_PMC7, val);
113 break;
114 case 7:
115 mtspr(SPRN_PMC8, val);
116 break;
117 default:
118 break;
119 }
120}
121#endif /* __powerpc64__ */
122
123#endif /* _ASM_POWERPC_OPROFILE_IMPL_H */
diff --git a/include/asm-powerpc/pSeries_reconfig.h b/include/asm-powerpc/pSeries_reconfig.h
new file mode 100644
index 000000000000..c0db1ea7f7d1
--- /dev/null
+++ b/include/asm-powerpc/pSeries_reconfig.h
@@ -0,0 +1,25 @@
1#ifndef _PPC64_PSERIES_RECONFIG_H
2#define _PPC64_PSERIES_RECONFIG_H
3
4#include <linux/notifier.h>
5
6/*
7 * Use this API if your code needs to know about OF device nodes being
8 * added or removed on pSeries systems.
9 */
10
11#define PSERIES_RECONFIG_ADD 0x0001
12#define PSERIES_RECONFIG_REMOVE 0x0002
13
14#ifdef CONFIG_PPC_PSERIES
15extern int pSeries_reconfig_notifier_register(struct notifier_block *);
16extern void pSeries_reconfig_notifier_unregister(struct notifier_block *);
17#else /* !CONFIG_PPC_PSERIES */
18static inline int pSeries_reconfig_notifier_register(struct notifier_block *nb)
19{
20 return 0;
21}
22static inline void pSeries_reconfig_notifier_unregister(struct notifier_block *nb) { }
23#endif /* CONFIG_PPC_PSERIES */
24
25#endif /* _PPC64_PSERIES_RECONFIG_H */
diff --git a/include/asm-powerpc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h
new file mode 100644
index 000000000000..e9683bcff19b
--- /dev/null
+++ b/include/asm-powerpc/pmac_feature.h
@@ -0,0 +1,380 @@
1/*
2 * Definition of platform feature hooks for PowerMacs
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1998 Paul Mackerras &
9 * Ben. Herrenschmidt.
10 *
11 *
12 * Note: I removed media-bay details from the feature stuff, I believe it's
13 * not worth it, the media-bay driver can directly use the mac-io
14 * ASIC registers.
15 *
16 * Implementation note: Currently, none of these functions will block.
17 * However, they may internally protect themselves with a spinlock
18 * for way too long. Be prepared for at least some of these to block
19 * in the future.
20 *
21 * Unless specifically defined, the result code is assumed to be an
22 * error when negative, 0 is the default success result. Some functions
23 * may return additional positive result values.
24 *
25 * To keep implementation simple, all feature calls are assumed to have
26 * the prototype parameters (struct device_node* node, int value).
27 * When either is not used, pass 0.
28 */
29
30#ifdef __KERNEL__
31#ifndef __PPC_ASM_PMAC_FEATURE_H
32#define __PPC_ASM_PMAC_FEATURE_H
33
34#include <asm/macio.h>
35#include <asm/machdep.h>
36
37/*
38 * Known Mac motherboard models
39 *
40 * Please, report any error here to benh@kernel.crashing.org, thanks !
41 *
42 * Note that I don't fully maintain this list for Core99 & MacRISC2
43 * and I'm considering removing all NewWorld entries from it and
44 * entirely rely on the model string.
45 */
46
47/* PowerSurge are the first generation of PCI Pmacs. This include
48 * all of the Grand-Central based machines. We currently don't
49 * differenciate most of them.
50 */
51#define PMAC_TYPE_PSURGE 0x10 /* PowerSurge */
52#define PMAC_TYPE_ANS 0x11 /* Apple Network Server */
53
54/* Here is the infamous serie of OHare based machines
55 */
56#define PMAC_TYPE_COMET 0x20 /* Beleived to be PowerBook 2400 */
57#define PMAC_TYPE_HOOPER 0x21 /* Beleived to be PowerBook 3400 */
58#define PMAC_TYPE_KANGA 0x22 /* PowerBook 3500 (first G3) */
59#define PMAC_TYPE_ALCHEMY 0x23 /* Alchemy motherboard base */
60#define PMAC_TYPE_GAZELLE 0x24 /* Spartacus, some 5xxx/6xxx */
61#define PMAC_TYPE_UNKNOWN_OHARE 0x2f /* Unknown, but OHare based */
62
63/* Here are the Heathrow based machines
64 * FIXME: Differenciate wallstreet,mainstreet,wallstreetII
65 */
66#define PMAC_TYPE_GOSSAMER 0x30 /* Gossamer motherboard */
67#define PMAC_TYPE_SILK 0x31 /* Desktop PowerMac G3 */
68#define PMAC_TYPE_WALLSTREET 0x32 /* Wallstreet/Mainstreet PowerBook*/
69#define PMAC_TYPE_UNKNOWN_HEATHROW 0x3f /* Unknown but heathrow based */
70
71/* Here are newworld machines based on Paddington (heathrow derivative)
72 */
73#define PMAC_TYPE_101_PBOOK 0x40 /* 101 PowerBook (aka Lombard) */
74#define PMAC_TYPE_ORIG_IMAC 0x41 /* First generation iMac */
75#define PMAC_TYPE_YOSEMITE 0x42 /* B&W G3 */
76#define PMAC_TYPE_YIKES 0x43 /* Yikes G4 (PCI graphics) */
77#define PMAC_TYPE_UNKNOWN_PADDINGTON 0x4f /* Unknown but paddington based */
78
79/* Core99 machines based on UniNorth 1.0 and 1.5
80 *
81 * Note: A single entry here may cover several actual models according
82 * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most
83 * FireWire based iMacs, etc...). Those machines are too similar to be
84 * distinguished here, when they need to be differencied, use the
85 * device-tree "model" or "compatible" property.
86 */
87#define PMAC_TYPE_ORIG_IBOOK 0x40 /* First iBook model (no firewire) */
88#define PMAC_TYPE_SAWTOOTH 0x41 /* Desktop G4s */
89#define PMAC_TYPE_FW_IMAC 0x42 /* FireWire iMacs (except Pangea based) */
90#define PMAC_TYPE_FW_IBOOK 0x43 /* FireWire iBooks (except iBook2) */
91#define PMAC_TYPE_CUBE 0x44 /* Cube PowerMac */
92#define PMAC_TYPE_QUICKSILVER 0x45 /* QuickSilver G4s */
93#define PMAC_TYPE_PISMO 0x46 /* Pismo PowerBook */
94#define PMAC_TYPE_TITANIUM 0x47 /* Titanium PowerBook */
95#define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook (no L3, M6) */
96#define PMAC_TYPE_TITANIUM3 0x49 /* Titanium III PowerBook (with L3 & M7) */
97#define PMAC_TYPE_TITANIUM4 0x50 /* Titanium IV PowerBook (with L3 & M9) */
98#define PMAC_TYPE_EMAC 0x50 /* eMac */
99#define PMAC_TYPE_UNKNOWN_CORE99 0x5f
100
101/* MacRisc2 with UniNorth 2.0 */
102#define PMAC_TYPE_RACKMAC 0x80 /* XServe */
103#define PMAC_TYPE_WINDTUNNEL 0x81
104
105/* MacRISC2 machines based on the Pangea chipset
106 */
107#define PMAC_TYPE_PANGEA_IMAC 0x100 /* Flower Power iMac */
108#define PMAC_TYPE_IBOOK2 0x101 /* iBook2 (polycarbonate) */
109#define PMAC_TYPE_FLAT_PANEL_IMAC 0x102 /* Flat panel iMac */
110#define PMAC_TYPE_UNKNOWN_PANGEA 0x10f
111
112/* MacRISC2 machines based on the Intrepid chipset
113 */
114#define PMAC_TYPE_UNKNOWN_INTREPID 0x11f /* Generic */
115
116/* MacRISC4 / G5 machines. We don't have per-machine selection here anymore,
117 * but rather machine families
118 */
119#define PMAC_TYPE_POWERMAC_G5 0x150 /* U3 & U3H based */
120#define PMAC_TYPE_POWERMAC_G5_U3L 0x151 /* U3L based desktop */
121#define PMAC_TYPE_IMAC_G5 0x152 /* iMac G5 */
122#define PMAC_TYPE_XSERVE_G5 0x153 /* Xserve G5 */
123#define PMAC_TYPE_UNKNOWN_K2 0x19f /* Any other K2 based */
124
125/*
126 * Motherboard flags
127 */
128
129#define PMAC_MB_CAN_SLEEP 0x00000001
130#define PMAC_MB_HAS_FW_POWER 0x00000002
131#define PMAC_MB_OLD_CORE99 0x00000004
132#define PMAC_MB_MOBILE 0x00000008
133#define PMAC_MB_MAY_SLEEP 0x00000010
134
135/*
136 * Feature calls supported on pmac
137 *
138 */
139
140/*
141 * Use this inline wrapper
142 */
143struct device_node;
144
145static inline long pmac_call_feature(int selector, struct device_node* node,
146 long param, long value)
147{
148 if (!ppc_md.feature_call)
149 return -ENODEV;
150 return ppc_md.feature_call(selector, node, param, value);
151}
152
153/* PMAC_FTR_SERIAL_ENABLE (struct device_node* node, int param, int value)
154 * enable/disable an SCC side. Pass the node corresponding to the
155 * channel side as a parameter.
156 * param is the type of port
157 * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled
158 * for use by xmon.
159 */
160#define PMAC_FTR_SCC_ENABLE PMAC_FTR_DEF(0)
161 #define PMAC_SCC_ASYNC 0
162 #define PMAC_SCC_IRDA 1
163 #define PMAC_SCC_I2S1 2
164 #define PMAC_SCC_FLAG_XMON 0x00001000
165
166/* PMAC_FTR_MODEM_ENABLE (struct device_node* node, 0, int value)
167 * enable/disable the internal modem.
168 */
169#define PMAC_FTR_MODEM_ENABLE PMAC_FTR_DEF(1)
170
171/* PMAC_FTR_SWIM3_ENABLE (struct device_node* node, 0,int value)
172 * enable/disable the swim3 (floppy) cell of a mac-io ASIC
173 */
174#define PMAC_FTR_SWIM3_ENABLE PMAC_FTR_DEF(2)
175
176/* PMAC_FTR_MESH_ENABLE (struct device_node* node, 0, int value)
177 * enable/disable the mesh (scsi) cell of a mac-io ASIC
178 */
179#define PMAC_FTR_MESH_ENABLE PMAC_FTR_DEF(3)
180
181/* PMAC_FTR_IDE_ENABLE (struct device_node* node, int busID, int value)
182 * enable/disable an IDE port of a mac-io ASIC
183 * pass the busID parameter
184 */
185#define PMAC_FTR_IDE_ENABLE PMAC_FTR_DEF(4)
186
187/* PMAC_FTR_IDE_RESET (struct device_node* node, int busID, int value)
188 * assert(1)/release(0) an IDE reset line (mac-io IDE only)
189 */
190#define PMAC_FTR_IDE_RESET PMAC_FTR_DEF(5)
191
192/* PMAC_FTR_BMAC_ENABLE (struct device_node* node, 0, int value)
193 * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive
194 * it's reset line
195 */
196#define PMAC_FTR_BMAC_ENABLE PMAC_FTR_DEF(6)
197
198/* PMAC_FTR_GMAC_ENABLE (struct device_node* node, 0, int value)
199 * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This
200 * control the cell's clock.
201 */
202#define PMAC_FTR_GMAC_ENABLE PMAC_FTR_DEF(7)
203
204/* PMAC_FTR_GMAC_PHY_RESET (struct device_node* node, 0, 0)
205 * Perform a HW reset of the PHY connected to a gmac controller.
206 * Pass the gmac device node, not the PHY node.
207 */
208#define PMAC_FTR_GMAC_PHY_RESET PMAC_FTR_DEF(8)
209
210/* PMAC_FTR_SOUND_CHIP_ENABLE (struct device_node* node, 0, int value)
211 * enable/disable the sound chip, whatever it is and provided it can
212 * acually be controlled
213 */
214#define PMAC_FTR_SOUND_CHIP_ENABLE PMAC_FTR_DEF(9)
215
216/* -- add various tweaks related to sound routing -- */
217
218/* PMAC_FTR_AIRPORT_ENABLE (struct device_node* node, 0, int value)
219 * enable/disable the airport card
220 */
221#define PMAC_FTR_AIRPORT_ENABLE PMAC_FTR_DEF(10)
222
223/* PMAC_FTR_RESET_CPU (NULL, int cpu_nr, 0)
224 * toggle the reset line of a CPU on an uninorth-based SMP machine
225 */
226#define PMAC_FTR_RESET_CPU PMAC_FTR_DEF(11)
227
228/* PMAC_FTR_USB_ENABLE (struct device_node* node, 0, int value)
229 * enable/disable an USB cell, along with the power of the USB "pad"
230 * on keylargo based machines
231 */
232#define PMAC_FTR_USB_ENABLE PMAC_FTR_DEF(12)
233
234/* PMAC_FTR_1394_ENABLE (struct device_node* node, 0, int value)
235 * enable/disable the firewire cell of an uninorth ASIC.
236 */
237#define PMAC_FTR_1394_ENABLE PMAC_FTR_DEF(13)
238
239/* PMAC_FTR_1394_CABLE_POWER (struct device_node* node, 0, int value)
240 * enable/disable the firewire cable power supply of the uninorth
241 * firewire cell
242 */
243#define PMAC_FTR_1394_CABLE_POWER PMAC_FTR_DEF(14)
244
245/* PMAC_FTR_SLEEP_STATE (struct device_node* node, 0, int value)
246 * set the sleep state of the motherboard.
247 *
248 * Pass -1 as value to query for sleep capability
249 * Pass 1 to set IOs to sleep
250 * Pass 0 to set IOs to wake
251 */
252#define PMAC_FTR_SLEEP_STATE PMAC_FTR_DEF(15)
253
254/* PMAC_FTR_GET_MB_INFO (NULL, selector, 0)
255 *
256 * returns some motherboard infos.
257 * selector: 0 - model id
258 * 1 - model flags (capabilities)
259 * 2 - model name (cast to const char *)
260 */
261#define PMAC_FTR_GET_MB_INFO PMAC_FTR_DEF(16)
262#define PMAC_MB_INFO_MODEL 0
263#define PMAC_MB_INFO_FLAGS 1
264#define PMAC_MB_INFO_NAME 2
265
266/* PMAC_FTR_READ_GPIO (NULL, int index, 0)
267 *
268 * read a GPIO from a mac-io controller of type KeyLargo or Pangea.
269 * the value returned is a byte (positive), or a negative error code
270 */
271#define PMAC_FTR_READ_GPIO PMAC_FTR_DEF(17)
272
273/* PMAC_FTR_WRITE_GPIO (NULL, int index, int value)
274 *
275 * write a GPIO of a mac-io controller of type KeyLargo or Pangea.
276 */
277#define PMAC_FTR_WRITE_GPIO PMAC_FTR_DEF(18)
278
279/* PMAC_FTR_ENABLE_MPIC
280 *
281 * Enable the MPIC cell
282 */
283#define PMAC_FTR_ENABLE_MPIC PMAC_FTR_DEF(19)
284
285/* PMAC_FTR_AACK_DELAY_ENABLE (NULL, int enable, 0)
286 *
287 * Enable/disable the AACK delay on the northbridge for systems using DFS
288 */
289#define PMAC_FTR_AACK_DELAY_ENABLE PMAC_FTR_DEF(20)
290
291/* PMAC_FTR_DEVICE_CAN_WAKE
292 *
293 * Used by video drivers to inform system that they can actually perform
294 * wakeup from sleep
295 */
296#define PMAC_FTR_DEVICE_CAN_WAKE PMAC_FTR_DEF(22)
297
298
299/* Don't use those directly, they are for the sake of pmac_setup.c */
300extern long pmac_do_feature_call(unsigned int selector, ...);
301extern void pmac_feature_init(void);
302
303/* Video suspend tweak */
304extern void pmac_set_early_video_resume(void (*proc)(void *data), void *data);
305extern void pmac_call_early_video_resume(void);
306
307#define PMAC_FTR_DEF(x) ((_MACH_Pmac << 16) | (x))
308
309/* The AGP driver registers itself here */
310extern void pmac_register_agp_pm(struct pci_dev *bridge,
311 int (*suspend)(struct pci_dev *bridge),
312 int (*resume)(struct pci_dev *bridge));
313
314/* Those are meant to be used by video drivers to deal with AGP
315 * suspend resume properly
316 */
317extern void pmac_suspend_agp_for_card(struct pci_dev *dev);
318extern void pmac_resume_agp_for_card(struct pci_dev *dev);
319
320/* Used by the via-pmu driver for suspend/resume
321 */
322extern void pmac_tweak_clock_spreading(int enable);
323
324/*
325 * The part below is for use by macio_asic.c only, do not rely
326 * on the data structures or constants below in a normal driver
327 *
328 */
329
330#define MAX_MACIO_CHIPS 2
331
332enum {
333 macio_unknown = 0,
334 macio_grand_central,
335 macio_ohare,
336 macio_ohareII,
337 macio_heathrow,
338 macio_gatwick,
339 macio_paddington,
340 macio_keylargo,
341 macio_pangea,
342 macio_intrepid,
343 macio_keylargo2,
344};
345
346struct macio_chip
347{
348 struct device_node *of_node;
349 int type;
350 const char *name;
351 int rev;
352 volatile u32 __iomem *base;
353 unsigned long flags;
354
355 /* For use by macio_asic PCI driver */
356 struct macio_bus lbus;
357};
358
359extern struct macio_chip macio_chips[MAX_MACIO_CHIPS];
360
361#define MACIO_FLAG_SCCA_ON 0x00000001
362#define MACIO_FLAG_SCCB_ON 0x00000002
363#define MACIO_FLAG_SCC_LOCKED 0x00000004
364#define MACIO_FLAG_AIRPORT_ON 0x00000010
365#define MACIO_FLAG_FW_SUPPORTED 0x00000020
366
367extern struct macio_chip* macio_find(struct device_node* child, int type);
368
369#define MACIO_FCR32(macio, r) ((macio)->base + ((r) >> 2))
370#define MACIO_FCR8(macio, r) (((volatile u8 __iomem *)((macio)->base)) + (r))
371
372#define MACIO_IN32(r) (in_le32(MACIO_FCR32(macio,r)))
373#define MACIO_OUT32(r,v) (out_le32(MACIO_FCR32(macio,r), (v)))
374#define MACIO_BIS(r,v) (MACIO_OUT32((r), MACIO_IN32(r) | (v)))
375#define MACIO_BIC(r,v) (MACIO_OUT32((r), MACIO_IN32(r) & ~(v)))
376#define MACIO_IN8(r) (in_8(MACIO_FCR8(macio,r)))
377#define MACIO_OUT8(r,v) (out_8(MACIO_FCR8(macio,r), (v)))
378
379#endif /* __PPC_ASM_PMAC_FEATURE_H */
380#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/pmac_low_i2c.h b/include/asm-powerpc/pmac_low_i2c.h
new file mode 100644
index 000000000000..809a5963d5e7
--- /dev/null
+++ b/include/asm-powerpc/pmac_low_i2c.h
@@ -0,0 +1,43 @@
1/*
2 * include/asm-ppc/pmac_low_i2c.h
3 *
4 * Copyright (C) 2003 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 *
11 */
12#ifndef __PMAC_LOW_I2C_H__
13#define __PMAC_LOW_I2C_H__
14
15/* i2c mode (based on the platform functions format) */
16enum {
17 pmac_low_i2c_mode_dumb = 1,
18 pmac_low_i2c_mode_std = 2,
19 pmac_low_i2c_mode_stdsub = 3,
20 pmac_low_i2c_mode_combined = 4,
21};
22
23/* RW bit in address */
24enum {
25 pmac_low_i2c_read = 0x01,
26 pmac_low_i2c_write = 0x00
27};
28
29/* Init, called early during boot */
30extern void pmac_init_low_i2c(void);
31
32/* Locking functions exposed to i2c-keywest */
33int pmac_low_i2c_lock(struct device_node *np);
34int pmac_low_i2c_unlock(struct device_node *np);
35
36/* Access functions for platform code */
37int pmac_low_i2c_open(struct device_node *np, int channel);
38int pmac_low_i2c_close(struct device_node *np);
39int pmac_low_i2c_setmode(struct device_node *np, int mode);
40int pmac_low_i2c_xfer(struct device_node *np, u8 addrdir, u8 subaddr, u8 *data, int len);
41
42
43#endif /* __PMAC_LOW_I2C_H__ */
diff --git a/include/asm-powerpc/pmc.h b/include/asm-powerpc/pmc.h
new file mode 100644
index 000000000000..2f3c3fc2b796
--- /dev/null
+++ b/include/asm-powerpc/pmc.h
@@ -0,0 +1,46 @@
1/*
2 * pmc.h
3 * Copyright (C) 2004 David Gibson, IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _POWERPC_PMC_H
20#define _POWERPC_PMC_H
21
22#include <asm/ptrace.h>
23
24typedef void (*perf_irq_t)(struct pt_regs *);
25
26int reserve_pmc_hardware(perf_irq_t new_perf_irq);
27void release_pmc_hardware(void);
28
29#ifdef CONFIG_PPC64
30void power4_enable_pmcs(void);
31#endif
32
33#ifdef CONFIG_FSL_BOOKE
34void init_pmc_stop(int ctr);
35void set_pmc_event(int ctr, int event);
36void set_pmc_user_kernel(int ctr, int user, int kernel);
37void set_pmc_marked(int ctr, int mark0, int mark1);
38void pmc_start_ctr(int ctr, int enable);
39void pmc_start_ctrs(int enable);
40void pmc_stop_ctrs(void);
41void dump_pmcs(void);
42
43extern struct op_powerpc_model op_model_fsl_booke;
44#endif
45
46#endif /* _POWERPC_PMC_H */
diff --git a/include/asm-powerpc/posix_types.h b/include/asm-powerpc/posix_types.h
new file mode 100644
index 000000000000..c6391077224f
--- /dev/null
+++ b/include/asm-powerpc/posix_types.h
@@ -0,0 +1,129 @@
1#ifndef _ASM_POWERPC_POSIX_TYPES_H
2#define _ASM_POWERPC_POSIX_TYPES_H
3
4/*
5 * This file is generally used by user-level software, so you need to
6 * be a little careful about namespace pollution etc. Also, we cannot
7 * assume GCC is being used.
8 */
9
10typedef unsigned long __kernel_ino_t;
11typedef unsigned int __kernel_mode_t;
12typedef long __kernel_off_t;
13typedef int __kernel_pid_t;
14typedef unsigned int __kernel_uid_t;
15typedef unsigned int __kernel_gid_t;
16typedef long __kernel_ptrdiff_t;
17typedef long __kernel_time_t;
18typedef long __kernel_clock_t;
19typedef int __kernel_timer_t;
20typedef int __kernel_clockid_t;
21typedef long __kernel_suseconds_t;
22typedef int __kernel_daddr_t;
23typedef char * __kernel_caddr_t;
24typedef unsigned short __kernel_uid16_t;
25typedef unsigned short __kernel_gid16_t;
26typedef unsigned int __kernel_uid32_t;
27typedef unsigned int __kernel_gid32_t;
28typedef unsigned int __kernel_old_uid_t;
29typedef unsigned int __kernel_old_gid_t;
30
31#ifdef __powerpc64__
32typedef unsigned long __kernel_nlink_t;
33typedef int __kernel_ipc_pid_t;
34typedef unsigned long __kernel_size_t;
35typedef long __kernel_ssize_t;
36typedef unsigned long __kernel_old_dev_t;
37#else
38typedef unsigned short __kernel_nlink_t;
39typedef short __kernel_ipc_pid_t;
40typedef unsigned int __kernel_size_t;
41typedef int __kernel_ssize_t;
42typedef unsigned int __kernel_old_dev_t;
43#endif
44
45#ifdef __powerpc64__
46typedef long long __kernel_loff_t;
47#else
48#ifdef __GNUC__
49typedef long long __kernel_loff_t;
50#endif
51#endif
52
53typedef struct {
54 int val[2];
55} __kernel_fsid_t;
56
57#ifndef __GNUC__
58
59#define __FD_SET(d, set) ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
60#define __FD_CLR(d, set) ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
61#define __FD_ISSET(d, set) (((set)->fds_bits[__FDELT(d)] & __FDMASK(d)) != 0)
62#define __FD_ZERO(set) \
63 ((void) memset ((__ptr_t) (set), 0, sizeof (__kernel_fd_set)))
64
65#else /* __GNUC__ */
66
67#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) \
68 || (__GLIBC__ == 2 && __GLIBC_MINOR__ == 0)
69/* With GNU C, use inline functions instead so args are evaluated only once: */
70
71#undef __FD_SET
72static __inline__ void __FD_SET(unsigned long fd, __kernel_fd_set *fdsetp)
73{
74 unsigned long _tmp = fd / __NFDBITS;
75 unsigned long _rem = fd % __NFDBITS;
76 fdsetp->fds_bits[_tmp] |= (1UL<<_rem);
77}
78
79#undef __FD_CLR
80static __inline__ void __FD_CLR(unsigned long fd, __kernel_fd_set *fdsetp)
81{
82 unsigned long _tmp = fd / __NFDBITS;
83 unsigned long _rem = fd % __NFDBITS;
84 fdsetp->fds_bits[_tmp] &= ~(1UL<<_rem);
85}
86
87#undef __FD_ISSET
88static __inline__ int __FD_ISSET(unsigned long fd, __kernel_fd_set *p)
89{
90 unsigned long _tmp = fd / __NFDBITS;
91 unsigned long _rem = fd % __NFDBITS;
92 return (p->fds_bits[_tmp] & (1UL<<_rem)) != 0;
93}
94
95/*
96 * This will unroll the loop for the normal constant case (8 ints,
97 * for a 256-bit fd_set)
98 */
99#undef __FD_ZERO
100static __inline__ void __FD_ZERO(__kernel_fd_set *p)
101{
102 unsigned long *tmp = (unsigned long *)p->fds_bits;
103 int i;
104
105 if (__builtin_constant_p(__FDSET_LONGS)) {
106 switch (__FDSET_LONGS) {
107 case 16:
108 tmp[12] = 0; tmp[13] = 0; tmp[14] = 0; tmp[15] = 0;
109 tmp[ 8] = 0; tmp[ 9] = 0; tmp[10] = 0; tmp[11] = 0;
110
111 case 8:
112 tmp[ 4] = 0; tmp[ 5] = 0; tmp[ 6] = 0; tmp[ 7] = 0;
113
114 case 4:
115 tmp[ 0] = 0; tmp[ 1] = 0; tmp[ 2] = 0; tmp[ 3] = 0;
116 return;
117 }
118 }
119 i = __FDSET_LONGS;
120 while (i) {
121 i--;
122 *tmp = 0;
123 tmp++;
124 }
125}
126
127#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
128#endif /* __GNUC__ */
129#endif /* _ASM_POWERPC_POSIX_TYPES_H */
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
new file mode 100644
index 000000000000..a88728fba8f6
--- /dev/null
+++ b/include/asm-powerpc/ppc-pci.h
@@ -0,0 +1,54 @@
1/*
2 * c 2001 PPC 64 Team, IBM Corp
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9#ifndef _ASM_POWERPC_PPC_PCI_H
10#define _ASM_POWERPC_PPC_PCI_H
11
12#include <linux/pci.h>
13#include <asm/pci-bridge.h>
14
15extern unsigned long isa_io_base;
16
17extern void pci_setup_pci_controller(struct pci_controller *hose);
18extern void pci_setup_phb_io(struct pci_controller *hose, int primary);
19extern void pci_setup_phb_io_dynamic(struct pci_controller *hose, int primary);
20
21
22extern struct list_head hose_list;
23extern int global_phb_number;
24
25extern unsigned long find_and_init_phbs(void);
26
27extern struct pci_dev *ppc64_isabridge_dev; /* may be NULL if no ISA bus */
28
29/* PCI device_node operations */
30struct device_node;
31typedef void *(*traverse_func)(struct device_node *me, void *data);
32void *traverse_pci_devices(struct device_node *start, traverse_func pre,
33 void *data);
34
35void pci_devs_phb_init(void);
36void pci_devs_phb_init_dynamic(struct pci_controller *phb);
37
38/* PCI address cache management routines */
39void pci_addr_cache_insert_device(struct pci_dev *dev);
40void pci_addr_cache_remove_device(struct pci_dev *dev);
41
42/* From rtas_pci.h */
43void init_pci_config_tokens (void);
44unsigned long get_phb_buid (struct device_node *);
45
46/* From pSeries_pci.h */
47extern void pSeries_final_fixup(void);
48extern void pSeries_irq_bus_setup(struct pci_bus *bus);
49
50extern unsigned long pci_probe_only;
51extern unsigned long pci_assign_all_buses;
52extern int pci_read_irq_line(struct pci_dev *pci_dev);
53
54#endif /* _ASM_POWERPC_PPC_PCI_H */
diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
new file mode 100644
index 000000000000..96367e04fa58
--- /dev/null
+++ b/include/asm-powerpc/ppc_asm.h
@@ -0,0 +1,502 @@
1/*
2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
3 */
4#ifndef _ASM_POWERPC_PPC_ASM_H
5#define _ASM_POWERPC_PPC_ASM_H
6
7#include <linux/stringify.h>
8#include <linux/config.h>
9
10#ifdef __ASSEMBLY__
11
12/*
13 * Macros for storing registers into and loading registers from
14 * exception frames.
15 */
16#ifdef __powerpc64__
17#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
18#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
19#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
20#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
21#else
22#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
23#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
24#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
25 SAVE_10GPRS(22, base)
26#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
27 REST_10GPRS(22, base)
28#endif
29
30
31#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
32#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
33#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
34#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
35#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
36#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
37#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
38#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
39
40#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
41#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
42#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
43#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
44#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
45#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
46#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
47#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
48#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
49#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
50#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
51#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
52
53#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
54#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
55#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
56#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
57#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
58#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
59#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
60#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
61#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
62#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
63#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
64#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
65
66#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
67#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
68#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
69#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
70#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
71#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
72#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
73#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
74#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
75#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
76#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
77#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
78
79/* Macros to adjust thread priority for Iseries hardware multithreading */
80#define HMT_VERY_LOW or 31,31,31 # very low priority\n"
81#define HMT_LOW or 1,1,1
82#define HMT_MEDIUM_LOW or 6,6,6 # medium low priority\n"
83#define HMT_MEDIUM or 2,2,2
84#define HMT_MEDIUM_HIGH or 5,5,5 # medium high priority\n"
85#define HMT_HIGH or 3,3,3
86
87/* handle instructions that older assemblers may not know */
88#define RFCI .long 0x4c000066 /* rfci instruction */
89#define RFDI .long 0x4c00004e /* rfdi instruction */
90#define RFMCI .long 0x4c00004c /* rfmci instruction */
91
92#ifdef CONFIG_PPC64
93
94#define XGLUE(a,b) a##b
95#define GLUE(a,b) XGLUE(a,b)
96
97#define _GLOBAL(name) \
98 .section ".text"; \
99 .align 2 ; \
100 .globl name; \
101 .globl GLUE(.,name); \
102 .section ".opd","aw"; \
103name: \
104 .quad GLUE(.,name); \
105 .quad .TOC.@tocbase; \
106 .quad 0; \
107 .previous; \
108 .type GLUE(.,name),@function; \
109GLUE(.,name):
110
111#define _KPROBE(name) \
112 .section ".kprobes.text","a"; \
113 .align 2 ; \
114 .globl name; \
115 .globl GLUE(.,name); \
116 .section ".opd","aw"; \
117name: \
118 .quad GLUE(.,name); \
119 .quad .TOC.@tocbase; \
120 .quad 0; \
121 .previous; \
122 .type GLUE(.,name),@function; \
123GLUE(.,name):
124
125#define _STATIC(name) \
126 .section ".text"; \
127 .align 2 ; \
128 .section ".opd","aw"; \
129name: \
130 .quad GLUE(.,name); \
131 .quad .TOC.@tocbase; \
132 .quad 0; \
133 .previous; \
134 .type GLUE(.,name),@function; \
135GLUE(.,name):
136
137#else /* 32-bit */
138
139#define _GLOBAL(n) \
140 .text; \
141 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
142 .globl n; \
143n:
144
145#define _KPROBE(n) \
146 .section ".kprobes.text","a"; \
147 .globl n; \
148n:
149
150#endif
151
152/*
153 * LOADADDR( rn, name )
154 * loads the address of 'name' into 'rn'
155 *
156 * LOADBASE( rn, name )
157 * loads the address (less the low 16 bits) of 'name' into 'rn'
158 * suitable for base+disp addressing
159 */
160#ifdef __powerpc64__
161#define LOADADDR(rn,name) \
162 lis rn,name##@highest; \
163 ori rn,rn,name##@higher; \
164 rldicr rn,rn,32,31; \
165 oris rn,rn,name##@h; \
166 ori rn,rn,name##@l
167
168#define LOADBASE(rn,name) \
169 .section .toc,"aw"; \
1701: .tc name[TC],name; \
171 .previous; \
172 ld rn,1b@toc(r2)
173
174#define OFF(name) 0
175
176#define SET_REG_TO_CONST(reg, value) \
177 lis reg,(((value)>>48)&0xFFFF); \
178 ori reg,reg,(((value)>>32)&0xFFFF); \
179 rldicr reg,reg,32,31; \
180 oris reg,reg,(((value)>>16)&0xFFFF); \
181 ori reg,reg,((value)&0xFFFF);
182
183#define SET_REG_TO_LABEL(reg, label) \
184 lis reg,(label)@highest; \
185 ori reg,reg,(label)@higher; \
186 rldicr reg,reg,32,31; \
187 oris reg,reg,(label)@h; \
188 ori reg,reg,(label)@l;
189
190/* operations for longs and pointers */
191#define LDL ld
192#define STL std
193#define CMPI cmpdi
194
195#else /* 32-bit */
196#define LOADADDR(rn,name) \
197 lis rn,name@ha; \
198 addi rn,rn,name@l
199
200#define LOADBASE(rn,name) \
201 lis rn,name@ha
202
203#define OFF(name) name@l
204
205/* operations for longs and pointers */
206#define LDL lwz
207#define STL stw
208#define CMPI cmpwi
209
210#endif
211
212/* various errata or part fixups */
213#ifdef CONFIG_PPC601_SYNC_FIX
214#define SYNC \
215BEGIN_FTR_SECTION \
216 sync; \
217 isync; \
218END_FTR_SECTION_IFSET(CPU_FTR_601)
219#define SYNC_601 \
220BEGIN_FTR_SECTION \
221 sync; \
222END_FTR_SECTION_IFSET(CPU_FTR_601)
223#define ISYNC_601 \
224BEGIN_FTR_SECTION \
225 isync; \
226END_FTR_SECTION_IFSET(CPU_FTR_601)
227#else
228#define SYNC
229#define SYNC_601
230#define ISYNC_601
231#endif
232
233
234#ifndef CONFIG_SMP
235#define TLBSYNC
236#else /* CONFIG_SMP */
237/* tlbsync is not implemented on 601 */
238#define TLBSYNC \
239BEGIN_FTR_SECTION \
240 tlbsync; \
241 sync; \
242END_FTR_SECTION_IFCLR(CPU_FTR_601)
243#endif
244
245
246/*
247 * This instruction is not implemented on the PPC 603 or 601; however, on
248 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
249 * All of these instructions exist in the 8xx, they have magical powers,
250 * and they must be used.
251 */
252
253#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
254#define tlbia \
255 li r4,1024; \
256 mtctr r4; \
257 lis r4,KERNELBASE@h; \
2580: tlbie r4; \
259 addi r4,r4,0x1000; \
260 bdnz 0b
261#endif
262
263
264#ifdef CONFIG_IBM405_ERR77
265#define PPC405_ERR77(ra,rb) dcbt ra, rb;
266#define PPC405_ERR77_SYNC sync;
267#else
268#define PPC405_ERR77(ra,rb)
269#define PPC405_ERR77_SYNC
270#endif
271
272
273#ifdef CONFIG_IBM440EP_ERR42
274#define PPC440EP_ERR42 isync
275#else
276#define PPC440EP_ERR42
277#endif
278
279
280#if defined(CONFIG_BOOKE)
281#define tophys(rd,rs) \
282 addis rd,rs,0
283
284#define tovirt(rd,rs) \
285 addis rd,rs,0
286
287#elif defined(CONFIG_PPC64)
288/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
289 * Then we can easily do this with one asm insn. -Peter
290 */
291#define tophys(rd,rs) \
292 lis rd,((KERNELBASE>>48)&0xFFFF); \
293 rldicr rd,rd,32,31; \
294 sub rd,rs,rd
295
296#define tovirt(rd,rs) \
297 lis rd,((KERNELBASE>>48)&0xFFFF); \
298 rldicr rd,rd,32,31; \
299 add rd,rs,rd
300#else
301/*
302 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
303 * physical base address of RAM at compile time.
304 */
305#define tophys(rd,rs) \
3060: addis rd,rs,-KERNELBASE@h; \
307 .section ".vtop_fixup","aw"; \
308 .align 1; \
309 .long 0b; \
310 .previous
311
312#define tovirt(rd,rs) \
3130: addis rd,rs,KERNELBASE@h; \
314 .section ".ptov_fixup","aw"; \
315 .align 1; \
316 .long 0b; \
317 .previous
318#endif
319
320#ifdef CONFIG_PPC64
321#define RFI rfid
322#define MTMSRD(r) mtmsrd r
323
324#else
325#define FIX_SRR1(ra, rb)
326#ifndef CONFIG_40x
327#define RFI rfi
328#else
329#define RFI rfi; b . /* Prevent prefetch past rfi */
330#endif
331#define MTMSRD(r) mtmsr r
332#define CLR_TOP32(r)
333#endif
334
335/* The boring bits... */
336
337/* Condition Register Bit Fields */
338
339#define cr0 0
340#define cr1 1
341#define cr2 2
342#define cr3 3
343#define cr4 4
344#define cr5 5
345#define cr6 6
346#define cr7 7
347
348
349/* General Purpose Registers (GPRs) */
350
351#define r0 0
352#define r1 1
353#define r2 2
354#define r3 3
355#define r4 4
356#define r5 5
357#define r6 6
358#define r7 7
359#define r8 8
360#define r9 9
361#define r10 10
362#define r11 11
363#define r12 12
364#define r13 13
365#define r14 14
366#define r15 15
367#define r16 16
368#define r17 17
369#define r18 18
370#define r19 19
371#define r20 20
372#define r21 21
373#define r22 22
374#define r23 23
375#define r24 24
376#define r25 25
377#define r26 26
378#define r27 27
379#define r28 28
380#define r29 29
381#define r30 30
382#define r31 31
383
384
385/* Floating Point Registers (FPRs) */
386
387#define fr0 0
388#define fr1 1
389#define fr2 2
390#define fr3 3
391#define fr4 4
392#define fr5 5
393#define fr6 6
394#define fr7 7
395#define fr8 8
396#define fr9 9
397#define fr10 10
398#define fr11 11
399#define fr12 12
400#define fr13 13
401#define fr14 14
402#define fr15 15
403#define fr16 16
404#define fr17 17
405#define fr18 18
406#define fr19 19
407#define fr20 20
408#define fr21 21
409#define fr22 22
410#define fr23 23
411#define fr24 24
412#define fr25 25
413#define fr26 26
414#define fr27 27
415#define fr28 28
416#define fr29 29
417#define fr30 30
418#define fr31 31
419
420/* AltiVec Registers (VPRs) */
421
422#define vr0 0
423#define vr1 1
424#define vr2 2
425#define vr3 3
426#define vr4 4
427#define vr5 5
428#define vr6 6
429#define vr7 7
430#define vr8 8
431#define vr9 9
432#define vr10 10
433#define vr11 11
434#define vr12 12
435#define vr13 13
436#define vr14 14
437#define vr15 15
438#define vr16 16
439#define vr17 17
440#define vr18 18
441#define vr19 19
442#define vr20 20
443#define vr21 21
444#define vr22 22
445#define vr23 23
446#define vr24 24
447#define vr25 25
448#define vr26 26
449#define vr27 27
450#define vr28 28
451#define vr29 29
452#define vr30 30
453#define vr31 31
454
455/* SPE Registers (EVPRs) */
456
457#define evr0 0
458#define evr1 1
459#define evr2 2
460#define evr3 3
461#define evr4 4
462#define evr5 5
463#define evr6 6
464#define evr7 7
465#define evr8 8
466#define evr9 9
467#define evr10 10
468#define evr11 11
469#define evr12 12
470#define evr13 13
471#define evr14 14
472#define evr15 15
473#define evr16 16
474#define evr17 17
475#define evr18 18
476#define evr19 19
477#define evr20 20
478#define evr21 21
479#define evr22 22
480#define evr23 23
481#define evr24 24
482#define evr25 25
483#define evr26 26
484#define evr27 27
485#define evr28 28
486#define evr29 29
487#define evr30 30
488#define evr31 31
489
490/* some stab codes */
491#define N_FUN 36
492#define N_RSYM 64
493#define N_SLINE 68
494#define N_SO 100
495
496#define ASM_CONST(x) x
497#else
498 #define __ASM_CONST(x) x##UL
499 #define ASM_CONST(x) __ASM_CONST(x)
500#endif /* __ASSEMBLY__ */
501
502#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
new file mode 100644
index 000000000000..9592f533e058
--- /dev/null
+++ b/include/asm-powerpc/processor.h
@@ -0,0 +1,280 @@
1#ifndef _ASM_POWERPC_PROCESSOR_H
2#define _ASM_POWERPC_PROCESSOR_H
3
4/*
5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#include <linux/config.h>
14#include <asm/reg.h>
15
16#ifndef __ASSEMBLY__
17#include <linux/compiler.h>
18#include <asm/ptrace.h>
19#include <asm/types.h>
20#ifdef CONFIG_PPC64
21#include <asm/systemcfg.h>
22#endif
23
24#ifdef CONFIG_PPC32
25/* 32-bit platform types */
26/* We only need to define a new _MACH_xxx for machines which are part of
27 * a configuration which supports more than one type of different machine.
28 * This is currently limited to CONFIG_PPC_MULTIPLATFORM and CHRP/PReP/PMac.
29 * -- Tom
30 */
31#define _MACH_prep 0x00000001
32#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */
33#define _MACH_chrp 0x00000004 /* chrp machine */
34
35/* see residual.h for these */
36#define _PREP_Motorola 0x01 /* motorola prep */
37#define _PREP_Firm 0x02 /* firmworks prep */
38#define _PREP_IBM 0x00 /* ibm prep */
39#define _PREP_Bull 0x03 /* bull prep */
40
41/* these are arbitrary */
42#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
43#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
44#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
45
46#ifdef CONFIG_PPC_MULTIPLATFORM
47extern int _machine;
48
49/* what kind of prep workstation we are */
50extern int _prep_type;
51extern int _chrp_type;
52
53/*
54 * This is used to identify the board type from a given PReP board
55 * vendor. Board revision is also made available.
56 */
57extern unsigned char ucSystemType;
58extern unsigned char ucBoardRev;
59extern unsigned char ucBoardRevMaj, ucBoardRevMin;
60#else
61#define _machine 0
62#endif /* CONFIG_PPC_MULTIPLATFORM */
63#endif /* CONFIG_PPC32 */
64
65#ifdef CONFIG_PPC64
66/* Platforms supported by PPC64 */
67#define PLATFORM_PSERIES 0x0100
68#define PLATFORM_PSERIES_LPAR 0x0101
69#define PLATFORM_ISERIES_LPAR 0x0201
70#define PLATFORM_LPAR 0x0001
71#define PLATFORM_POWERMAC 0x0400
72#define PLATFORM_MAPLE 0x0500
73#define PLATFORM_BPA 0x1000
74
75/* Compatibility with drivers coming from PPC32 world */
76#define _machine (systemcfg->platform)
77#define _MACH_Pmac PLATFORM_POWERMAC
78#endif
79
80/*
81 * Default implementation of macro that returns current
82 * instruction pointer ("program counter").
83 */
84#define current_text_addr() ({ __label__ _l; _l: &&_l;})
85
86/* Macros for adjusting thread priority (hardware multi-threading) */
87#define HMT_very_low() asm volatile("or 31,31,31 # very low priority")
88#define HMT_low() asm volatile("or 1,1,1 # low priority")
89#define HMT_medium_low() asm volatile("or 6,6,6 # medium low priority")
90#define HMT_medium() asm volatile("or 2,2,2 # medium priority")
91#define HMT_medium_high() asm volatile("or 5,5,5 # medium high priority")
92#define HMT_high() asm volatile("or 3,3,3 # high priority")
93
94#ifdef __KERNEL__
95
96extern int have_of;
97
98struct task_struct;
99void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
100void release_thread(struct task_struct *);
101
102/* Prepare to copy thread state - unlazy all lazy status */
103extern void prepare_to_copy(struct task_struct *tsk);
104
105/* Create a new kernel thread. */
106extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
107
108/* Lazy FPU handling on uni-processor */
109extern struct task_struct *last_task_used_math;
110extern struct task_struct *last_task_used_altivec;
111extern struct task_struct *last_task_used_spe;
112
113#ifdef CONFIG_PPC32
114#define TASK_SIZE (CONFIG_TASK_SIZE)
115
116/* This decides where the kernel will search for a free chunk of vm
117 * space during mmap's.
118 */
119#define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
120#endif
121
122#ifdef CONFIG_PPC64
123/* 64-bit user address space is 44-bits (16TB user VM) */
124#define TASK_SIZE_USER64 (0x0000100000000000UL)
125
126/*
127 * 32-bit user address space is 4GB - 1 page
128 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
129 */
130#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
131
132#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
133 TASK_SIZE_USER32 : TASK_SIZE_USER64)
134
135/* This decides where the kernel will search for a free chunk of vm
136 * space during mmap's.
137 */
138#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
139#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
140
141#define TASK_UNMAPPED_BASE ((test_thread_flag(TIF_32BIT)) ? \
142 TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
143#endif
144
145typedef struct {
146 unsigned long seg;
147} mm_segment_t;
148
149struct thread_struct {
150 unsigned long ksp; /* Kernel stack pointer */
151#ifdef CONFIG_PPC64
152 unsigned long ksp_vsid;
153#endif
154 struct pt_regs *regs; /* Pointer to saved register state */
155 mm_segment_t fs; /* for get_fs() validation */
156#ifdef CONFIG_PPC32
157 void *pgdir; /* root of page-table tree */
158 signed long last_syscall;
159#endif
160#if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
161 unsigned long dbcr0; /* debug control register values */
162 unsigned long dbcr1;
163#endif
164 double fpr[32]; /* Complete floating point set */
165#ifdef CONFIG_PPC32
166 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
167#endif
168 unsigned long fpscr; /* Floating point status */
169 int fpexc_mode; /* floating-point exception mode */
170#ifdef CONFIG_PPC64
171 unsigned long start_tb; /* Start purr when proc switched in */
172 unsigned long accum_tb; /* Total accumilated purr for process */
173 unsigned long vdso_base; /* base of the vDSO library */
174#endif
175 unsigned long dabr; /* Data address breakpoint register */
176#ifdef CONFIG_ALTIVEC
177 /* Complete AltiVec register set */
178 vector128 vr[32] __attribute((aligned(16)));
179 /* AltiVec status */
180 vector128 vscr __attribute((aligned(16)));
181 unsigned long vrsave;
182 int used_vr; /* set if process has used altivec */
183#endif /* CONFIG_ALTIVEC */
184#ifdef CONFIG_SPE
185 unsigned long evr[32]; /* upper 32-bits of SPE regs */
186 u64 acc; /* Accumulator */
187 unsigned long spefscr; /* SPE & eFP status */
188 int used_spe; /* set if process has used spe */
189#endif /* CONFIG_SPE */
190};
191
192#define ARCH_MIN_TASKALIGN 16
193
194#define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
195
196
197#ifdef CONFIG_PPC32
198#define INIT_THREAD { \
199 .ksp = INIT_SP, \
200 .fs = KERNEL_DS, \
201 .pgdir = swapper_pg_dir, \
202 .fpexc_mode = MSR_FE0 | MSR_FE1, \
203}
204#else
205#define INIT_THREAD { \
206 .ksp = INIT_SP, \
207 .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
208 .fs = KERNEL_DS, \
209 .fpr = {0}, \
210 .fpscr = 0, \
211 .fpexc_mode = MSR_FE0|MSR_FE1, \
212}
213#endif
214
215/*
216 * Return saved PC of a blocked thread. For now, this is the "user" PC
217 */
218#define thread_saved_pc(tsk) \
219 ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
220
221unsigned long get_wchan(struct task_struct *p);
222
223#define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
224#define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
225
226/* Get/set floating-point exception mode */
227#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
228#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
229
230extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
231extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
232
233static inline unsigned int __unpack_fe01(unsigned long msr_bits)
234{
235 return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
236}
237
238static inline unsigned long __pack_fe01(unsigned int fpmode)
239{
240 return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
241}
242
243#ifdef CONFIG_PPC64
244#define cpu_relax() do { HMT_low(); HMT_medium(); barrier(); } while (0)
245#else
246#define cpu_relax() barrier()
247#endif
248
249/*
250 * Prefetch macros.
251 */
252#define ARCH_HAS_PREFETCH
253#define ARCH_HAS_PREFETCHW
254#define ARCH_HAS_SPINLOCK_PREFETCH
255
256static inline void prefetch(const void *x)
257{
258 if (unlikely(!x))
259 return;
260
261 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
262}
263
264static inline void prefetchw(const void *x)
265{
266 if (unlikely(!x))
267 return;
268
269 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
270}
271
272#define spin_lock_prefetch(x) prefetchw(x)
273
274#ifdef CONFIG_PPC64
275#define HAVE_ARCH_PICK_MMAP_LAYOUT
276#endif
277
278#endif /* __KERNEL__ */
279#endif /* __ASSEMBLY__ */
280#endif /* _ASM_POWERPC_PROCESSOR_H */
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
new file mode 100644
index 000000000000..8a21791c7cae
--- /dev/null
+++ b/include/asm-powerpc/prom.h
@@ -0,0 +1,219 @@
1#ifndef _POWERPC_PROM_H
2#define _POWERPC_PROM_H
3#ifdef __KERNEL__
4
5/*
6 * Definitions for talking to the Open Firmware PROM on
7 * Power Macintosh computers.
8 *
9 * Copyright (C) 1996-2005 Paul Mackerras.
10 *
11 * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18#include <linux/config.h>
19#include <linux/types.h>
20#include <linux/proc_fs.h>
21#include <asm/atomic.h>
22
23/* Definitions used by the flattened device tree */
24#define OF_DT_HEADER 0xd00dfeed /* marker */
25#define OF_DT_BEGIN_NODE 0x1 /* Start of node, full name */
26#define OF_DT_END_NODE 0x2 /* End node */
27#define OF_DT_PROP 0x3 /* Property: name off, size,
28 * content */
29#define OF_DT_NOP 0x4 /* nop */
30#define OF_DT_END 0x9
31
32#define OF_DT_VERSION 0x10
33
34/*
35 * This is what gets passed to the kernel by prom_init or kexec
36 *
37 * The dt struct contains the device tree structure, full pathes and
38 * property contents. The dt strings contain a separate block with just
39 * the strings for the property names, and is fully page aligned and
40 * self contained in a page, so that it can be kept around by the kernel,
41 * each property name appears only once in this page (cheap compression)
42 *
43 * the mem_rsvmap contains a map of reserved ranges of physical memory,
44 * passing it here instead of in the device-tree itself greatly simplifies
45 * the job of everybody. It's just a list of u64 pairs (base/size) that
46 * ends when size is 0
47 */
48struct boot_param_header
49{
50 u32 magic; /* magic word OF_DT_HEADER */
51 u32 totalsize; /* total size of DT block */
52 u32 off_dt_struct; /* offset to structure */
53 u32 off_dt_strings; /* offset to strings */
54 u32 off_mem_rsvmap; /* offset to memory reserve map */
55 u32 version; /* format version */
56 u32 last_comp_version; /* last compatible version */
57 /* version 2 fields below */
58 u32 boot_cpuid_phys; /* Physical CPU id we're booting on */
59 /* version 3 fields below */
60 u32 dt_strings_size; /* size of the DT strings block */
61};
62
63
64
65typedef u32 phandle;
66typedef u32 ihandle;
67
68struct address_range {
69 unsigned long space;
70 unsigned long address;
71 unsigned long size;
72};
73
74struct interrupt_info {
75 int line;
76 int sense; /* +ve/-ve logic, edge or level, etc. */
77};
78
79struct pci_address {
80 u32 a_hi;
81 u32 a_mid;
82 u32 a_lo;
83};
84
85struct isa_address {
86 u32 a_hi;
87 u32 a_lo;
88};
89
90struct isa_range {
91 struct isa_address isa_addr;
92 struct pci_address pci_addr;
93 unsigned int size;
94};
95
96struct reg_property {
97 unsigned long address;
98 unsigned long size;
99};
100
101struct reg_property32 {
102 unsigned int address;
103 unsigned int size;
104};
105
106struct reg_property64 {
107 unsigned long address;
108 unsigned long size;
109};
110
111struct property {
112 char *name;
113 int length;
114 unsigned char *value;
115 struct property *next;
116};
117
118struct device_node {
119 char *name;
120 char *type;
121 phandle node;
122 phandle linux_phandle;
123 int n_addrs;
124 struct address_range *addrs;
125 int n_intrs;
126 struct interrupt_info *intrs;
127 char *full_name;
128
129 struct property *properties;
130 struct device_node *parent;
131 struct device_node *child;
132 struct device_node *sibling;
133 struct device_node *next; /* next device of same type */
134 struct device_node *allnext; /* next in list of all nodes */
135 struct proc_dir_entry *pde; /* this node's proc directory */
136 struct kref kref;
137 unsigned long _flags;
138 void *data;
139};
140
141extern struct device_node *of_chosen;
142
143/* flag descriptions */
144#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */
145
146#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
147#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
148
149#define HAVE_ARCH_DEVTREE_FIXUPS
150
151static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de)
152{
153 dn->pde = de;
154}
155
156
157/* OBSOLETE: Old style node lookup */
158extern struct device_node *find_devices(const char *name);
159extern struct device_node *find_type_devices(const char *type);
160extern struct device_node *find_path_device(const char *path);
161extern struct device_node *find_compatible_devices(const char *type,
162 const char *compat);
163extern struct device_node *find_all_nodes(void);
164
165/* New style node lookup */
166extern struct device_node *of_find_node_by_name(struct device_node *from,
167 const char *name);
168extern struct device_node *of_find_node_by_type(struct device_node *from,
169 const char *type);
170extern struct device_node *of_find_compatible_node(struct device_node *from,
171 const char *type, const char *compat);
172extern struct device_node *of_find_node_by_path(const char *path);
173extern struct device_node *of_find_node_by_phandle(phandle handle);
174extern struct device_node *of_find_all_nodes(struct device_node *prev);
175extern struct device_node *of_get_parent(const struct device_node *node);
176extern struct device_node *of_get_next_child(const struct device_node *node,
177 struct device_node *prev);
178extern struct device_node *of_node_get(struct device_node *node);
179extern void of_node_put(struct device_node *node);
180
181/* For updating the device tree at runtime */
182extern void of_attach_node(struct device_node *);
183extern void of_detach_node(const struct device_node *);
184
185/* Other Prototypes */
186extern void finish_device_tree(void);
187extern void unflatten_device_tree(void);
188extern void early_init_devtree(void *);
189extern int device_is_compatible(struct device_node *device, const char *);
190extern int machine_is_compatible(const char *compat);
191extern unsigned char *get_property(struct device_node *node, const char *name,
192 int *lenp);
193extern void print_properties(struct device_node *node);
194extern int prom_n_addr_cells(struct device_node* np);
195extern int prom_n_size_cells(struct device_node* np);
196extern int prom_n_intr_cells(struct device_node* np);
197extern void prom_get_irq_senses(unsigned char *senses, int off, int max);
198extern void prom_add_property(struct device_node* np, struct property* prop);
199
200#ifdef CONFIG_PPC32
201/*
202 * PCI <-> OF matching functions
203 * (XXX should these be here?)
204 */
205struct pci_bus;
206struct pci_dev;
207extern int pci_device_from_OF_node(struct device_node *node,
208 u8* bus, u8* devfn);
209extern struct device_node* pci_busdev_to_OF_node(struct pci_bus *, int);
210extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
211extern void pci_create_OF_bus_map(void);
212#endif
213
214extern struct resource *request_OF_resource(struct device_node* node,
215 int index, const char* name_postfix);
216extern int release_OF_resource(struct device_node* node, int index);
217
218#endif /* __KERNEL__ */
219#endif /* _POWERPC_PROM_H */
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
new file mode 100644
index 000000000000..06a1f0f2db21
--- /dev/null
+++ b/include/asm-powerpc/reg.h
@@ -0,0 +1,611 @@
1/*
2 * Contains the definition of registers common to all PowerPC variants.
3 * If a register definition has been changed in a different PowerPC
4 * variant, we will case it in #ifndef XXX ... #endif, and have the
5 * number used in the Programming Environments Manual For 32-Bit
6 * Implementations of the PowerPC Architecture (a.k.a. Green Book) here.
7 */
8
9#ifndef _ASM_POWERPC_REG_H
10#define _ASM_POWERPC_REG_H
11#ifdef __KERNEL__
12
13#include <linux/stringify.h>
14#include <asm/cputable.h>
15
16/* Pickup Book E specific registers. */
17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18#include <asm/reg_booke.h>
19#endif
20
21#define MSR_SF_LG 63 /* Enable 64 bit mode */
22#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
23#define MSR_HV_LG 60 /* Hypervisor state */
24#define MSR_VEC_LG 25 /* Enable AltiVec */
25#define MSR_POW_LG 18 /* Enable Power Management */
26#define MSR_WE_LG 18 /* Wait State Enable */
27#define MSR_TGPR_LG 17 /* TLB Update registers in use */
28#define MSR_CE_LG 17 /* Critical Interrupt Enable */
29#define MSR_ILE_LG 16 /* Interrupt Little Endian */
30#define MSR_EE_LG 15 /* External Interrupt Enable */
31#define MSR_PR_LG 14 /* Problem State / Privilege Level */
32#define MSR_FP_LG 13 /* Floating Point enable */
33#define MSR_ME_LG 12 /* Machine Check Enable */
34#define MSR_FE0_LG 11 /* Floating Exception mode 0 */
35#define MSR_SE_LG 10 /* Single Step */
36#define MSR_BE_LG 9 /* Branch Trace */
37#define MSR_DE_LG 9 /* Debug Exception Enable */
38#define MSR_FE1_LG 8 /* Floating Exception mode 1 */
39#define MSR_IP_LG 6 /* Exception prefix 0x000/0xFFF */
40#define MSR_IR_LG 5 /* Instruction Relocate */
41#define MSR_DR_LG 4 /* Data Relocate */
42#define MSR_PE_LG 3 /* Protection Enable */
43#define MSR_PX_LG 2 /* Protection Exclusive Mode */
44#define MSR_PMM_LG 2 /* Performance monitor */
45#define MSR_RI_LG 1 /* Recoverable Exception */
46#define MSR_LE_LG 0 /* Little Endian */
47
48#ifdef __ASSEMBLY__
49#define __MASK(X) (1<<(X))
50#else
51#define __MASK(X) (1UL<<(X))
52#endif
53
54#define MSR_SF __MASK(MSR_SF_LG) /* Enable 64 bit mode */
55#define MSR_ISF __MASK(MSR_ISF_LG) /* Interrupt 64b mode valid on 630 */
56#define MSR_HV __MASK(MSR_HV_LG) /* Hypervisor state */
57#define MSR_VEC __MASK(MSR_VEC_LG) /* Enable AltiVec */
58#define MSR_POW __MASK(MSR_POW_LG) /* Enable Power Management */
59#define MSR_WE __MASK(MSR_WE_LG) /* Wait State Enable */
60#define MSR_TGPR __MASK(MSR_TGPR_LG) /* TLB Update registers in use */
61#define MSR_CE __MASK(MSR_CE_LG) /* Critical Interrupt Enable */
62#define MSR_ILE __MASK(MSR_ILE_LG) /* Interrupt Little Endian */
63#define MSR_EE __MASK(MSR_EE_LG) /* External Interrupt Enable */
64#define MSR_PR __MASK(MSR_PR_LG) /* Problem State / Privilege Level */
65#define MSR_FP __MASK(MSR_FP_LG) /* Floating Point enable */
66#define MSR_ME __MASK(MSR_ME_LG) /* Machine Check Enable */
67#define MSR_FE0 __MASK(MSR_FE0_LG) /* Floating Exception mode 0 */
68#define MSR_SE __MASK(MSR_SE_LG) /* Single Step */
69#define MSR_BE __MASK(MSR_BE_LG) /* Branch Trace */
70#define MSR_DE __MASK(MSR_DE_LG) /* Debug Exception Enable */
71#define MSR_FE1 __MASK(MSR_FE1_LG) /* Floating Exception mode 1 */
72#define MSR_IP __MASK(MSR_IP_LG) /* Exception prefix 0x000/0xFFF */
73#define MSR_IR __MASK(MSR_IR_LG) /* Instruction Relocate */
74#define MSR_DR __MASK(MSR_DR_LG) /* Data Relocate */
75#define MSR_PE __MASK(MSR_PE_LG) /* Protection Enable */
76#define MSR_PX __MASK(MSR_PX_LG) /* Protection Exclusive Mode */
77#ifndef MSR_PMM
78#define MSR_PMM __MASK(MSR_PMM_LG) /* Performance monitor */
79#endif
80#define MSR_RI __MASK(MSR_RI_LG) /* Recoverable Exception */
81#define MSR_LE __MASK(MSR_LE_LG) /* Little Endian */
82
83#ifdef CONFIG_PPC64
84#define MSR_ MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_ISF
85#define MSR_KERNEL MSR_ | MSR_SF | MSR_HV
86
87#define MSR_USER32 MSR_ | MSR_PR | MSR_EE
88#define MSR_USER64 MSR_USER32 | MSR_SF
89
90#else /* 32-bit */
91/* Default MSR for kernel mode. */
92#ifndef MSR_KERNEL /* reg_booke.h also defines this */
93#ifdef CONFIG_APUS_FAST_EXCEPT
94#define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR)
95#else
96#define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR)
97#endif
98#endif
99
100#define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE)
101#endif
102
103/* Floating Point Status and Control Register (FPSCR) Fields */
104#define FPSCR_FX 0x80000000 /* FPU exception summary */
105#define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
106#define FPSCR_VX 0x20000000 /* Invalid operation summary */
107#define FPSCR_OX 0x10000000 /* Overflow exception summary */
108#define FPSCR_UX 0x08000000 /* Underflow exception summary */
109#define FPSCR_ZX 0x04000000 /* Zero-divide exception summary */
110#define FPSCR_XX 0x02000000 /* Inexact exception summary */
111#define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
112#define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
113#define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
114#define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
115#define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
116#define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
117#define FPSCR_FR 0x00040000 /* Fraction rounded */
118#define FPSCR_FI 0x00020000 /* Fraction inexact */
119#define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
120#define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
121#define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
122#define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
123#define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
124#define FPSCR_VE 0x00000080 /* Invalid op exception enable */
125#define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
126#define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
127#define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
128#define FPSCR_XE 0x00000008 /* FP inexact exception enable */
129#define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
130#define FPSCR_RN 0x00000003 /* FPU rounding control */
131
132/* Special Purpose Registers (SPRNs)*/
133#define SPRN_CTR 0x009 /* Count Register */
134#define SPRN_CTRLF 0x088
135#define SPRN_CTRLT 0x098
136#define CTRL_RUNLATCH 0x1
137#define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
138#define DABR_TRANSLATION (1UL << 2)
139#define SPRN_DAR 0x013 /* Data Address Register */
140#define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
141#define DSISR_NOHPTE 0x40000000 /* no translation found */
142#define DSISR_PROTFAULT 0x08000000 /* protection fault */
143#define DSISR_ISSTORE 0x02000000 /* access was a store */
144#define DSISR_DABRMATCH 0x00400000 /* hit data breakpoint */
145#define DSISR_NOSEGMENT 0x00200000 /* STAB/SLB miss */
146#define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
147#define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
148#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
149#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
150#define SPRN_HIOR 0x137 /* 970 Hypervisor interrupt offset */
151#define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
152#define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
153#define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
154#define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
155#define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
156#define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
157#define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
158#define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
159#define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
160#define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
161#define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
162#define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
163#define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
164#define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
165#define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
166#define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
167
168#define SPRN_DEC 0x016 /* Decrement Register */
169#define SPRN_DER 0x095 /* Debug Enable Regsiter */
170#define DER_RSTE 0x40000000 /* Reset Interrupt */
171#define DER_CHSTPE 0x20000000 /* Check Stop */
172#define DER_MCIE 0x10000000 /* Machine Check Interrupt */
173#define DER_EXTIE 0x02000000 /* External Interrupt */
174#define DER_ALIE 0x01000000 /* Alignment Interrupt */
175#define DER_PRIE 0x00800000 /* Program Interrupt */
176#define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
177#define DER_DECIE 0x00200000 /* Decrementer Interrupt */
178#define DER_SYSIE 0x00040000 /* System Call Interrupt */
179#define DER_TRE 0x00020000 /* Trace Interrupt */
180#define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
181#define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
182#define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
183#define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
184#define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
185#define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
186#define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
187#define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
188#define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
189#define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
190#define SPRN_EAR 0x11A /* External Address Register */
191#define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
192#define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
193#define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
194#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
195#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
196#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
197#define HID0_SBCLK (1<<27)
198#define HID0_EICE (1<<26)
199#define HID0_TBEN (1<<26) /* Timebase enable - 745x */
200#define HID0_ECLK (1<<25)
201#define HID0_PAR (1<<24)
202#define HID0_STEN (1<<24) /* Software table search enable - 745x */
203#define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
204#define HID0_DOZE (1<<23)
205#define HID0_NAP (1<<22)
206#define HID0_SLEEP (1<<21)
207#define HID0_DPM (1<<20)
208#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
209#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
210#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
211#define HID0_ICE (1<<15) /* Instruction Cache Enable */
212#define HID0_DCE (1<<14) /* Data Cache Enable */
213#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
214#define HID0_DLOCK (1<<12) /* Data Cache Lock */
215#define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
216#define HID0_DCI (1<<10) /* Data Cache Invalidate */
217#define HID0_SPD (1<<9) /* Speculative disable */
218#define HID0_DAPUEN (1<<8) /* Debug APU enable */
219#define HID0_SGE (1<<7) /* Store Gathering Enable */
220#define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
221#define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
222#define HID0_LRSTK (1<<4) /* Link register stack - 745x */
223#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
224#define HID0_ABE (1<<3) /* Address Broadcast Enable */
225#define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
226#define HID0_BHTE (1<<2) /* Branch History Table Enable */
227#define HID0_BTCD (1<<1) /* Branch target cache disable */
228#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
229#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
230
231#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
232#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
233#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
234#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
235#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
236#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
237#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
238#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
239#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
240#define HID1_PS (1<<16) /* 750FX PLL selection */
241#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
242#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
243#define SPRN_HID4 0x3F4 /* 970 HID4 */
244#define SPRN_HID5 0x3F6 /* 970 HID5 */
245#define SPRN_HID6 0x3F9 /* BE HID 6 */
246#define HID6_LB (0x0F<<12) /* Concurrent Large Page Modes */
247#define HID6_DLP (1<<20) /* Disable all large page modes (4K only) */
248#define SPRN_TSCR 0x399 /* Thread switch control on BE */
249#define SPRN_TTR 0x39A /* Thread switch timeout on BE */
250#define TSCR_DEC_ENABLE 0x200000 /* Decrementer Interrupt */
251#define TSCR_EE_ENABLE 0x100000 /* External Interrupt */
252#define TSCR_EE_BOOST 0x080000 /* External Interrupt Boost */
253#define SPRN_TSC 0x3FD /* Thread switch control on others */
254#define SPRN_TST 0x3FC /* Thread switch timeout on others */
255#if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
256#define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
257#define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
258#endif
259#define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
260#define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
261#define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
262#define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
263#define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
264#define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
265#define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
266#define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
267#define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
268#define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
269#define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
270#define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
271#define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
272#define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
273#define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
274#define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
275#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
276#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
277#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
278#define ICTRL_EICE 0x08000000 /* enable icache parity errs */
279#define ICTRL_EDC 0x04000000 /* enable dcache parity errs */
280#define ICTRL_EICP 0x00000100 /* enable icache par. check */
281#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
282#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
283#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
284#define SPRN_L2CR2 0x3f8
285#define L2CR_L2E 0x80000000 /* L2 enable */
286#define L2CR_L2PE 0x40000000 /* L2 parity enable */
287#define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
288#define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
289#define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
290#define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
291#define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
292#define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
293#define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
294#define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
295#define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
296#define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
297#define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
298#define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
299#define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
300#define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
301#define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
302#define L2CR_L2DO 0x00400000 /* L2 data only */
303#define L2CR_L2I 0x00200000 /* L2 global invalidate */
304#define L2CR_L2CTL 0x00100000 /* L2 RAM control */
305#define L2CR_L2WT 0x00080000 /* L2 write-through */
306#define L2CR_L2TS 0x00040000 /* L2 test support */
307#define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
308#define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
309#define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
310#define L2CR_L2SL 0x00008000 /* L2 DLL slow */
311#define L2CR_L2DF 0x00004000 /* L2 differential clock */
312#define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
313#define L2CR_L2IP 0x00000001 /* L2 GI in progress */
314#define L2CR_L2IO_745x 0x00100000 /* L2 instr. only (745x) */
315#define L2CR_L2DO_745x 0x00010000 /* L2 data only (745x) */
316#define L2CR_L2REP_745x 0x00001000 /* L2 repl. algorithm (745x) */
317#define L2CR_L2HWF_745x 0x00000800 /* L2 hardware flush (745x) */
318#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter */
319#define L3CR_L3E 0x80000000 /* L3 enable */
320#define L3CR_L3PE 0x40000000 /* L3 data parity enable */
321#define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
322#define L3CR_L3SIZ 0x10000000 /* L3 size */
323#define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
324#define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
325#define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
326#define L3CR_L3IO 0x00400000 /* L3 instruction only */
327#define L3CR_L3SPO 0x00040000 /* L3 sample point override */
328#define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
329#define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
330#define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
331#define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
332#define L3CR_L3I 0x00000400 /* L3 global invalidate */
333#define L3CR_L3RT 0x00000300 /* L3 SRAM type */
334#define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
335#define L3CR_L3DO 0x00000040 /* L3 data only mode */
336#define L3CR_PMEN 0x00000004 /* L3 private memory enable */
337#define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
338
339#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
340#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
341#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
342#define SPRN_LDSTDB 0x3f4 /* */
343#define SPRN_LR 0x008 /* Link Register */
344#ifndef SPRN_PIR
345#define SPRN_PIR 0x3FF /* Processor Identification Register */
346#endif
347#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
348#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
349#define SPRN_PURR 0x135 /* Processor Utilization of Resources Reg */
350#define SPRN_PVR 0x11F /* Processor Version Register */
351#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
352#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
353#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
354#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
355#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
356#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
357#define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
358#define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
359#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */
360#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */
361#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */
362#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */
363#define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
364#define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
365#ifndef SPRN_SVR
366#define SPRN_SVR 0x11E /* System Version Register */
367#endif
368#define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
369/* these bits were defined in inverted endian sense originally, ugh, confusing */
370#define THRM1_TIN (1 << 31)
371#define THRM1_TIV (1 << 30)
372#define THRM1_THRES(x) ((x&0x7f)<<23)
373#define THRM3_SITV(x) ((x&0x3fff)<<1)
374#define THRM1_TID (1<<2)
375#define THRM1_TIE (1<<1)
376#define THRM1_V (1<<0)
377#define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
378#define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
379#define THRM3_E (1<<0)
380#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
381#define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
382#define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
383#define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
384#define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
385#define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
386#define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
387#define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
388#define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
389#define SPRN_XER 0x001 /* Fixed Point Exception Register */
390
391/* Performance monitor SPRs */
392#ifdef CONFIG_PPC64
393#define SPRN_MMCR0 795
394#define MMCR0_FC 0x80000000UL /* freeze counters */
395#define MMCR0_FCS 0x40000000UL /* freeze in supervisor state */
396#define MMCR0_KERNEL_DISABLE MMCR0_FCS
397#define MMCR0_FCP 0x20000000UL /* freeze in problem state */
398#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
399#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
400#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
401#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
402#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
403#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
404#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
405#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
406#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
407#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
408#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
409#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
410#define MMCR0_FCTA 0x00000004UL /* freeze counters in tags active mode */
411#define MMCR0_FCWAIT 0x00000002UL /* freeze counter in WAIT state */
412#define MMCR0_FCHV 0x00000001UL /* freeze conditions in hypervisor mode */
413#define SPRN_MMCR1 798
414#define SPRN_MMCRA 0x312
415#define MMCRA_SIHV 0x10000000UL /* state of MSR HV when SIAR set */
416#define MMCRA_SIPR 0x08000000UL /* state of MSR PR when SIAR set */
417#define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */
418#define SPRN_PMC1 787
419#define SPRN_PMC2 788
420#define SPRN_PMC3 789
421#define SPRN_PMC4 790
422#define SPRN_PMC5 791
423#define SPRN_PMC6 792
424#define SPRN_PMC7 793
425#define SPRN_PMC8 794
426#define SPRN_SIAR 780
427#define SPRN_SDAR 781
428
429#else /* 32-bit */
430#define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
431#define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
432#define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
433#define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
434#define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
435#define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
436
437/* Bit definitions for MMCR0 and PMC1 / PMC2. */
438#define MMCR0_PMC1_CYCLES (1 << 7)
439#define MMCR0_PMC1_ICACHEMISS (5 << 7)
440#define MMCR0_PMC1_DTLB (6 << 7)
441#define MMCR0_PMC2_DCACHEMISS 0x6
442#define MMCR0_PMC2_CYCLES 0x1
443#define MMCR0_PMC2_ITLB 0x7
444#define MMCR0_PMC2_LOADMISSTIME 0x5
445#define MMCR0_PMXE (1 << 26)
446#endif
447
448/* Processor Version Register (PVR) field extraction */
449
450#define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
451#define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
452
453#define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
454
455/*
456 * IBM has further subdivided the standard PowerPC 16-bit version and
457 * revision subfields of the PVR for the PowerPC 403s into the following:
458 */
459
460#define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
461#define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
462#define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
463#define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
464#define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
465#define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
466
467/* Processor Version Numbers */
468
469#define PVR_403GA 0x00200000
470#define PVR_403GB 0x00200100
471#define PVR_403GC 0x00200200
472#define PVR_403GCX 0x00201400
473#define PVR_405GP 0x40110000
474#define PVR_STB03XXX 0x40310000
475#define PVR_NP405H 0x41410000
476#define PVR_NP405L 0x41610000
477#define PVR_601 0x00010000
478#define PVR_602 0x00050000
479#define PVR_603 0x00030000
480#define PVR_603e 0x00060000
481#define PVR_603ev 0x00070000
482#define PVR_603r 0x00071000
483#define PVR_604 0x00040000
484#define PVR_604e 0x00090000
485#define PVR_604r 0x000A0000
486#define PVR_620 0x00140000
487#define PVR_740 0x00080000
488#define PVR_750 PVR_740
489#define PVR_740P 0x10080000
490#define PVR_750P PVR_740P
491#define PVR_7400 0x000C0000
492#define PVR_7410 0x800C0000
493#define PVR_7450 0x80000000
494#define PVR_8540 0x80200000
495#define PVR_8560 0x80200000
496/*
497 * For the 8xx processors, all of them report the same PVR family for
498 * the PowerPC core. The various versions of these processors must be
499 * differentiated by the version number in the Communication Processor
500 * Module (CPM).
501 */
502#define PVR_821 0x00500000
503#define PVR_823 PVR_821
504#define PVR_850 PVR_821
505#define PVR_860 PVR_821
506#define PVR_8240 0x00810100
507#define PVR_8245 0x80811014
508#define PVR_8260 PVR_8240
509
510/* 64-bit processors */
511/* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
512#define PV_NORTHSTAR 0x0033
513#define PV_PULSAR 0x0034
514#define PV_POWER4 0x0035
515#define PV_ICESTAR 0x0036
516#define PV_SSTAR 0x0037
517#define PV_POWER4p 0x0038
518#define PV_970 0x0039
519#define PV_POWER5 0x003A
520#define PV_POWER5p 0x003B
521#define PV_970FX 0x003C
522#define PV_630 0x0040
523#define PV_630p 0x0041
524#define PV_970MP 0x0044
525#define PV_BE 0x0070
526
527/*
528 * Number of entries in the SLB. If this ever changes we should handle
529 * it with a use a cpu feature fixup.
530 */
531#define SLB_NUM_ENTRIES 64
532
533/* Macros for setting and retrieving special purpose registers */
534#ifndef __ASSEMBLY__
535#define mfmsr() ({unsigned long rval; \
536 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
537#ifdef CONFIG_PPC64
538#define __mtmsrd(v, l) asm volatile("mtmsrd %0," __stringify(l) \
539 : : "r" (v))
540#define mtmsrd(v) __mtmsrd((v), 0)
541#else
542#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
543#endif
544
545#define mfspr(rn) ({unsigned long rval; \
546 asm volatile("mfspr %0," __stringify(rn) \
547 : "=r" (rval)); rval;})
548#define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
549
550#define mftb() ({unsigned long rval; \
551 asm volatile("mftb %0" : "=r" (rval)); rval;})
552#define mftbl() ({unsigned long rval; \
553 asm volatile("mftbl %0" : "=r" (rval)); rval;})
554
555#define mttbl(v) asm volatile("mttbl %0":: "r"(v))
556#define mttbu(v) asm volatile("mttbu %0":: "r"(v))
557
558#ifdef CONFIG_PPC32
559#define mfsrin(v) ({unsigned int rval; \
560 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
561 rval;})
562#endif
563
564#define proc_trap() asm volatile("trap")
565
566#ifdef CONFIG_PPC64
567static inline void ppc64_runlatch_on(void)
568{
569 unsigned long ctrl;
570
571 if (cpu_has_feature(CPU_FTR_CTRL)) {
572 ctrl = mfspr(SPRN_CTRLF);
573 ctrl |= CTRL_RUNLATCH;
574 mtspr(SPRN_CTRLT, ctrl);
575 }
576}
577
578static inline void ppc64_runlatch_off(void)
579{
580 unsigned long ctrl;
581
582 if (cpu_has_feature(CPU_FTR_CTRL)) {
583 ctrl = mfspr(SPRN_CTRLF);
584 ctrl &= ~CTRL_RUNLATCH;
585 mtspr(SPRN_CTRLT, ctrl);
586 }
587}
588
589static inline void set_tb(unsigned int upper, unsigned int lower)
590{
591 mttbl(0);
592 mttbu(upper);
593 mttbl(lower);
594}
595#endif
596
597#define __get_SP() ({unsigned long sp; \
598 asm volatile("mr %0,1": "=r" (sp)); sp;})
599
600#else /* __ASSEMBLY__ */
601
602#define RUNLATCH_ON(REG) \
603BEGIN_FTR_SECTION \
604 mfspr (REG),SPRN_CTRLF; \
605 ori (REG),(REG),CTRL_RUNLATCH; \
606 mtspr SPRN_CTRLT,(REG); \
607END_FTR_SECTION_IFSET(CPU_FTR_CTRL)
608
609#endif /* __ASSEMBLY__ */
610#endif /* __KERNEL__ */
611#endif /* _ASM_POWERPC_REG_H */
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
new file mode 100644
index 000000000000..2c050332471d
--- /dev/null
+++ b/include/asm-powerpc/rtas.h
@@ -0,0 +1,249 @@
1#ifndef _POWERPC_RTAS_H
2#define _POWERPC_RTAS_H
3
4#include <linux/spinlock.h>
5#include <asm/page.h>
6
7/*
8 * Definitions for talking to the RTAS on CHRP machines.
9 *
10 * Copyright (C) 2001 Peter Bergner
11 * Copyright (C) 2001 PPC 64 Team, IBM Corp
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#define RTAS_UNKNOWN_SERVICE (-1)
20#define RTAS_INSTANTIATE_MAX (1UL<<30) /* Don't instantiate rtas at/above this value */
21
22/* Buffer size for ppc_rtas system call. */
23#define RTAS_RMOBUF_MAX (64 * 1024)
24
25/* RTAS return status codes */
26#define RTAS_BUSY -2 /* RTAS Busy */
27#define RTAS_EXTENDED_DELAY_MIN 9900
28#define RTAS_EXTENDED_DELAY_MAX 9905
29
30/*
31 * In general to call RTAS use rtas_token("string") to lookup
32 * an RTAS token for the given string (e.g. "event-scan").
33 * To actually perform the call use
34 * ret = rtas_call(token, n_in, n_out, ...)
35 * Where n_in is the number of input parameters and
36 * n_out is the number of output parameters
37 *
38 * If the "string" is invalid on this system, RTAS_UNKNOWN_SERVICE
39 * will be returned as a token. rtas_call() does look for this
40 * token and error out gracefully so rtas_call(rtas_token("str"), ...)
41 * may be safely used for one-shot calls to RTAS.
42 *
43 */
44
45typedef u32 rtas_arg_t;
46
47struct rtas_args {
48 u32 token;
49 u32 nargs;
50 u32 nret;
51 rtas_arg_t args[16];
52 rtas_arg_t *rets; /* Pointer to return values in args[]. */
53};
54
55extern struct rtas_args rtas_stop_self_args;
56
57struct rtas_t {
58 unsigned long entry; /* physical address pointer */
59 unsigned long base; /* physical address pointer */
60 unsigned long size;
61 spinlock_t lock;
62 struct rtas_args args;
63 struct device_node *dev; /* virtual address pointer */
64};
65
66/* RTAS event classes */
67#define RTAS_INTERNAL_ERROR 0x80000000 /* set bit 0 */
68#define RTAS_EPOW_WARNING 0x40000000 /* set bit 1 */
69#define RTAS_POWERMGM_EVENTS 0x20000000 /* set bit 2 */
70#define RTAS_HOTPLUG_EVENTS 0x10000000 /* set bit 3 */
71#define RTAS_EVENT_SCAN_ALL_EVENTS 0xf0000000
72
73/* RTAS event severity */
74#define RTAS_SEVERITY_FATAL 0x5
75#define RTAS_SEVERITY_ERROR 0x4
76#define RTAS_SEVERITY_ERROR_SYNC 0x3
77#define RTAS_SEVERITY_WARNING 0x2
78#define RTAS_SEVERITY_EVENT 0x1
79#define RTAS_SEVERITY_NO_ERROR 0x0
80
81/* RTAS event disposition */
82#define RTAS_DISP_FULLY_RECOVERED 0x0
83#define RTAS_DISP_LIMITED_RECOVERY 0x1
84#define RTAS_DISP_NOT_RECOVERED 0x2
85
86/* RTAS event initiator */
87#define RTAS_INITIATOR_UNKNOWN 0x0
88#define RTAS_INITIATOR_CPU 0x1
89#define RTAS_INITIATOR_PCI 0x2
90#define RTAS_INITIATOR_ISA 0x3
91#define RTAS_INITIATOR_MEMORY 0x4
92#define RTAS_INITIATOR_POWERMGM 0x5
93
94/* RTAS event target */
95#define RTAS_TARGET_UNKNOWN 0x0
96#define RTAS_TARGET_CPU 0x1
97#define RTAS_TARGET_PCI 0x2
98#define RTAS_TARGET_ISA 0x3
99#define RTAS_TARGET_MEMORY 0x4
100#define RTAS_TARGET_POWERMGM 0x5
101
102/* RTAS event type */
103#define RTAS_TYPE_RETRY 0x01
104#define RTAS_TYPE_TCE_ERR 0x02
105#define RTAS_TYPE_INTERN_DEV_FAIL 0x03
106#define RTAS_TYPE_TIMEOUT 0x04
107#define RTAS_TYPE_DATA_PARITY 0x05
108#define RTAS_TYPE_ADDR_PARITY 0x06
109#define RTAS_TYPE_CACHE_PARITY 0x07
110#define RTAS_TYPE_ADDR_INVALID 0x08
111#define RTAS_TYPE_ECC_UNCORR 0x09
112#define RTAS_TYPE_ECC_CORR 0x0a
113#define RTAS_TYPE_EPOW 0x40
114#define RTAS_TYPE_PLATFORM 0xE0
115#define RTAS_TYPE_IO 0xE1
116#define RTAS_TYPE_INFO 0xE2
117#define RTAS_TYPE_DEALLOC 0xE3
118#define RTAS_TYPE_DUMP 0xE4
119/* I don't add PowerMGM events right now, this is a different topic */
120#define RTAS_TYPE_PMGM_POWER_SW_ON 0x60
121#define RTAS_TYPE_PMGM_POWER_SW_OFF 0x61
122#define RTAS_TYPE_PMGM_LID_OPEN 0x62
123#define RTAS_TYPE_PMGM_LID_CLOSE 0x63
124#define RTAS_TYPE_PMGM_SLEEP_BTN 0x64
125#define RTAS_TYPE_PMGM_WAKE_BTN 0x65
126#define RTAS_TYPE_PMGM_BATTERY_WARN 0x66
127#define RTAS_TYPE_PMGM_BATTERY_CRIT 0x67
128#define RTAS_TYPE_PMGM_SWITCH_TO_BAT 0x68
129#define RTAS_TYPE_PMGM_SWITCH_TO_AC 0x69
130#define RTAS_TYPE_PMGM_KBD_OR_MOUSE 0x6a
131#define RTAS_TYPE_PMGM_ENCLOS_OPEN 0x6b
132#define RTAS_TYPE_PMGM_ENCLOS_CLOSED 0x6c
133#define RTAS_TYPE_PMGM_RING_INDICATE 0x6d
134#define RTAS_TYPE_PMGM_LAN_ATTENTION 0x6e
135#define RTAS_TYPE_PMGM_TIME_ALARM 0x6f
136#define RTAS_TYPE_PMGM_CONFIG_CHANGE 0x70
137#define RTAS_TYPE_PMGM_SERVICE_PROC 0x71
138
139struct rtas_error_log {
140 unsigned long version:8; /* Architectural version */
141 unsigned long severity:3; /* Severity level of error */
142 unsigned long disposition:2; /* Degree of recovery */
143 unsigned long extended:1; /* extended log present? */
144 unsigned long /* reserved */ :2; /* Reserved for future use */
145 unsigned long initiator:4; /* Initiator of event */
146 unsigned long target:4; /* Target of failed operation */
147 unsigned long type:8; /* General event or error*/
148 unsigned long extended_log_length:32; /* length in bytes */
149 unsigned char buffer[1];
150};
151
152struct flash_block {
153 char *data;
154 unsigned long length;
155};
156
157/* This struct is very similar but not identical to
158 * that needed by the rtas flash update.
159 * All we need to do for rtas is rewrite num_blocks
160 * into a version/length and translate the pointers
161 * to absolute.
162 */
163#define FLASH_BLOCKS_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct flash_block))
164struct flash_block_list {
165 unsigned long num_blocks;
166 struct flash_block_list *next;
167 struct flash_block blocks[FLASH_BLOCKS_PER_NODE];
168};
169struct flash_block_list_header { /* just the header of flash_block_list */
170 unsigned long num_blocks;
171 struct flash_block_list *next;
172};
173extern struct flash_block_list_header rtas_firmware_flash_list;
174
175extern struct rtas_t rtas;
176
177extern void enter_rtas(unsigned long);
178extern int rtas_token(const char *service);
179extern int rtas_call(int token, int, int, int *, ...);
180extern void call_rtas_display_status(unsigned char);
181extern void rtas_restart(char *cmd);
182extern void rtas_power_off(void);
183extern void rtas_halt(void);
184extern void rtas_os_term(char *str);
185extern int rtas_get_sensor(int sensor, int index, int *state);
186extern int rtas_get_power_level(int powerdomain, int *level);
187extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
188extern int rtas_set_indicator(int indicator, int index, int new_value);
189extern void rtas_progress(char *s, unsigned short hex);
190extern void rtas_initialize(void);
191
192struct rtc_time;
193extern unsigned long rtas_get_boot_time(void);
194extern void rtas_get_rtc_time(struct rtc_time *rtc_time);
195extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
196
197/* Given an RTAS status code of 9900..9905 compute the hinted delay */
198unsigned int rtas_extended_busy_delay_time(int status);
199static inline int rtas_is_extended_busy(int status)
200{
201 return status >= 9900 && status <= 9909;
202}
203
204extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
205
206/* Error types logged. */
207#define ERR_FLAG_ALREADY_LOGGED 0x0
208#define ERR_FLAG_BOOT 0x1 /* log was pulled from NVRAM on boot */
209#define ERR_TYPE_RTAS_LOG 0x2 /* from rtas event-scan */
210#define ERR_TYPE_KERNEL_PANIC 0x4 /* from panic() */
211
212/* All the types and not flags */
213#define ERR_TYPE_MASK (ERR_TYPE_RTAS_LOG | ERR_TYPE_KERNEL_PANIC)
214
215#define RTAS_DEBUG KERN_DEBUG "RTAS: "
216
217#define RTAS_ERROR_LOG_MAX 2048
218
219/*
220 * Return the firmware-specified size of the error log buffer
221 * for all rtas calls that require an error buffer argument.
222 * This includes 'check-exception' and 'rtas-last-error'.
223 */
224extern int rtas_get_error_log_max(void);
225
226/* Event Scan Parameters */
227#define EVENT_SCAN_ALL_EVENTS 0xf0000000
228#define SURVEILLANCE_TOKEN 9000
229#define LOG_NUMBER 64 /* must be a power of two */
230#define LOG_NUMBER_MASK (LOG_NUMBER-1)
231
232/* Some RTAS ops require a data buffer and that buffer must be < 4G.
233 * Rather than having a memory allocator, just use this buffer
234 * (get the lock first), make the RTAS call. Copy the data instead
235 * of holding the buffer for long.
236 */
237
238#define RTAS_DATA_BUF_SIZE 4096
239extern spinlock_t rtas_data_buf_lock;
240extern char rtas_data_buf[RTAS_DATA_BUF_SIZE];
241
242extern void rtas_stop_self(void);
243
244/* RMO buffer reserved for user-space RTAS use */
245extern unsigned long rtas_rmo_buf;
246
247#define GLOBAL_INTERRUPT_QUEUE 9005
248
249#endif /* _POWERPC_RTAS_H */
diff --git a/include/asm-powerpc/rtc.h b/include/asm-powerpc/rtc.h
new file mode 100644
index 000000000000..f5802926b6c0
--- /dev/null
+++ b/include/asm-powerpc/rtc.h
@@ -0,0 +1,78 @@
1/*
2 * Real-time clock definitions and interfaces
3 *
4 * Author: Tom Rini <trini@mvista.com>
5 *
6 * 2002 (c) MontaVista, Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 *
11 * Based on:
12 * include/asm-m68k/rtc.h
13 *
14 * Copyright Richard Zidlicky
15 * implementation details for genrtc/q40rtc driver
16 *
17 * And the old drivers/macintosh/rtc.c which was heavily based on:
18 * Linux/SPARC Real Time Clock Driver
19 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
20 *
21 * With additional work by Paul Mackerras and Franz Sirl.
22 */
23
24#ifndef __ASM_POWERPC_RTC_H__
25#define __ASM_POWERPC_RTC_H__
26
27#ifdef __KERNEL__
28
29#include <linux/rtc.h>
30
31#include <asm/machdep.h>
32#include <asm/time.h>
33
34#define RTC_PIE 0x40 /* periodic interrupt enable */
35#define RTC_AIE 0x20 /* alarm interrupt enable */
36#define RTC_UIE 0x10 /* update-finished interrupt enable */
37
38/* some dummy definitions */
39#define RTC_BATT_BAD 0x100 /* battery bad */
40#define RTC_SQWE 0x08 /* enable square-wave output */
41#define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */
42#define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */
43#define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */
44
45static inline unsigned int get_rtc_time(struct rtc_time *time)
46{
47 if (ppc_md.get_rtc_time)
48 ppc_md.get_rtc_time(time);
49 return RTC_24H;
50}
51
52/* Set the current date and time in the real time clock. */
53static inline int set_rtc_time(struct rtc_time *time)
54{
55 if (ppc_md.set_rtc_time)
56 return ppc_md.set_rtc_time(time);
57 return -EINVAL;
58}
59
60static inline unsigned int get_rtc_ss(void)
61{
62 struct rtc_time h;
63
64 get_rtc_time(&h);
65 return h.tm_sec;
66}
67
68static inline int get_rtc_pll(struct rtc_pll_info *pll)
69{
70 return -EINVAL;
71}
72static inline int set_rtc_pll(struct rtc_pll_info *pll)
73{
74 return -EINVAL;
75}
76
77#endif /* __KERNEL__ */
78#endif /* __ASM_POWERPC_RTC_H__ */
diff --git a/include/asm-powerpc/rwsem.h b/include/asm-powerpc/rwsem.h
new file mode 100644
index 000000000000..0a5b83a3c949
--- /dev/null
+++ b/include/asm-powerpc/rwsem.h
@@ -0,0 +1,163 @@
1#ifndef _ASM_POWERPC_RWSEM_H
2#define _ASM_POWERPC_RWSEM_H
3
4#ifdef __KERNEL__
5
6/*
7 * include/asm-ppc64/rwsem.h: R/W semaphores for PPC using the stuff
8 * in lib/rwsem.c. Adapted largely from include/asm-i386/rwsem.h
9 * by Paul Mackerras <paulus@samba.org>.
10 */
11
12#include <linux/list.h>
13#include <linux/spinlock.h>
14#include <asm/atomic.h>
15#include <asm/system.h>
16
17/*
18 * the semaphore definition
19 */
20struct rw_semaphore {
21 /* XXX this should be able to be an atomic_t -- paulus */
22 signed int count;
23#define RWSEM_UNLOCKED_VALUE 0x00000000
24#define RWSEM_ACTIVE_BIAS 0x00000001
25#define RWSEM_ACTIVE_MASK 0x0000ffff
26#define RWSEM_WAITING_BIAS (-0x00010000)
27#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
28#define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
29 spinlock_t wait_lock;
30 struct list_head wait_list;
31#if RWSEM_DEBUG
32 int debug;
33#endif
34};
35
36/*
37 * initialisation
38 */
39#if RWSEM_DEBUG
40#define __RWSEM_DEBUG_INIT , 0
41#else
42#define __RWSEM_DEBUG_INIT /* */
43#endif
44
45#define __RWSEM_INITIALIZER(name) \
46 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, \
47 LIST_HEAD_INIT((name).wait_list) \
48 __RWSEM_DEBUG_INIT }
49
50#define DECLARE_RWSEM(name) \
51 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
52
53extern struct rw_semaphore *rwsem_down_read_failed(struct rw_semaphore *sem);
54extern struct rw_semaphore *rwsem_down_write_failed(struct rw_semaphore *sem);
55extern struct rw_semaphore *rwsem_wake(struct rw_semaphore *sem);
56extern struct rw_semaphore *rwsem_downgrade_wake(struct rw_semaphore *sem);
57
58static inline void init_rwsem(struct rw_semaphore *sem)
59{
60 sem->count = RWSEM_UNLOCKED_VALUE;
61 spin_lock_init(&sem->wait_lock);
62 INIT_LIST_HEAD(&sem->wait_list);
63#if RWSEM_DEBUG
64 sem->debug = 0;
65#endif
66}
67
68/*
69 * lock for reading
70 */
71static inline void __down_read(struct rw_semaphore *sem)
72{
73 if (unlikely(atomic_inc_return((atomic_t *)(&sem->count)) <= 0))
74 rwsem_down_read_failed(sem);
75}
76
77static inline int __down_read_trylock(struct rw_semaphore *sem)
78{
79 int tmp;
80
81 while ((tmp = sem->count) >= 0) {
82 if (tmp == cmpxchg(&sem->count, tmp,
83 tmp + RWSEM_ACTIVE_READ_BIAS)) {
84 return 1;
85 }
86 }
87 return 0;
88}
89
90/*
91 * lock for writing
92 */
93static inline void __down_write(struct rw_semaphore *sem)
94{
95 int tmp;
96
97 tmp = atomic_add_return(RWSEM_ACTIVE_WRITE_BIAS,
98 (atomic_t *)(&sem->count));
99 if (unlikely(tmp != RWSEM_ACTIVE_WRITE_BIAS))
100 rwsem_down_write_failed(sem);
101}
102
103static inline int __down_write_trylock(struct rw_semaphore *sem)
104{
105 int tmp;
106
107 tmp = cmpxchg(&sem->count, RWSEM_UNLOCKED_VALUE,
108 RWSEM_ACTIVE_WRITE_BIAS);
109 return tmp == RWSEM_UNLOCKED_VALUE;
110}
111
112/*
113 * unlock after reading
114 */
115static inline void __up_read(struct rw_semaphore *sem)
116{
117 int tmp;
118
119 tmp = atomic_dec_return((atomic_t *)(&sem->count));
120 if (unlikely(tmp < -1 && (tmp & RWSEM_ACTIVE_MASK) == 0))
121 rwsem_wake(sem);
122}
123
124/*
125 * unlock after writing
126 */
127static inline void __up_write(struct rw_semaphore *sem)
128{
129 if (unlikely(atomic_sub_return(RWSEM_ACTIVE_WRITE_BIAS,
130 (atomic_t *)(&sem->count)) < 0))
131 rwsem_wake(sem);
132}
133
134/*
135 * implement atomic add functionality
136 */
137static inline void rwsem_atomic_add(int delta, struct rw_semaphore *sem)
138{
139 atomic_add(delta, (atomic_t *)(&sem->count));
140}
141
142/*
143 * downgrade write lock to read lock
144 */
145static inline void __downgrade_write(struct rw_semaphore *sem)
146{
147 int tmp;
148
149 tmp = atomic_add_return(-RWSEM_WAITING_BIAS, (atomic_t *)(&sem->count));
150 if (tmp < 0)
151 rwsem_downgrade_wake(sem);
152}
153
154/*
155 * implement exchange and add functionality
156 */
157static inline int rwsem_atomic_update(int delta, struct rw_semaphore *sem)
158{
159 return atomic_add_return(delta, (atomic_t *)(&sem->count));
160}
161
162#endif /* __KERNEL__ */
163#endif /* _ASM_POWERPC_RWSEM_H */
diff --git a/include/asm-powerpc/seccomp.h b/include/asm-powerpc/seccomp.h
new file mode 100644
index 000000000000..1e1cfe12882b
--- /dev/null
+++ b/include/asm-powerpc/seccomp.h
@@ -0,0 +1,16 @@
1#ifndef _ASM_POWERPC_SECCOMP_H
2
3#include <linux/thread_info.h>
4#include <linux/unistd.h>
5
6#define __NR_seccomp_read __NR_read
7#define __NR_seccomp_write __NR_write
8#define __NR_seccomp_exit __NR_exit
9#define __NR_seccomp_sigreturn __NR_rt_sigreturn
10
11#define __NR_seccomp_read_32 __NR_read
12#define __NR_seccomp_write_32 __NR_write
13#define __NR_seccomp_exit_32 __NR_exit
14#define __NR_seccomp_sigreturn_32 __NR_sigreturn
15
16#endif /* _ASM_POWERPC_SECCOMP_H */
diff --git a/include/asm-powerpc/sections.h b/include/asm-powerpc/sections.h
new file mode 100644
index 000000000000..47be2ac2a925
--- /dev/null
+++ b/include/asm-powerpc/sections.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_POWERPC_SECTIONS_H
2#define _ASM_POWERPC_SECTIONS_H
3
4#include <asm-generic/sections.h>
5
6#ifdef __powerpc64__
7
8extern char _end[];
9
10static inline int in_kernel_text(unsigned long addr)
11{
12 if (addr >= (unsigned long)_stext && addr < (unsigned long)__init_end)
13 return 1;
14
15 return 0;
16}
17
18#endif
19
20#endif /* _ASM_POWERPC_SECTIONS_H */
diff --git a/include/asm-powerpc/semaphore.h b/include/asm-powerpc/semaphore.h
new file mode 100644
index 000000000000..fd42fe97158f
--- /dev/null
+++ b/include/asm-powerpc/semaphore.h
@@ -0,0 +1,98 @@
1#ifndef _ASM_POWERPC_SEMAPHORE_H
2#define _ASM_POWERPC_SEMAPHORE_H
3
4/*
5 * Remove spinlock-based RW semaphores; RW semaphore definitions are
6 * now in rwsem.h and we use the generic lib/rwsem.c implementation.
7 * Rework semaphores to use atomic_dec_if_positive.
8 * -- Paul Mackerras (paulus@samba.org)
9 */
10
11#ifdef __KERNEL__
12
13#include <asm/atomic.h>
14#include <asm/system.h>
15#include <linux/wait.h>
16#include <linux/rwsem.h>
17
18struct semaphore {
19 /*
20 * Note that any negative value of count is equivalent to 0,
21 * but additionally indicates that some process(es) might be
22 * sleeping on `wait'.
23 */
24 atomic_t count;
25 wait_queue_head_t wait;
26};
27
28#define __SEMAPHORE_INITIALIZER(name, n) \
29{ \
30 .count = ATOMIC_INIT(n), \
31 .wait = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait) \
32}
33
34#define __MUTEX_INITIALIZER(name) \
35 __SEMAPHORE_INITIALIZER(name, 1)
36
37#define __DECLARE_SEMAPHORE_GENERIC(name, count) \
38 struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
39
40#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name, 1)
41#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name, 0)
42
43static inline void sema_init (struct semaphore *sem, int val)
44{
45 atomic_set(&sem->count, val);
46 init_waitqueue_head(&sem->wait);
47}
48
49static inline void init_MUTEX (struct semaphore *sem)
50{
51 sema_init(sem, 1);
52}
53
54static inline void init_MUTEX_LOCKED (struct semaphore *sem)
55{
56 sema_init(sem, 0);
57}
58
59extern void __down(struct semaphore * sem);
60extern int __down_interruptible(struct semaphore * sem);
61extern void __up(struct semaphore * sem);
62
63static inline void down(struct semaphore * sem)
64{
65 might_sleep();
66
67 /*
68 * Try to get the semaphore, take the slow path if we fail.
69 */
70 if (unlikely(atomic_dec_return(&sem->count) < 0))
71 __down(sem);
72}
73
74static inline int down_interruptible(struct semaphore * sem)
75{
76 int ret = 0;
77
78 might_sleep();
79
80 if (unlikely(atomic_dec_return(&sem->count) < 0))
81 ret = __down_interruptible(sem);
82 return ret;
83}
84
85static inline int down_trylock(struct semaphore * sem)
86{
87 return atomic_dec_if_positive(&sem->count) < 0;
88}
89
90static inline void up(struct semaphore * sem)
91{
92 if (unlikely(atomic_inc_return(&sem->count) <= 0))
93 __up(sem);
94}
95
96#endif /* __KERNEL__ */
97
98#endif /* _ASM_POWERPC_SEMAPHORE_H */
diff --git a/include/asm-powerpc/smu.h b/include/asm-powerpc/smu.h
new file mode 100644
index 000000000000..dee8eefe47bc
--- /dev/null
+++ b/include/asm-powerpc/smu.h
@@ -0,0 +1,379 @@
1#ifndef _SMU_H
2#define _SMU_H
3
4/*
5 * Definitions for talking to the SMU chip in newer G5 PowerMacs
6 */
7
8#include <linux/config.h>
9#include <linux/list.h>
10
11/*
12 * Known SMU commands
13 *
14 * Most of what is below comes from looking at the Open Firmware driver,
15 * though this is still incomplete and could use better documentation here
16 * or there...
17 */
18
19
20/*
21 * Partition info commands
22 *
23 * I do not know what those are for at this point
24 */
25#define SMU_CMD_PARTITION_COMMAND 0x3e
26
27
28/*
29 * Fan control
30 *
31 * This is a "mux" for fan control commands, first byte is the
32 * "sub" command.
33 */
34#define SMU_CMD_FAN_COMMAND 0x4a
35
36
37/*
38 * Battery access
39 *
40 * Same command number as the PMU, could it be same syntax ?
41 */
42#define SMU_CMD_BATTERY_COMMAND 0x6f
43#define SMU_CMD_GET_BATTERY_INFO 0x00
44
45/*
46 * Real time clock control
47 *
48 * This is a "mux", first data byte contains the "sub" command.
49 * The "RTC" part of the SMU controls the date, time, powerup
50 * timer, but also a PRAM
51 *
52 * Dates are in BCD format on 7 bytes:
53 * [sec] [min] [hour] [weekday] [month day] [month] [year]
54 * with month being 1 based and year minus 100
55 */
56#define SMU_CMD_RTC_COMMAND 0x8e
57#define SMU_CMD_RTC_SET_PWRUP_TIMER 0x00 /* i: 7 bytes date */
58#define SMU_CMD_RTC_GET_PWRUP_TIMER 0x01 /* o: 7 bytes date */
59#define SMU_CMD_RTC_STOP_PWRUP_TIMER 0x02
60#define SMU_CMD_RTC_SET_PRAM_BYTE_ACC 0x20 /* i: 1 byte (address?) */
61#define SMU_CMD_RTC_SET_PRAM_AUTOINC 0x21 /* i: 1 byte (data?) */
62#define SMU_CMD_RTC_SET_PRAM_LO_BYTES 0x22 /* i: 10 bytes */
63#define SMU_CMD_RTC_SET_PRAM_HI_BYTES 0x23 /* i: 10 bytes */
64#define SMU_CMD_RTC_GET_PRAM_BYTE 0x28 /* i: 1 bytes (address?) */
65#define SMU_CMD_RTC_GET_PRAM_LO_BYTES 0x29 /* o: 10 bytes */
66#define SMU_CMD_RTC_GET_PRAM_HI_BYTES 0x2a /* o: 10 bytes */
67#define SMU_CMD_RTC_SET_DATETIME 0x80 /* i: 7 bytes date */
68#define SMU_CMD_RTC_GET_DATETIME 0x81 /* o: 7 bytes date */
69
70 /*
71 * i2c commands
72 *
73 * To issue an i2c command, first is to send a parameter block to the
74 * the SMU. This is a command of type 0x9a with 9 bytes of header
75 * eventually followed by data for a write:
76 *
77 * 0: bus number (from device-tree usually, SMU has lots of busses !)
78 * 1: transfer type/format (see below)
79 * 2: device address. For combined and combined4 type transfers, this
80 * is the "write" version of the address (bit 0x01 cleared)
81 * 3: subaddress length (0..3)
82 * 4: subaddress byte 0 (or only byte for subaddress length 1)
83 * 5: subaddress byte 1
84 * 6: subaddress byte 2
85 * 7: combined address (device address for combined mode data phase)
86 * 8: data length
87 *
88 * The transfer types are the same good old Apple ones it seems,
89 * that is:
90 * - 0x00: Simple transfer
91 * - 0x01: Subaddress transfer (addr write + data tx, no restart)
92 * - 0x02: Combined transfer (addr write + restart + data tx)
93 *
94 * This is then followed by actual data for a write.
95 *
96 * At this point, the OF driver seems to have a limitation on transfer
97 * sizes of 0xd bytes on reads and 0x5 bytes on writes. I do not know
98 * wether this is just an OF limit due to some temporary buffer size
99 * or if this is an SMU imposed limit. This driver has the same limitation
100 * for now as I use a 0x10 bytes temporary buffer as well
101 *
102 * Once that is completed, a response is expected from the SMU. This is
103 * obtained via a command of type 0x9a with a length of 1 byte containing
104 * 0 as the data byte. OF also fills the rest of the data buffer with 0xff's
105 * though I can't tell yet if this is actually necessary. Once this command
106 * is complete, at this point, all I can tell is what OF does. OF tests
107 * byte 0 of the reply:
108 * - on read, 0xfe or 0xfc : bus is busy, wait (see below) or nak ?
109 * - on read, 0x00 or 0x01 : reply is in buffer (after the byte 0)
110 * - on write, < 0 -> failure (immediate exit)
111 * - else, OF just exists (without error, weird)
112 *
113 * So on read, there is this wait-for-busy thing when getting a 0xfc or
114 * 0xfe result. OF does a loop of up to 64 retries, waiting 20ms and
115 * doing the above again until either the retries expire or the result
116 * is no longer 0xfe or 0xfc
117 *
118 * The Darwin I2C driver is less subtle though. On any non-success status
119 * from the response command, it waits 5ms and tries again up to 20 times,
120 * it doesn't differenciate between fatal errors or "busy" status.
121 *
122 * This driver provides an asynchronous paramblock based i2c command
123 * interface to be used either directly by low level code or by a higher
124 * level driver interfacing to the linux i2c layer. The current
125 * implementation of this relies on working timers & timer interrupts
126 * though, so be careful of calling context for now. This may be "fixed"
127 * in the future by adding a polling facility.
128 */
129#define SMU_CMD_I2C_COMMAND 0x9a
130 /* transfer types */
131#define SMU_I2C_TRANSFER_SIMPLE 0x00
132#define SMU_I2C_TRANSFER_STDSUB 0x01
133#define SMU_I2C_TRANSFER_COMBINED 0x02
134
135/*
136 * Power supply control
137 *
138 * The "sub" command is an ASCII string in the data, the
139 * data lenght is that of the string.
140 *
141 * The VSLEW command can be used to get or set the voltage slewing.
142 * - lenght 5 (only "VSLEW") : it returns "DONE" and 3 bytes of
143 * reply at data offset 6, 7 and 8.
144 * - lenght 8 ("VSLEWxyz") has 3 additional bytes appended, and is
145 * used to set the voltage slewing point. The SMU replies with "DONE"
146 * I yet have to figure out their exact meaning of those 3 bytes in
147 * both cases.
148 *
149 */
150#define SMU_CMD_POWER_COMMAND 0xaa
151#define SMU_CMD_POWER_RESTART "RESTART"
152#define SMU_CMD_POWER_SHUTDOWN "SHUTDOWN"
153#define SMU_CMD_POWER_VOLTAGE_SLEW "VSLEW"
154
155/* Misc commands
156 *
157 * This command seem to be a grab bag of various things
158 */
159#define SMU_CMD_MISC_df_COMMAND 0xdf
160#define SMU_CMD_MISC_df_SET_DISPLAY_LIT 0x02 /* i: 1 byte */
161#define SMU_CMD_MISC_df_NMI_OPTION 0x04
162
163/*
164 * Version info commands
165 *
166 * I haven't quite tried to figure out how these work
167 */
168#define SMU_CMD_VERSION_COMMAND 0xea
169
170
171/*
172 * Misc commands
173 *
174 * This command seem to be a grab bag of various things
175 */
176#define SMU_CMD_MISC_ee_COMMAND 0xee
177#define SMU_CMD_MISC_ee_GET_DATABLOCK_REC 0x02
178#define SMU_CMD_MISC_ee_LEDS_CTRL 0x04 /* i: 00 (00,01) [00] */
179#define SMU_CMD_MISC_ee_GET_DATA 0x05 /* i: 00 , o: ?? */
180
181
182
183/*
184 * - Kernel side interface -
185 */
186
187#ifdef __KERNEL__
188
189/*
190 * Asynchronous SMU commands
191 *
192 * Fill up this structure and submit it via smu_queue_command(),
193 * and get notified by the optional done() callback, or because
194 * status becomes != 1
195 */
196
197struct smu_cmd;
198
199struct smu_cmd
200{
201 /* public */
202 u8 cmd; /* command */
203 int data_len; /* data len */
204 int reply_len; /* reply len */
205 void *data_buf; /* data buffer */
206 void *reply_buf; /* reply buffer */
207 int status; /* command status */
208 void (*done)(struct smu_cmd *cmd, void *misc);
209 void *misc;
210
211 /* private */
212 struct list_head link;
213};
214
215/*
216 * Queues an SMU command, all fields have to be initialized
217 */
218extern int smu_queue_cmd(struct smu_cmd *cmd);
219
220/*
221 * Simple command wrapper. This structure embeds a small buffer
222 * to ease sending simple SMU commands from the stack
223 */
224struct smu_simple_cmd
225{
226 struct smu_cmd cmd;
227 u8 buffer[16];
228};
229
230/*
231 * Queues a simple command. All fields will be initialized by that
232 * function
233 */
234extern int smu_queue_simple(struct smu_simple_cmd *scmd, u8 command,
235 unsigned int data_len,
236 void (*done)(struct smu_cmd *cmd, void *misc),
237 void *misc,
238 ...);
239
240/*
241 * Completion helper. Pass it to smu_queue_simple or as 'done'
242 * member to smu_queue_cmd, it will call complete() on the struct
243 * completion passed in the "misc" argument
244 */
245extern void smu_done_complete(struct smu_cmd *cmd, void *misc);
246
247/*
248 * Synchronous helpers. Will spin-wait for completion of a command
249 */
250extern void smu_spinwait_cmd(struct smu_cmd *cmd);
251
252static inline void smu_spinwait_simple(struct smu_simple_cmd *scmd)
253{
254 smu_spinwait_cmd(&scmd->cmd);
255}
256
257/*
258 * Poll routine to call if blocked with irqs off
259 */
260extern void smu_poll(void);
261
262
263/*
264 * Init routine, presence check....
265 */
266extern int smu_init(void);
267extern int smu_present(void);
268struct of_device;
269extern struct of_device *smu_get_ofdev(void);
270
271
272/*
273 * Common command wrappers
274 */
275extern void smu_shutdown(void);
276extern void smu_restart(void);
277struct rtc_time;
278extern int smu_get_rtc_time(struct rtc_time *time, int spinwait);
279extern int smu_set_rtc_time(struct rtc_time *time, int spinwait);
280
281/*
282 * SMU command buffer absolute address, exported by pmac_setup,
283 * this is allocated very early during boot.
284 */
285extern unsigned long smu_cmdbuf_abs;
286
287
288/*
289 * Kenrel asynchronous i2c interface
290 */
291
292/* SMU i2c header, exactly matches i2c header on wire */
293struct smu_i2c_param
294{
295 u8 bus; /* SMU bus ID (from device tree) */
296 u8 type; /* i2c transfer type */
297 u8 devaddr; /* device address (includes direction) */
298 u8 sublen; /* subaddress length */
299 u8 subaddr[3]; /* subaddress */
300 u8 caddr; /* combined address, filled by SMU driver */
301 u8 datalen; /* length of transfer */
302 u8 data[7]; /* data */
303};
304
305#define SMU_I2C_READ_MAX 0x0d
306#define SMU_I2C_WRITE_MAX 0x05
307
308struct smu_i2c_cmd
309{
310 /* public */
311 struct smu_i2c_param info;
312 void (*done)(struct smu_i2c_cmd *cmd, void *misc);
313 void *misc;
314 int status; /* 1 = pending, 0 = ok, <0 = fail */
315
316 /* private */
317 struct smu_cmd scmd;
318 int read;
319 int stage;
320 int retries;
321 u8 pdata[0x10];
322 struct list_head link;
323};
324
325/*
326 * Call this to queue an i2c command to the SMU. You must fill info,
327 * including info.data for a write, done and misc.
328 * For now, no polling interface is provided so you have to use completion
329 * callback.
330 */
331extern int smu_queue_i2c(struct smu_i2c_cmd *cmd);
332
333
334#endif /* __KERNEL__ */
335
336/*
337 * - Userland interface -
338 */
339
340/*
341 * A given instance of the device can be configured for 2 different
342 * things at the moment:
343 *
344 * - sending SMU commands (default at open() time)
345 * - receiving SMU events (not yet implemented)
346 *
347 * Commands are written with write() of a command block. They can be
348 * "driver" commands (for example to switch to event reception mode)
349 * or real SMU commands. They are made of a header followed by command
350 * data if any.
351 *
352 * For SMU commands (not for driver commands), you can then read() back
353 * a reply. The reader will be blocked or not depending on how the device
354 * file is opened. poll() isn't implemented yet. The reply will consist
355 * of a header as well, followed by the reply data if any. You should
356 * always provide a buffer large enough for the maximum reply data, I
357 * recommand one page.
358 *
359 * It is illegal to send SMU commands through a file descriptor configured
360 * for events reception
361 *
362 */
363struct smu_user_cmd_hdr
364{
365 __u32 cmdtype;
366#define SMU_CMDTYPE_SMU 0 /* SMU command */
367#define SMU_CMDTYPE_WANTS_EVENTS 1 /* switch fd to events mode */
368
369 __u8 cmd; /* SMU command byte */
370 __u32 data_len; /* Lenght of data following */
371};
372
373struct smu_user_reply_hdr
374{
375 __u32 status; /* Command status */
376 __u32 reply_len; /* Lenght of data follwing */
377};
378
379#endif /* _SMU_H */
diff --git a/include/asm-powerpc/spinlock_types.h b/include/asm-powerpc/spinlock_types.h
new file mode 100644
index 000000000000..74236c9f05b1
--- /dev/null
+++ b/include/asm-powerpc/spinlock_types.h
@@ -0,0 +1,20 @@
1#ifndef _ASM_POWERPC_SPINLOCK_TYPES_H
2#define _ASM_POWERPC_SPINLOCK_TYPES_H
3
4#ifndef __LINUX_SPINLOCK_TYPES_H
5# error "please don't include this file directly"
6#endif
7
8typedef struct {
9 volatile unsigned int slock;
10} raw_spinlock_t;
11
12#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
13
14typedef struct {
15 volatile signed int lock;
16} raw_rwlock_t;
17
18#define __RAW_RW_LOCK_UNLOCKED { 0 }
19
20#endif
diff --git a/include/asm-powerpc/statfs.h b/include/asm-powerpc/statfs.h
new file mode 100644
index 000000000000..67024026c10d
--- /dev/null
+++ b/include/asm-powerpc/statfs.h
@@ -0,0 +1,60 @@
1#ifndef _ASM_POWERPC_STATFS_H
2#define _ASM_POWERPC_STATFS_H
3
4/* For ppc32 we just use the generic definitions, not so simple on ppc64 */
5
6#ifndef __powerpc64__
7#include <asm-generic/statfs.h>
8#else
9
10#ifndef __KERNEL_STRICT_NAMES
11#include <linux/types.h>
12typedef __kernel_fsid_t fsid_t;
13#endif
14
15/*
16 * We're already 64-bit, so duplicate the definition
17 */
18struct statfs {
19 long f_type;
20 long f_bsize;
21 long f_blocks;
22 long f_bfree;
23 long f_bavail;
24 long f_files;
25 long f_ffree;
26 __kernel_fsid_t f_fsid;
27 long f_namelen;
28 long f_frsize;
29 long f_spare[5];
30};
31
32struct statfs64 {
33 long f_type;
34 long f_bsize;
35 long f_blocks;
36 long f_bfree;
37 long f_bavail;
38 long f_files;
39 long f_ffree;
40 __kernel_fsid_t f_fsid;
41 long f_namelen;
42 long f_frsize;
43 long f_spare[5];
44};
45
46struct compat_statfs64 {
47 __u32 f_type;
48 __u32 f_bsize;
49 __u64 f_blocks;
50 __u64 f_bfree;
51 __u64 f_bavail;
52 __u64 f_files;
53 __u64 f_ffree;
54 __kernel_fsid_t f_fsid;
55 __u32 f_namelen;
56 __u32 f_frsize;
57 __u32 f_spare[5];
58};
59#endif /* ! __powerpc64__ */
60#endif
diff --git a/include/asm-powerpc/synch.h b/include/asm-powerpc/synch.h
new file mode 100644
index 000000000000..4660c0394a77
--- /dev/null
+++ b/include/asm-powerpc/synch.h
@@ -0,0 +1,51 @@
1#ifndef _ASM_POWERPC_SYNCH_H
2#define _ASM_POWERPC_SYNCH_H
3
4#include <linux/config.h>
5
6#ifdef __powerpc64__
7#define __SUBARCH_HAS_LWSYNC
8#endif
9
10#ifdef __SUBARCH_HAS_LWSYNC
11# define LWSYNC lwsync
12#else
13# define LWSYNC sync
14#endif
15
16
17/*
18 * Arguably the bitops and *xchg operations don't imply any memory barrier
19 * or SMP ordering, but in fact a lot of drivers expect them to imply
20 * both, since they do on x86 cpus.
21 */
22#ifdef CONFIG_SMP
23#define EIEIO_ON_SMP "eieio\n"
24#define ISYNC_ON_SMP "\n\tisync"
25#define SYNC_ON_SMP __stringify(LWSYNC) "\n"
26#else
27#define EIEIO_ON_SMP
28#define ISYNC_ON_SMP
29#define SYNC_ON_SMP
30#endif
31
32static inline void eieio(void)
33{
34 __asm__ __volatile__ ("eieio" : : : "memory");
35}
36
37static inline void isync(void)
38{
39 __asm__ __volatile__ ("isync" : : : "memory");
40}
41
42#ifdef CONFIG_SMP
43#define eieio_on_smp() eieio()
44#define isync_on_smp() isync()
45#else
46#define eieio_on_smp() __asm__ __volatile__("": : :"memory")
47#define isync_on_smp() __asm__ __volatile__("": : :"memory")
48#endif
49
50#endif /* _ASM_POWERPC_SYNCH_H */
51
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
new file mode 100644
index 000000000000..d60c8c928922
--- /dev/null
+++ b/include/asm-powerpc/system.h
@@ -0,0 +1,362 @@
1/*
2 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
3 */
4#ifndef _ASM_POWERPC_SYSTEM_H
5#define _ASM_POWERPC_SYSTEM_H
6
7#include <linux/config.h>
8#include <linux/kernel.h>
9
10#include <asm/hw_irq.h>
11#include <asm/ppc_asm.h>
12#include <asm/atomic.h>
13
14/*
15 * Memory barrier.
16 * The sync instruction guarantees that all memory accesses initiated
17 * by this processor have been performed (with respect to all other
18 * mechanisms that access memory). The eieio instruction is a barrier
19 * providing an ordering (separately) for (a) cacheable stores and (b)
20 * loads and stores to non-cacheable memory (e.g. I/O devices).
21 *
22 * mb() prevents loads and stores being reordered across this point.
23 * rmb() prevents loads being reordered across this point.
24 * wmb() prevents stores being reordered across this point.
25 * read_barrier_depends() prevents data-dependent loads being reordered
26 * across this point (nop on PPC).
27 *
28 * We have to use the sync instructions for mb(), since lwsync doesn't
29 * order loads with respect to previous stores. Lwsync is fine for
30 * rmb(), though. Note that lwsync is interpreted as sync by
31 * 32-bit and older 64-bit CPUs.
32 *
33 * For wmb(), we use sync since wmb is used in drivers to order
34 * stores to system memory with respect to writes to the device.
35 * However, smp_wmb() can be a lighter-weight eieio barrier on
36 * SMP since it is only used to order updates to system memory.
37 */
38#define mb() __asm__ __volatile__ ("sync" : : : "memory")
39#define rmb() __asm__ __volatile__ ("lwsync" : : : "memory")
40#define wmb() __asm__ __volatile__ ("sync" : : : "memory")
41#define read_barrier_depends() do { } while(0)
42
43#define set_mb(var, value) do { var = value; mb(); } while (0)
44#define set_wmb(var, value) do { var = value; wmb(); } while (0)
45
46#ifdef CONFIG_SMP
47#define smp_mb() mb()
48#define smp_rmb() rmb()
49#define smp_wmb() __asm__ __volatile__ ("eieio" : : : "memory")
50#define smp_read_barrier_depends() read_barrier_depends()
51#else
52#define smp_mb() barrier()
53#define smp_rmb() barrier()
54#define smp_wmb() barrier()
55#define smp_read_barrier_depends() do { } while(0)
56#endif /* CONFIG_SMP */
57
58#ifdef __KERNEL__
59struct task_struct;
60struct pt_regs;
61
62#ifdef CONFIG_DEBUGGER
63
64extern int (*__debugger)(struct pt_regs *regs);
65extern int (*__debugger_ipi)(struct pt_regs *regs);
66extern int (*__debugger_bpt)(struct pt_regs *regs);
67extern int (*__debugger_sstep)(struct pt_regs *regs);
68extern int (*__debugger_iabr_match)(struct pt_regs *regs);
69extern int (*__debugger_dabr_match)(struct pt_regs *regs);
70extern int (*__debugger_fault_handler)(struct pt_regs *regs);
71
72#define DEBUGGER_BOILERPLATE(__NAME) \
73static inline int __NAME(struct pt_regs *regs) \
74{ \
75 if (unlikely(__ ## __NAME)) \
76 return __ ## __NAME(regs); \
77 return 0; \
78}
79
80DEBUGGER_BOILERPLATE(debugger)
81DEBUGGER_BOILERPLATE(debugger_ipi)
82DEBUGGER_BOILERPLATE(debugger_bpt)
83DEBUGGER_BOILERPLATE(debugger_sstep)
84DEBUGGER_BOILERPLATE(debugger_iabr_match)
85DEBUGGER_BOILERPLATE(debugger_dabr_match)
86DEBUGGER_BOILERPLATE(debugger_fault_handler)
87
88#ifdef CONFIG_XMON
89extern void xmon_init(int enable);
90#endif
91
92#else
93static inline int debugger(struct pt_regs *regs) { return 0; }
94static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
95static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
96static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
97static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
98static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
99static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
100#endif
101
102extern int set_dabr(unsigned long dabr);
103extern void print_backtrace(unsigned long *);
104extern void show_regs(struct pt_regs * regs);
105extern void flush_instruction_cache(void);
106extern void hard_reset_now(void);
107extern void poweroff_now(void);
108
109#ifdef CONFIG_6xx
110extern long _get_L2CR(void);
111extern long _get_L3CR(void);
112extern void _set_L2CR(unsigned long);
113extern void _set_L3CR(unsigned long);
114#else
115#define _get_L2CR() 0L
116#define _get_L3CR() 0L
117#define _set_L2CR(val) do { } while(0)
118#define _set_L3CR(val) do { } while(0)
119#endif
120
121extern void via_cuda_init(void);
122extern void read_rtc_time(void);
123extern void pmac_find_display(void);
124extern void giveup_fpu(struct task_struct *);
125extern void disable_kernel_fp(void);
126extern void enable_kernel_fp(void);
127extern void flush_fp_to_thread(struct task_struct *);
128extern void enable_kernel_altivec(void);
129extern void giveup_altivec(struct task_struct *);
130extern void load_up_altivec(struct task_struct *);
131extern int emulate_altivec(struct pt_regs *);
132extern void giveup_spe(struct task_struct *);
133extern void load_up_spe(struct task_struct *);
134extern int fix_alignment(struct pt_regs *);
135extern void cvt_fd(float *from, double *to, unsigned long *fpscr);
136extern void cvt_df(double *from, float *to, unsigned long *fpscr);
137
138#ifdef CONFIG_ALTIVEC
139extern void flush_altivec_to_thread(struct task_struct *);
140#else
141static inline void flush_altivec_to_thread(struct task_struct *t)
142{
143}
144#endif
145
146#ifdef CONFIG_SPE
147extern void flush_spe_to_thread(struct task_struct *);
148#else
149static inline void flush_spe_to_thread(struct task_struct *t)
150{
151}
152#endif
153
154extern int call_rtas(const char *, int, int, unsigned long *, ...);
155extern void cacheable_memzero(void *p, unsigned int nb);
156extern void *cacheable_memcpy(void *, const void *, unsigned int);
157extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
158extern void bad_page_fault(struct pt_regs *, unsigned long, int);
159extern int die(const char *, struct pt_regs *, long);
160extern void _exception(int, struct pt_regs *, int, unsigned long);
161#ifdef CONFIG_BOOKE_WDT
162extern u32 booke_wdt_enabled;
163extern u32 booke_wdt_period;
164#endif /* CONFIG_BOOKE_WDT */
165
166/* EBCDIC -> ASCII conversion for [0-9A-Z] on iSeries */
167extern unsigned char e2a(unsigned char);
168
169struct device_node;
170extern void note_scsi_host(struct device_node *, void *);
171
172extern struct task_struct *__switch_to(struct task_struct *,
173 struct task_struct *);
174#define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
175
176struct thread_struct;
177extern struct task_struct *_switch(struct thread_struct *prev,
178 struct thread_struct *next);
179
180extern unsigned int rtas_data;
181extern int mem_init_done; /* set on boot once kmalloc can be called */
182
183extern int powersave_nap; /* set if nap mode can be used in idle loop */
184
185/*
186 * Atomic exchange
187 *
188 * Changes the memory location '*ptr' to be val and returns
189 * the previous value stored there.
190 */
191static __inline__ unsigned long
192__xchg_u32(volatile void *p, unsigned long val)
193{
194 unsigned long prev;
195
196 __asm__ __volatile__(
197 EIEIO_ON_SMP
198"1: lwarx %0,0,%2 \n"
199 PPC405_ERR77(0,%2)
200" stwcx. %3,0,%2 \n\
201 bne- 1b"
202 ISYNC_ON_SMP
203 : "=&r" (prev), "=m" (*(volatile unsigned int *)p)
204 : "r" (p), "r" (val), "m" (*(volatile unsigned int *)p)
205 : "cc", "memory");
206
207 return prev;
208}
209
210#ifdef CONFIG_PPC64
211static __inline__ unsigned long
212__xchg_u64(volatile void *p, unsigned long val)
213{
214 unsigned long prev;
215
216 __asm__ __volatile__(
217 EIEIO_ON_SMP
218"1: ldarx %0,0,%2 \n"
219 PPC405_ERR77(0,%2)
220" stdcx. %3,0,%2 \n\
221 bne- 1b"
222 ISYNC_ON_SMP
223 : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
224 : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
225 : "cc", "memory");
226
227 return prev;
228}
229#endif
230
231/*
232 * This function doesn't exist, so you'll get a linker error
233 * if something tries to do an invalid xchg().
234 */
235extern void __xchg_called_with_bad_pointer(void);
236
237static __inline__ unsigned long
238__xchg(volatile void *ptr, unsigned long x, unsigned int size)
239{
240 switch (size) {
241 case 4:
242 return __xchg_u32(ptr, x);
243#ifdef CONFIG_PPC64
244 case 8:
245 return __xchg_u64(ptr, x);
246#endif
247 }
248 __xchg_called_with_bad_pointer();
249 return x;
250}
251
252#define xchg(ptr,x) \
253 ({ \
254 __typeof__(*(ptr)) _x_ = (x); \
255 (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
256 })
257
258#define tas(ptr) (xchg((ptr),1))
259
260/*
261 * Compare and exchange - if *p == old, set it to new,
262 * and return the old value of *p.
263 */
264#define __HAVE_ARCH_CMPXCHG 1
265
266static __inline__ unsigned long
267__cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
268{
269 unsigned int prev;
270
271 __asm__ __volatile__ (
272 EIEIO_ON_SMP
273"1: lwarx %0,0,%2 # __cmpxchg_u32\n\
274 cmpw 0,%0,%3\n\
275 bne- 2f\n"
276 PPC405_ERR77(0,%2)
277" stwcx. %4,0,%2\n\
278 bne- 1b"
279 ISYNC_ON_SMP
280 "\n\
2812:"
282 : "=&r" (prev), "=m" (*p)
283 : "r" (p), "r" (old), "r" (new), "m" (*p)
284 : "cc", "memory");
285
286 return prev;
287}
288
289#ifdef CONFIG_PPC64
290static __inline__ unsigned long
291__cmpxchg_u64(volatile long *p, unsigned long old, unsigned long new)
292{
293 unsigned long prev;
294
295 __asm__ __volatile__ (
296 EIEIO_ON_SMP
297"1: ldarx %0,0,%2 # __cmpxchg_u64\n\
298 cmpd 0,%0,%3\n\
299 bne- 2f\n\
300 stdcx. %4,0,%2\n\
301 bne- 1b"
302 ISYNC_ON_SMP
303 "\n\
3042:"
305 : "=&r" (prev), "=m" (*p)
306 : "r" (p), "r" (old), "r" (new), "m" (*p)
307 : "cc", "memory");
308
309 return prev;
310}
311#endif
312
313/* This function doesn't exist, so you'll get a linker error
314 if something tries to do an invalid cmpxchg(). */
315extern void __cmpxchg_called_with_bad_pointer(void);
316
317static __inline__ unsigned long
318__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
319 unsigned int size)
320{
321 switch (size) {
322 case 4:
323 return __cmpxchg_u32(ptr, old, new);
324#ifdef CONFIG_PPC64
325 case 8:
326 return __cmpxchg_u64(ptr, old, new);
327#endif
328 }
329 __cmpxchg_called_with_bad_pointer();
330 return old;
331}
332
333#define cmpxchg(ptr,o,n) \
334 ({ \
335 __typeof__(*(ptr)) _o_ = (o); \
336 __typeof__(*(ptr)) _n_ = (n); \
337 (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
338 (unsigned long)_n_, sizeof(*(ptr))); \
339 })
340
341#ifdef CONFIG_PPC64
342/*
343 * We handle most unaligned accesses in hardware. On the other hand
344 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
345 * powers of 2 writes until it reaches sufficient alignment).
346 *
347 * Based on this we disable the IP header alignment in network drivers.
348 */
349#define NET_IP_ALIGN 0
350#endif
351
352#define arch_align_stack(x) (x)
353
354/* Used in very early kernel initialization. */
355extern unsigned long reloc_offset(void);
356extern unsigned long add_reloc_offset(unsigned long);
357extern void reloc_got2(unsigned long);
358
359#define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
360
361#endif /* __KERNEL__ */
362#endif /* _ASM_POWERPC_SYSTEM_H */
diff --git a/include/asm-powerpc/thread_info.h b/include/asm-powerpc/thread_info.h
new file mode 100644
index 000000000000..0b4c24551c21
--- /dev/null
+++ b/include/asm-powerpc/thread_info.h
@@ -0,0 +1,135 @@
1/* thread_info.h: PowerPC low-level thread information
2 * adapted from the i386 version by Paul Mackerras
3 *
4 * Copyright (C) 2002 David Howells (dhowells@redhat.com)
5 * - Incorporating suggestions made by Linus Torvalds and Dave Miller
6 */
7
8#ifndef _ASM_POWERPC_THREAD_INFO_H
9#define _ASM_POWERPC_THREAD_INFO_H
10
11#ifdef __KERNEL__
12
13/* We have 8k stacks on ppc32 and 16k on ppc64 */
14
15#ifdef CONFIG_PPC64
16#define THREAD_SHIFT 14
17#else
18#define THREAD_SHIFT 13
19#endif
20
21#define THREAD_SIZE (1 << THREAD_SHIFT)
22
23#ifndef __ASSEMBLY__
24#include <linux/config.h>
25#include <linux/cache.h>
26#include <asm/processor.h>
27#include <asm/page.h>
28#include <linux/stringify.h>
29
30/*
31 * low level task data.
32 */
33struct thread_info {
34 struct task_struct *task; /* main task structure */
35 struct exec_domain *exec_domain; /* execution domain */
36 int cpu; /* cpu we're on */
37 int preempt_count; /* 0 => preemptable,
38 <0 => BUG */
39 struct restart_block restart_block;
40 /* set by force_successful_syscall_return */
41 unsigned char syscall_noerror;
42 /* low level flags - has atomic operations done on it */
43 unsigned long flags ____cacheline_aligned_in_smp;
44};
45
46/*
47 * macros/functions for gaining access to the thread information structure
48 *
49 * preempt_count needs to be 1 initially, until the scheduler is functional.
50 */
51#define INIT_THREAD_INFO(tsk) \
52{ \
53 .task = &tsk, \
54 .exec_domain = &default_exec_domain, \
55 .cpu = 0, \
56 .preempt_count = 1, \
57 .restart_block = { \
58 .fn = do_no_restart_syscall, \
59 }, \
60 .flags = 0, \
61}
62
63#define init_thread_info (init_thread_union.thread_info)
64#define init_stack (init_thread_union.stack)
65
66/* thread information allocation */
67
68#ifdef CONFIG_DEBUG_STACK_USAGE
69#define alloc_thread_info(tsk) \
70 ({ \
71 struct thread_info *ret; \
72 \
73 ret = kmalloc(THREAD_SIZE, GFP_KERNEL); \
74 if (ret) \
75 memset(ret, 0, THREAD_SIZE); \
76 ret; \
77 })
78#else
79#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
80#endif
81#define free_thread_info(ti) kfree(ti)
82#define get_thread_info(ti) get_task_struct((ti)->task)
83#define put_thread_info(ti) put_task_struct((ti)->task)
84
85/* how to get the thread information struct from C */
86static inline struct thread_info *current_thread_info(void)
87{
88 register unsigned long sp asm("r1");
89
90 /* gcc4, at least, is smart enough to turn this into a single
91 * rlwinm for ppc32 and clrrdi for ppc64 */
92 return (struct thread_info *)(sp & ~(THREAD_SIZE-1));
93}
94
95#endif /* __ASSEMBLY__ */
96
97#define PREEMPT_ACTIVE 0x10000000
98
99/*
100 * thread information flag bit numbers
101 */
102#define TIF_SYSCALL_TRACE 0 /* syscall trace active */
103#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */
104#define TIF_SIGPENDING 2 /* signal pending */
105#define TIF_NEED_RESCHED 3 /* rescheduling necessary */
106#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling
107 TIF_NEED_RESCHED */
108#define TIF_32BIT 5 /* 32 bit binary */
109/* #define SPARE 6 */
110#define TIF_ABI_PENDING 7 /* 32/64 bit switch needed */
111#define TIF_SYSCALL_AUDIT 8 /* syscall auditing active */
112#define TIF_SINGLESTEP 9 /* singlestepping active */
113#define TIF_MEMDIE 10
114#define TIF_SECCOMP 11 /* secure computing */
115
116/* as above, but as bit values */
117#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE)
118#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
119#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
120#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
121#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG)
122#define _TIF_32BIT (1<<TIF_32BIT)
123/* #define _SPARE (1<<SPARE) */
124#define _TIF_ABI_PENDING (1<<TIF_ABI_PENDING)
125#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
126#define _TIF_SINGLESTEP (1<<TIF_SINGLESTEP)
127#define _TIF_SECCOMP (1<<TIF_SECCOMP)
128#define _TIF_SYSCALL_T_OR_A (_TIF_SYSCALL_TRACE|_TIF_SYSCALL_AUDIT|_TIF_SECCOMP)
129
130#define _TIF_USER_WORK_MASK (_TIF_NOTIFY_RESUME | _TIF_SIGPENDING | \
131 _TIF_NEED_RESCHED)
132
133#endif /* __KERNEL__ */
134
135#endif /* _ASM_POWERPC_THREAD_INFO_H */
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
new file mode 100644
index 000000000000..99bfe3281768
--- /dev/null
+++ b/include/asm-powerpc/time.h
@@ -0,0 +1,214 @@
1/*
2 * Common time prototypes and such for all ppc machines.
3 *
4 * Written by Cort Dougan (cort@cs.nmt.edu) to merge
5 * Paul Mackerras' version and mine for PReP and Pmac.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#ifndef __POWERPC_TIME_H
14#define __POWERPC_TIME_H
15
16#ifdef __KERNEL__
17#include <linux/config.h>
18#include <linux/types.h>
19#include <linux/percpu.h>
20
21#include <asm/processor.h>
22#ifdef CONFIG_PPC64
23#include <asm/paca.h>
24#include <asm/iSeries/HvCall.h>
25#endif
26
27/* time.c */
28extern unsigned long tb_ticks_per_jiffy;
29extern unsigned long tb_ticks_per_usec;
30extern unsigned long tb_ticks_per_sec;
31extern u64 tb_to_xs;
32extern unsigned tb_to_us;
33extern u64 tb_last_stamp;
34
35DECLARE_PER_CPU(unsigned long, last_jiffy);
36
37struct rtc_time;
38extern void to_tm(int tim, struct rtc_time * tm);
39extern time_t last_rtc_update;
40
41extern void generic_calibrate_decr(void);
42extern void wakeup_decrementer(void);
43
44/* Some sane defaults: 125 MHz timebase, 1GHz processor */
45extern unsigned long ppc_proc_freq;
46#define DEFAULT_PROC_FREQ (DEFAULT_TB_FREQ * 8)
47extern unsigned long ppc_tb_freq;
48#define DEFAULT_TB_FREQ 125000000UL
49
50/*
51 * By putting all of this stuff into a single struct we
52 * reduce the number of cache lines touched by do_gettimeofday.
53 * Both by collecting all of the data in one cache line and
54 * by touching only one TOC entry on ppc64.
55 */
56struct gettimeofday_vars {
57 u64 tb_to_xs;
58 u64 stamp_xsec;
59 u64 tb_orig_stamp;
60};
61
62struct gettimeofday_struct {
63 unsigned long tb_ticks_per_sec;
64 struct gettimeofday_vars vars[2];
65 struct gettimeofday_vars * volatile varp;
66 unsigned var_idx;
67 unsigned tb_to_us;
68};
69
70struct div_result {
71 u64 result_high;
72 u64 result_low;
73};
74
75/* Accessor functions for the timebase (RTC on 601) registers. */
76/* If one day CONFIG_POWER is added just define __USE_RTC as 1 */
77#ifdef CONFIG_6xx
78#define __USE_RTC() (!cpu_has_feature(CPU_FTR_USE_TB))
79#else
80#define __USE_RTC() 0
81#endif
82
83/* On ppc64 this gets us the whole timebase; on ppc32 just the lower half */
84static inline unsigned long get_tbl(void)
85{
86 unsigned long tbl;
87
88#if defined(CONFIG_403GCX)
89 asm volatile("mfspr %0, 0x3dd" : "=r" (tbl));
90#else
91 asm volatile("mftb %0" : "=r" (tbl));
92#endif
93 return tbl;
94}
95
96static inline unsigned int get_tbu(void)
97{
98 unsigned int tbu;
99
100#if defined(CONFIG_403GCX)
101 asm volatile("mfspr %0, 0x3dc" : "=r" (tbu));
102#else
103 asm volatile("mftbu %0" : "=r" (tbu));
104#endif
105 return tbu;
106}
107
108static inline unsigned int get_rtcl(void)
109{
110 unsigned int rtcl;
111
112 asm volatile("mfrtcl %0" : "=r" (rtcl));
113 return rtcl;
114}
115
116#ifdef CONFIG_PPC64
117static inline u64 get_tb(void)
118{
119 return mftb();
120}
121#else
122static inline u64 get_tb(void)
123{
124 unsigned int tbhi, tblo, tbhi2;
125
126 do {
127 tbhi = get_tbu();
128 tblo = get_tbl();
129 tbhi2 = get_tbu();
130 } while (tbhi != tbhi2);
131
132 return ((u64)tbhi << 32) | tblo;
133}
134#endif
135
136static inline void set_tb(unsigned int upper, unsigned int lower)
137{
138 mtspr(SPRN_TBWL, 0);
139 mtspr(SPRN_TBWU, upper);
140 mtspr(SPRN_TBWL, lower);
141}
142
143/* Accessor functions for the decrementer register.
144 * The 4xx doesn't even have a decrementer. I tried to use the
145 * generic timer interrupt code, which seems OK, with the 4xx PIT
146 * in auto-reload mode. The problem is PIT stops counting when it
147 * hits zero. If it would wrap, we could use it just like a decrementer.
148 */
149static inline unsigned int get_dec(void)
150{
151#if defined(CONFIG_40x)
152 return (mfspr(SPRN_PIT));
153#else
154 return (mfspr(SPRN_DEC));
155#endif
156}
157
158static inline void set_dec(int val)
159{
160#if defined(CONFIG_40x)
161 return; /* Have to let it auto-reload */
162#elif defined(CONFIG_8xx_CPU6)
163 set_dec_cpu6(val);
164#else
165#ifdef CONFIG_PPC_ISERIES
166 struct paca_struct *lpaca = get_paca();
167 int cur_dec;
168
169 if (lpaca->lppaca.shared_proc) {
170 lpaca->lppaca.virtual_decr = val;
171 cur_dec = get_dec();
172 if (cur_dec > val)
173 HvCall_setVirtualDecr();
174 } else
175#endif
176 mtspr(SPRN_DEC, val);
177#endif /* not 40x or 8xx_CPU6 */
178}
179
180static inline unsigned long tb_ticks_since(unsigned long tstamp)
181{
182 if (__USE_RTC()) {
183 int delta = get_rtcl() - (unsigned int) tstamp;
184 return delta < 0 ? delta + 1000000000 : delta;
185 }
186 return get_tbl() - tstamp;
187}
188
189#define mulhwu(x,y) \
190({unsigned z; asm ("mulhwu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
191
192#ifdef CONFIG_PPC64
193#define mulhdu(x,y) \
194({unsigned long z; asm ("mulhdu %0,%1,%2" : "=r" (z) : "r" (x), "r" (y)); z;})
195#else
196extern u64 mulhdu(u64, u64);
197#endif
198
199extern void smp_space_timers(unsigned int);
200
201extern unsigned mulhwu_scale_factor(unsigned, unsigned);
202extern void div128_by_32(u64 dividend_high, u64 dividend_low,
203 unsigned divisor, struct div_result *dr);
204
205/* Used to store Processor Utilization register (purr) values */
206
207struct cpu_usage {
208 u64 current_tb; /* Holds the current purr register values */
209};
210
211DECLARE_PER_CPU(struct cpu_usage, cpu_usage_array);
212
213#endif /* __KERNEL__ */
214#endif /* __PPC64_TIME_H */
diff --git a/include/asm-powerpc/types.h b/include/asm-powerpc/types.h
new file mode 100644
index 000000000000..7d803cb547bb
--- /dev/null
+++ b/include/asm-powerpc/types.h
@@ -0,0 +1,104 @@
1#ifndef _ASM_POWERPC_TYPES_H
2#define _ASM_POWERPC_TYPES_H
3
4#ifndef __ASSEMBLY__
5
6/*
7 * This file is never included by application software unless
8 * explicitly requested (e.g., via linux/types.h) in which case the
9 * application is Linux specific so (user-) name space pollution is
10 * not a major issue. However, for interoperability, libraries still
11 * need to be careful to avoid a name clashes.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version
16 * 2 of the License, or (at your option) any later version.
17 */
18
19#ifdef __powerpc64__
20typedef unsigned int umode_t;
21#else
22typedef unsigned short umode_t;
23#endif
24
25/*
26 * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
27 * header files exported to user space
28 */
29
30typedef __signed__ char __s8;
31typedef unsigned char __u8;
32
33typedef __signed__ short __s16;
34typedef unsigned short __u16;
35
36typedef __signed__ int __s32;
37typedef unsigned int __u32;
38
39#ifdef __powerpc64__
40typedef __signed__ long __s64;
41typedef unsigned long __u64;
42#else
43#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
44typedef __signed__ long long __s64;
45typedef unsigned long long __u64;
46#endif
47#endif /* __powerpc64__ */
48
49typedef struct {
50 __u32 u[4];
51} __attribute((aligned(16))) __vector128;
52
53#endif /* __ASSEMBLY__ */
54
55#ifdef __KERNEL__
56/*
57 * These aren't exported outside the kernel to avoid name space clashes
58 */
59#ifdef __powerpc64__
60#define BITS_PER_LONG 64
61#else
62#define BITS_PER_LONG 32
63#endif
64
65#ifndef __ASSEMBLY__
66
67typedef signed char s8;
68typedef unsigned char u8;
69
70typedef signed short s16;
71typedef unsigned short u16;
72
73typedef signed int s32;
74typedef unsigned int u32;
75
76#ifdef __powerpc64__
77typedef signed long s64;
78typedef unsigned long u64;
79#else
80typedef signed long long s64;
81typedef unsigned long long u64;
82#endif
83
84typedef __vector128 vector128;
85
86typedef u32 dma_addr_t;
87typedef u64 dma64_addr_t;
88
89typedef struct {
90 unsigned long entry;
91 unsigned long toc;
92 unsigned long env;
93} func_descr_t;
94
95#ifdef CONFIG_LBD
96typedef u64 sector_t;
97#define HAVE_SECTOR_T
98#endif
99
100#endif /* __ASSEMBLY__ */
101
102#endif /* __KERNEL__ */
103
104#endif /* _ASM_POWERPC_TYPES_H */
diff --git a/include/asm-powerpc/uninorth.h b/include/asm-powerpc/uninorth.h
new file mode 100644
index 000000000000..f737732c3861
--- /dev/null
+++ b/include/asm-powerpc/uninorth.h
@@ -0,0 +1,229 @@
1/*
2 * uninorth.h: definitions for using the "UniNorth" host bridge chip
3 * from Apple. This chip is used on "Core99" machines
4 * This also includes U2 used on more recent MacRISC2/3
5 * machines and U3 (G5)
6 *
7 */
8#ifdef __KERNEL__
9#ifndef __ASM_UNINORTH_H__
10#define __ASM_UNINORTH_H__
11
12/*
13 * Uni-N and U3 config space reg. definitions
14 *
15 * (Little endian)
16 */
17
18/* Address ranges selection. This one should work with Bandit too */
19/* Not U3 */
20#define UNI_N_ADDR_SELECT 0x48
21#define UNI_N_ADDR_COARSE_MASK 0xffff0000 /* 256Mb regions at *0000000 */
22#define UNI_N_ADDR_FINE_MASK 0x0000ffff /* 16Mb regions at f*000000 */
23
24/* AGP registers */
25/* Not U3 */
26#define UNI_N_CFG_GART_BASE 0x8c
27#define UNI_N_CFG_AGP_BASE 0x90
28#define UNI_N_CFG_GART_CTRL 0x94
29#define UNI_N_CFG_INTERNAL_STATUS 0x98
30#define UNI_N_CFG_GART_DUMMY_PAGE 0xa4
31
32/* UNI_N_CFG_GART_CTRL bits definitions */
33#define UNI_N_CFG_GART_INVAL 0x00000001
34#define UNI_N_CFG_GART_ENABLE 0x00000100
35#define UNI_N_CFG_GART_2xRESET 0x00010000
36#define UNI_N_CFG_GART_DISSBADET 0x00020000
37/* The following seems to only be used only on U3 <j.glisse@gmail.com> */
38#define U3_N_CFG_GART_SYNCMODE 0x00040000
39#define U3_N_CFG_GART_PERFRD 0x00080000
40#define U3_N_CFG_GART_B2BGNT 0x00200000
41#define U3_N_CFG_GART_FASTDDR 0x00400000
42
43/* My understanding of UniNorth AGP as of UniNorth rev 1.0x,
44 * revision 1.5 (x4 AGP) may need further changes.
45 *
46 * AGP_BASE register contains the base address of the AGP aperture on
47 * the AGP bus. It doesn't seem to be visible to the CPU as of UniNorth 1.x,
48 * even if decoding of this address range is enabled in the address select
49 * register. Apparently, the only supported bases are 256Mb multiples
50 * (high 4 bits of that register).
51 *
52 * GART_BASE register appear to contain the physical address of the GART
53 * in system memory in the high address bits (page aligned), and the
54 * GART size in the low order bits (number of GART pages)
55 *
56 * The GART format itself is one 32bits word per physical memory page.
57 * This word contains, in little-endian format (!!!), the physical address
58 * of the page in the high bits, and what appears to be an "enable" bit
59 * in the LSB bit (0) that must be set to 1 when the entry is valid.
60 *
61 * Obviously, the GART is not cache coherent and so any change to it
62 * must be flushed to memory (or maybe just make the GART space non
63 * cachable). AGP memory itself doens't seem to be cache coherent neither.
64 *
65 * In order to invalidate the GART (which is probably necessary to inval
66 * the bridge internal TLBs), the following sequence has to be written,
67 * in order, to the GART_CTRL register:
68 *
69 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
70 * UNI_N_CFG_GART_ENABLE
71 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_2xRESET
72 * UNI_N_CFG_GART_ENABLE
73 *
74 * As far as AGP "features" are concerned, it looks like fast write may
75 * not be supported but this has to be confirmed.
76 *
77 * Turning on AGP seem to require a double invalidate operation, one before
78 * setting the AGP command register, on after.
79 *
80 * Turning off AGP seems to require the following sequence: first wait
81 * for the AGP to be idle by reading the internal status register, then
82 * write in that order to the GART_CTRL register:
83 *
84 * UNI_N_CFG_GART_ENABLE | UNI_N_CFG_GART_INVAL
85 * 0
86 * UNI_N_CFG_GART_2xRESET
87 * 0
88 */
89
90/*
91 * Uni-N memory mapped reg. definitions
92 *
93 * Those registers are Big-Endian !!
94 *
95 * Their meaning come from either Darwin and/or from experiments I made with
96 * the bootrom, I'm not sure about their exact meaning yet
97 *
98 */
99
100/* Version of the UniNorth chip */
101#define UNI_N_VERSION 0x0000 /* Known versions: 3,7 and 8 */
102
103#define UNI_N_VERSION_107 0x0003 /* 1.0.7 */
104#define UNI_N_VERSION_10A 0x0007 /* 1.0.10 */
105#define UNI_N_VERSION_150 0x0011 /* 1.5 */
106#define UNI_N_VERSION_200 0x0024 /* 2.0 */
107#define UNI_N_VERSION_PANGEA 0x00C0 /* Integrated U1 + K */
108#define UNI_N_VERSION_INTREPID 0x00D2 /* Integrated U2 + K */
109#define UNI_N_VERSION_300 0x0030 /* 3.0 (U3 on G5) */
110
111/* This register is used to enable/disable various clocks */
112#define UNI_N_CLOCK_CNTL 0x0020
113#define UNI_N_CLOCK_CNTL_PCI 0x00000001 /* PCI2 clock control */
114#define UNI_N_CLOCK_CNTL_GMAC 0x00000002 /* GMAC clock control */
115#define UNI_N_CLOCK_CNTL_FW 0x00000004 /* FireWire clock control */
116#define UNI_N_CLOCK_CNTL_ATA100 0x00000010 /* ATA-100 clock control (U2) */
117
118/* Power Management control */
119#define UNI_N_POWER_MGT 0x0030
120#define UNI_N_POWER_MGT_NORMAL 0x00
121#define UNI_N_POWER_MGT_IDLE2 0x01
122#define UNI_N_POWER_MGT_SLEEP 0x02
123
124/* This register is configured by Darwin depending on the UniN
125 * revision
126 */
127#define UNI_N_ARB_CTRL 0x0040
128#define UNI_N_ARB_CTRL_QACK_DELAY_SHIFT 15
129#define UNI_N_ARB_CTRL_QACK_DELAY_MASK 0x0e1f8000
130#define UNI_N_ARB_CTRL_QACK_DELAY 0x30
131#define UNI_N_ARB_CTRL_QACK_DELAY105 0x00
132
133/* This one _might_ return the CPU number of the CPU reading it;
134 * the bootROM decides whether to boot or to sleep/spinloop depending
135 * on this register beeing 0 or not
136 */
137#define UNI_N_CPU_NUMBER 0x0050
138
139/* This register appear to be read by the bootROM to decide what
140 * to do on a non-recoverable reset (powerup or wakeup)
141 */
142#define UNI_N_HWINIT_STATE 0x0070
143#define UNI_N_HWINIT_STATE_SLEEPING 0x01
144#define UNI_N_HWINIT_STATE_RUNNING 0x02
145/* This last bit appear to be used by the bootROM to know the second
146 * CPU has started and will enter it's sleep loop with IP=0
147 */
148#define UNI_N_HWINIT_STATE_CPU1_FLAG 0x10000000
149
150/* This register controls AACK delay, which is set when 2004 iBook/PowerBook
151 * is in low speed mode.
152 */
153#define UNI_N_AACK_DELAY 0x0100
154#define UNI_N_AACK_DELAY_ENABLE 0x00000001
155
156/* Clock status for Intrepid */
157#define UNI_N_CLOCK_STOP_STATUS0 0x0150
158#define UNI_N_CLOCK_STOPPED_EXTAGP 0x00200000
159#define UNI_N_CLOCK_STOPPED_AGPDEL 0x00100000
160#define UNI_N_CLOCK_STOPPED_I2S0_45_49 0x00080000
161#define UNI_N_CLOCK_STOPPED_I2S0_18 0x00040000
162#define UNI_N_CLOCK_STOPPED_I2S1_45_49 0x00020000
163#define UNI_N_CLOCK_STOPPED_I2S1_18 0x00010000
164#define UNI_N_CLOCK_STOPPED_TIMER 0x00008000
165#define UNI_N_CLOCK_STOPPED_SCC_RTCLK18 0x00004000
166#define UNI_N_CLOCK_STOPPED_SCC_RTCLK32 0x00002000
167#define UNI_N_CLOCK_STOPPED_SCC_VIA32 0x00001000
168#define UNI_N_CLOCK_STOPPED_SCC_SLOT0 0x00000800
169#define UNI_N_CLOCK_STOPPED_SCC_SLOT1 0x00000400
170#define UNI_N_CLOCK_STOPPED_SCC_SLOT2 0x00000200
171#define UNI_N_CLOCK_STOPPED_PCI_FBCLKO 0x00000100
172#define UNI_N_CLOCK_STOPPED_VEO0 0x00000080
173#define UNI_N_CLOCK_STOPPED_VEO1 0x00000040
174#define UNI_N_CLOCK_STOPPED_USB0 0x00000020
175#define UNI_N_CLOCK_STOPPED_USB1 0x00000010
176#define UNI_N_CLOCK_STOPPED_USB2 0x00000008
177#define UNI_N_CLOCK_STOPPED_32 0x00000004
178#define UNI_N_CLOCK_STOPPED_45 0x00000002
179#define UNI_N_CLOCK_STOPPED_49 0x00000001
180
181#define UNI_N_CLOCK_STOP_STATUS1 0x0160
182#define UNI_N_CLOCK_STOPPED_PLL4REF 0x00080000
183#define UNI_N_CLOCK_STOPPED_CPUDEL 0x00040000
184#define UNI_N_CLOCK_STOPPED_CPU 0x00020000
185#define UNI_N_CLOCK_STOPPED_BUF_REFCKO 0x00010000
186#define UNI_N_CLOCK_STOPPED_PCI2 0x00008000
187#define UNI_N_CLOCK_STOPPED_FW 0x00004000
188#define UNI_N_CLOCK_STOPPED_GB 0x00002000
189#define UNI_N_CLOCK_STOPPED_ATA66 0x00001000
190#define UNI_N_CLOCK_STOPPED_ATA100 0x00000800
191#define UNI_N_CLOCK_STOPPED_MAX 0x00000400
192#define UNI_N_CLOCK_STOPPED_PCI1 0x00000200
193#define UNI_N_CLOCK_STOPPED_KLPCI 0x00000100
194#define UNI_N_CLOCK_STOPPED_USB0PCI 0x00000080
195#define UNI_N_CLOCK_STOPPED_USB1PCI 0x00000040
196#define UNI_N_CLOCK_STOPPED_USB2PCI 0x00000020
197#define UNI_N_CLOCK_STOPPED_7PCI1 0x00000008
198#define UNI_N_CLOCK_STOPPED_AGP 0x00000004
199#define UNI_N_CLOCK_STOPPED_PCI0 0x00000002
200#define UNI_N_CLOCK_STOPPED_18 0x00000001
201
202/* Intrepid registe to OF do-platform-clockspreading */
203#define UNI_N_CLOCK_SPREADING 0x190
204
205/* Uninorth 1.5 rev. has additional perf. monitor registers at 0xf00-0xf50 */
206
207
208/*
209 * U3 specific registers
210 */
211
212
213/* U3 Toggle */
214#define U3_TOGGLE_REG 0x00e0
215#define U3_PMC_START_STOP 0x0001
216#define U3_MPIC_RESET 0x0002
217#define U3_MPIC_OUTPUT_ENABLE 0x0004
218
219/* U3 API PHY Config 1 */
220#define U3_API_PHY_CONFIG_1 0x23030
221
222/* U3 HyperTransport registers */
223#define U3_HT_CONFIG_BASE 0x70000
224#define U3_HT_LINK_COMMAND 0x100
225#define U3_HT_LINK_CONFIG 0x110
226#define U3_HT_LINK_FREQ 0x120
227
228#endif /* __ASM_UNINORTH_H__ */
229#endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/unistd.h b/include/asm-powerpc/unistd.h
new file mode 100644
index 000000000000..c2d039e338a8
--- /dev/null
+++ b/include/asm-powerpc/unistd.h
@@ -0,0 +1,510 @@
1#ifndef _ASM_PPC_UNISTD_H_
2#define _ASM_PPC_UNISTD_H_
3
4/*
5 * This file contains the system call numbers.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13#define __NR_restart_syscall 0
14#define __NR_exit 1
15#define __NR_fork 2
16#define __NR_read 3
17#define __NR_write 4
18#define __NR_open 5
19#define __NR_close 6
20#define __NR_waitpid 7
21#define __NR_creat 8
22#define __NR_link 9
23#define __NR_unlink 10
24#define __NR_execve 11
25#define __NR_chdir 12
26#define __NR_time 13
27#define __NR_mknod 14
28#define __NR_chmod 15
29#define __NR_lchown 16
30#define __NR_break 17
31#define __NR_oldstat 18
32#define __NR_lseek 19
33#define __NR_getpid 20
34#define __NR_mount 21
35#define __NR_umount 22
36#define __NR_setuid 23
37#define __NR_getuid 24
38#define __NR_stime 25
39#define __NR_ptrace 26
40#define __NR_alarm 27
41#define __NR_oldfstat 28
42#define __NR_pause 29
43#define __NR_utime 30
44#define __NR_stty 31
45#define __NR_gtty 32
46#define __NR_access 33
47#define __NR_nice 34
48#define __NR_ftime 35
49#define __NR_sync 36
50#define __NR_kill 37
51#define __NR_rename 38
52#define __NR_mkdir 39
53#define __NR_rmdir 40
54#define __NR_dup 41
55#define __NR_pipe 42
56#define __NR_times 43
57#define __NR_prof 44
58#define __NR_brk 45
59#define __NR_setgid 46
60#define __NR_getgid 47
61#define __NR_signal 48
62#define __NR_geteuid 49
63#define __NR_getegid 50
64#define __NR_acct 51
65#define __NR_umount2 52
66#define __NR_lock 53
67#define __NR_ioctl 54
68#define __NR_fcntl 55
69#define __NR_mpx 56
70#define __NR_setpgid 57
71#define __NR_ulimit 58
72#define __NR_oldolduname 59
73#define __NR_umask 60
74#define __NR_chroot 61
75#define __NR_ustat 62
76#define __NR_dup2 63
77#define __NR_getppid 64
78#define __NR_getpgrp 65
79#define __NR_setsid 66
80#define __NR_sigaction 67
81#define __NR_sgetmask 68
82#define __NR_ssetmask 69
83#define __NR_setreuid 70
84#define __NR_setregid 71
85#define __NR_sigsuspend 72
86#define __NR_sigpending 73
87#define __NR_sethostname 74
88#define __NR_setrlimit 75
89#define __NR_getrlimit 76
90#define __NR_getrusage 77
91#define __NR_gettimeofday 78
92#define __NR_settimeofday 79
93#define __NR_getgroups 80
94#define __NR_setgroups 81
95#define __NR_select 82
96#define __NR_symlink 83
97#define __NR_oldlstat 84
98#define __NR_readlink 85
99#define __NR_uselib 86
100#define __NR_swapon 87
101#define __NR_reboot 88
102#define __NR_readdir 89
103#define __NR_mmap 90
104#define __NR_munmap 91
105#define __NR_truncate 92
106#define __NR_ftruncate 93
107#define __NR_fchmod 94
108#define __NR_fchown 95
109#define __NR_getpriority 96
110#define __NR_setpriority 97
111#define __NR_profil 98
112#define __NR_statfs 99
113#define __NR_fstatfs 100
114#define __NR_ioperm 101
115#define __NR_socketcall 102
116#define __NR_syslog 103
117#define __NR_setitimer 104
118#define __NR_getitimer 105
119#define __NR_stat 106
120#define __NR_lstat 107
121#define __NR_fstat 108
122#define __NR_olduname 109
123#define __NR_iopl 110
124#define __NR_vhangup 111
125#define __NR_idle 112
126#define __NR_vm86 113
127#define __NR_wait4 114
128#define __NR_swapoff 115
129#define __NR_sysinfo 116
130#define __NR_ipc 117
131#define __NR_fsync 118
132#define __NR_sigreturn 119
133#define __NR_clone 120
134#define __NR_setdomainname 121
135#define __NR_uname 122
136#define __NR_modify_ldt 123
137#define __NR_adjtimex 124
138#define __NR_mprotect 125
139#define __NR_sigprocmask 126
140#define __NR_create_module 127
141#define __NR_init_module 128
142#define __NR_delete_module 129
143#define __NR_get_kernel_syms 130
144#define __NR_quotactl 131
145#define __NR_getpgid 132
146#define __NR_fchdir 133
147#define __NR_bdflush 134
148#define __NR_sysfs 135
149#define __NR_personality 136
150#define __NR_afs_syscall 137 /* Syscall for Andrew File System */
151#define __NR_setfsuid 138
152#define __NR_setfsgid 139
153#define __NR__llseek 140
154#define __NR_getdents 141
155#define __NR__newselect 142
156#define __NR_flock 143
157#define __NR_msync 144
158#define __NR_readv 145
159#define __NR_writev 146
160#define __NR_getsid 147
161#define __NR_fdatasync 148
162#define __NR__sysctl 149
163#define __NR_mlock 150
164#define __NR_munlock 151
165#define __NR_mlockall 152
166#define __NR_munlockall 153
167#define __NR_sched_setparam 154
168#define __NR_sched_getparam 155
169#define __NR_sched_setscheduler 156
170#define __NR_sched_getscheduler 157
171#define __NR_sched_yield 158
172#define __NR_sched_get_priority_max 159
173#define __NR_sched_get_priority_min 160
174#define __NR_sched_rr_get_interval 161
175#define __NR_nanosleep 162
176#define __NR_mremap 163
177#define __NR_setresuid 164
178#define __NR_getresuid 165
179#define __NR_query_module 166
180#define __NR_poll 167
181#define __NR_nfsservctl 168
182#define __NR_setresgid 169
183#define __NR_getresgid 170
184#define __NR_prctl 171
185#define __NR_rt_sigreturn 172
186#define __NR_rt_sigaction 173
187#define __NR_rt_sigprocmask 174
188#define __NR_rt_sigpending 175
189#define __NR_rt_sigtimedwait 176
190#define __NR_rt_sigqueueinfo 177
191#define __NR_rt_sigsuspend 178
192#define __NR_pread64 179
193#define __NR_pwrite64 180
194#define __NR_chown 181
195#define __NR_getcwd 182
196#define __NR_capget 183
197#define __NR_capset 184
198#define __NR_sigaltstack 185
199#define __NR_sendfile 186
200#define __NR_getpmsg 187 /* some people actually want streams */
201#define __NR_putpmsg 188 /* some people actually want streams */
202#define __NR_vfork 189
203#define __NR_ugetrlimit 190 /* SuS compliant getrlimit */
204#define __NR_readahead 191
205#ifndef __powerpc64__ /* these are 32-bit only */
206#define __NR_mmap2 192
207#define __NR_truncate64 193
208#define __NR_ftruncate64 194
209#define __NR_stat64 195
210#define __NR_lstat64 196
211#define __NR_fstat64 197
212#endif
213#define __NR_pciconfig_read 198
214#define __NR_pciconfig_write 199
215#define __NR_pciconfig_iobase 200
216#define __NR_multiplexer 201
217#define __NR_getdents64 202
218#define __NR_pivot_root 203
219#ifndef __powerpc64__
220#define __NR_fcntl64 204
221#endif
222#define __NR_madvise 205
223#define __NR_mincore 206
224#define __NR_gettid 207
225#define __NR_tkill 208
226#define __NR_setxattr 209
227#define __NR_lsetxattr 210
228#define __NR_fsetxattr 211
229#define __NR_getxattr 212
230#define __NR_lgetxattr 213
231#define __NR_fgetxattr 214
232#define __NR_listxattr 215
233#define __NR_llistxattr 216
234#define __NR_flistxattr 217
235#define __NR_removexattr 218
236#define __NR_lremovexattr 219
237#define __NR_fremovexattr 220
238#define __NR_futex 221
239#define __NR_sched_setaffinity 222
240#define __NR_sched_getaffinity 223
241/* 224 currently unused */
242#define __NR_tuxcall 225
243#ifndef __powerpc64__
244#define __NR_sendfile64 226
245#endif
246#define __NR_io_setup 227
247#define __NR_io_destroy 228
248#define __NR_io_getevents 229
249#define __NR_io_submit 230
250#define __NR_io_cancel 231
251#define __NR_set_tid_address 232
252#define __NR_fadvise64 233
253#define __NR_exit_group 234
254#define __NR_lookup_dcookie 235
255#define __NR_epoll_create 236
256#define __NR_epoll_ctl 237
257#define __NR_epoll_wait 238
258#define __NR_remap_file_pages 239
259#define __NR_timer_create 240
260#define __NR_timer_settime 241
261#define __NR_timer_gettime 242
262#define __NR_timer_getoverrun 243
263#define __NR_timer_delete 244
264#define __NR_clock_settime 245
265#define __NR_clock_gettime 246
266#define __NR_clock_getres 247
267#define __NR_clock_nanosleep 248
268#define __NR_swapcontext 249
269#define __NR_tgkill 250
270#define __NR_utimes 251
271#define __NR_statfs64 252
272#define __NR_fstatfs64 253
273#ifndef __powerpc64__
274#define __NR_fadvise64_64 254
275#endif
276#define __NR_rtas 255
277#define __NR_sys_debug_setcontext 256
278/* Number 257 is reserved for vserver */
279/* 258 currently unused */
280#define __NR_mbind 259
281#define __NR_get_mempolicy 260
282#define __NR_set_mempolicy 261
283#define __NR_mq_open 262
284#define __NR_mq_unlink 263
285#define __NR_mq_timedsend 264
286#define __NR_mq_timedreceive 265
287#define __NR_mq_notify 266
288#define __NR_mq_getsetattr 267
289#define __NR_kexec_load 268
290#define __NR_add_key 269
291#define __NR_request_key 270
292#define __NR_keyctl 271
293#define __NR_waitid 272
294#define __NR_ioprio_set 273
295#define __NR_ioprio_get 274
296#define __NR_inotify_init 275
297#define __NR_inotify_add_watch 276
298#define __NR_inotify_rm_watch 277
299
300#define __NR_syscalls 278
301
302#ifdef __KERNEL__
303#define __NR__exit __NR_exit
304#define NR_syscalls __NR_syscalls
305#endif
306
307#ifndef __ASSEMBLY__
308
309/* On powerpc a system call basically clobbers the same registers like a
310 * function call, with the exception of LR (which is needed for the
311 * "sc; bnslr" sequence) and CR (where only CR0.SO is clobbered to signal
312 * an error return status).
313 */
314
315#define __syscall_nr(nr, type, name, args...) \
316 unsigned long __sc_ret, __sc_err; \
317 { \
318 register unsigned long __sc_0 __asm__ ("r0"); \
319 register unsigned long __sc_3 __asm__ ("r3"); \
320 register unsigned long __sc_4 __asm__ ("r4"); \
321 register unsigned long __sc_5 __asm__ ("r5"); \
322 register unsigned long __sc_6 __asm__ ("r6"); \
323 register unsigned long __sc_7 __asm__ ("r7"); \
324 register unsigned long __sc_8 __asm__ ("r8"); \
325 \
326 __sc_loadargs_##nr(name, args); \
327 __asm__ __volatile__ \
328 ("sc \n\t" \
329 "mfcr %0 " \
330 : "=&r" (__sc_0), \
331 "=&r" (__sc_3), "=&r" (__sc_4), \
332 "=&r" (__sc_5), "=&r" (__sc_6), \
333 "=&r" (__sc_7), "=&r" (__sc_8) \
334 : __sc_asm_input_##nr \
335 : "cr0", "ctr", "memory", \
336 "r9", "r10","r11", "r12"); \
337 __sc_ret = __sc_3; \
338 __sc_err = __sc_0; \
339 } \
340 if (__sc_err & 0x10000000) \
341 { \
342 errno = __sc_ret; \
343 __sc_ret = -1; \
344 } \
345 return (type) __sc_ret
346
347#define __sc_loadargs_0(name, dummy...) \
348 __sc_0 = __NR_##name
349#define __sc_loadargs_1(name, arg1) \
350 __sc_loadargs_0(name); \
351 __sc_3 = (unsigned long) (arg1)
352#define __sc_loadargs_2(name, arg1, arg2) \
353 __sc_loadargs_1(name, arg1); \
354 __sc_4 = (unsigned long) (arg2)
355#define __sc_loadargs_3(name, arg1, arg2, arg3) \
356 __sc_loadargs_2(name, arg1, arg2); \
357 __sc_5 = (unsigned long) (arg3)
358#define __sc_loadargs_4(name, arg1, arg2, arg3, arg4) \
359 __sc_loadargs_3(name, arg1, arg2, arg3); \
360 __sc_6 = (unsigned long) (arg4)
361#define __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5) \
362 __sc_loadargs_4(name, arg1, arg2, arg3, arg4); \
363 __sc_7 = (unsigned long) (arg5)
364#define __sc_loadargs_6(name, arg1, arg2, arg3, arg4, arg5, arg6) \
365 __sc_loadargs_5(name, arg1, arg2, arg3, arg4, arg5); \
366 __sc_8 = (unsigned long) (arg6)
367
368#define __sc_asm_input_0 "0" (__sc_0)
369#define __sc_asm_input_1 __sc_asm_input_0, "1" (__sc_3)
370#define __sc_asm_input_2 __sc_asm_input_1, "2" (__sc_4)
371#define __sc_asm_input_3 __sc_asm_input_2, "3" (__sc_5)
372#define __sc_asm_input_4 __sc_asm_input_3, "4" (__sc_6)
373#define __sc_asm_input_5 __sc_asm_input_4, "5" (__sc_7)
374#define __sc_asm_input_6 __sc_asm_input_5, "6" (__sc_8)
375
376#define _syscall0(type,name) \
377type name(void) \
378{ \
379 __syscall_nr(0, type, name); \
380}
381
382#define _syscall1(type,name,type1,arg1) \
383type name(type1 arg1) \
384{ \
385 __syscall_nr(1, type, name, arg1); \
386}
387
388#define _syscall2(type,name,type1,arg1,type2,arg2) \
389type name(type1 arg1, type2 arg2) \
390{ \
391 __syscall_nr(2, type, name, arg1, arg2); \
392}
393
394#define _syscall3(type,name,type1,arg1,type2,arg2,type3,arg3) \
395type name(type1 arg1, type2 arg2, type3 arg3) \
396{ \
397 __syscall_nr(3, type, name, arg1, arg2, arg3); \
398}
399
400#define _syscall4(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4) \
401type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) \
402{ \
403 __syscall_nr(4, type, name, arg1, arg2, arg3, arg4); \
404}
405
406#define _syscall5(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5) \
407type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) \
408{ \
409 __syscall_nr(5, type, name, arg1, arg2, arg3, arg4, arg5); \
410}
411#define _syscall6(type,name,type1,arg1,type2,arg2,type3,arg3,type4,arg4,type5,arg5,type6,arg6) \
412type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6) \
413{ \
414 __syscall_nr(6, type, name, arg1, arg2, arg3, arg4, arg5, arg6); \
415}
416
417#ifdef __KERNEL__
418
419#include <linux/config.h>
420#include <linux/types.h>
421#include <linux/compiler.h>
422#include <linux/linkage.h>
423
424#define __ARCH_WANT_IPC_PARSE_VERSION
425#define __ARCH_WANT_OLD_READDIR
426#define __ARCH_WANT_STAT64
427#define __ARCH_WANT_SYS_ALARM
428#define __ARCH_WANT_SYS_GETHOSTNAME
429#define __ARCH_WANT_SYS_PAUSE
430#define __ARCH_WANT_SYS_SGETMASK
431#define __ARCH_WANT_SYS_SIGNAL
432#define __ARCH_WANT_SYS_TIME
433#define __ARCH_WANT_SYS_UTIME
434#define __ARCH_WANT_SYS_WAITPID
435#define __ARCH_WANT_SYS_SOCKETCALL
436#define __ARCH_WANT_SYS_FADVISE64
437#define __ARCH_WANT_SYS_GETPGRP
438#define __ARCH_WANT_SYS_LLSEEK
439#define __ARCH_WANT_SYS_NICE
440#define __ARCH_WANT_SYS_OLD_GETRLIMIT
441#define __ARCH_WANT_SYS_OLDUMOUNT
442#define __ARCH_WANT_SYS_SIGPENDING
443#define __ARCH_WANT_SYS_SIGPROCMASK
444#define __ARCH_WANT_SYS_RT_SIGACTION
445#ifdef CONFIG_PPC32
446#define __ARCH_WANT_OLD_STAT
447#endif
448#ifdef CONFIG_PPC64
449#define __ARCH_WANT_COMPAT_SYS_TIME
450#endif
451
452/*
453 * System call prototypes.
454 */
455#ifdef __KERNEL_SYSCALLS__
456extern pid_t setsid(void);
457extern int write(int fd, const char *buf, off_t count);
458extern int read(int fd, char *buf, off_t count);
459extern off_t lseek(int fd, off_t offset, int count);
460extern int dup(int fd);
461extern int execve(const char *file, char **argv, char **envp);
462extern int open(const char *file, int flag, int mode);
463extern int close(int fd);
464extern pid_t waitpid(pid_t pid, int *wait_stat, int options);
465#endif /* __KERNEL_SYSCALLS__ */
466
467/*
468 * Functions that implement syscalls.
469 */
470unsigned long sys_mmap(unsigned long addr, size_t len, unsigned long prot,
471 unsigned long flags, unsigned long fd, off_t offset);
472unsigned long sys_mmap2(unsigned long addr, size_t len,
473 unsigned long prot, unsigned long flags,
474 unsigned long fd, unsigned long pgoff);
475struct pt_regs;
476int sys_execve(unsigned long a0, unsigned long a1, unsigned long a2,
477 unsigned long a3, unsigned long a4, unsigned long a5,
478 struct pt_regs *regs);
479int sys_clone(unsigned long clone_flags, unsigned long usp,
480 int __user *parent_tidp, void __user *child_threadptr,
481 int __user *child_tidp, int p6, struct pt_regs *regs);
482int sys_fork(unsigned long p1, unsigned long p2, unsigned long p3,
483 unsigned long p4, unsigned long p5, unsigned long p6,
484 struct pt_regs *regs);
485int sys_vfork(unsigned long p1, unsigned long p2, unsigned long p3,
486 unsigned long p4, unsigned long p5, unsigned long p6,
487 struct pt_regs *regs);
488int sys_pipe(int __user *fildes);
489int sys_ptrace(long request, long pid, long addr, long data);
490struct sigaction;
491long sys_rt_sigaction(int sig, const struct sigaction __user *act,
492 struct sigaction __user *oact, size_t sigsetsize);
493
494/*
495 * "Conditional" syscalls
496 *
497 * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
498 * but it doesn't work on all toolchains, so we just do it by hand
499 */
500#ifdef CONFIG_PPC32
501#define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
502#else
503#define cond_syscall(x) asm(".weak\t." #x "\n\t.set\t." #x ",.sys_ni_syscall")
504#endif
505
506#endif /* __KERNEL__ */
507
508#endif /* __ASSEMBLY__ */
509
510#endif /* _ASM_PPC_UNISTD_H_ */
diff --git a/include/asm-powerpc/vga.h b/include/asm-powerpc/vga.h
new file mode 100644
index 000000000000..f8d350aabf1a
--- /dev/null
+++ b/include/asm-powerpc/vga.h
@@ -0,0 +1,54 @@
1#ifndef _ASM_POWERPC_VGA_H_
2#define _ASM_POWERPC_VGA_H_
3
4#ifdef __KERNEL__
5
6/*
7 * Access to VGA videoram
8 *
9 * (c) 1998 Martin Mares <mj@ucw.cz>
10 */
11
12
13#include <asm/io.h>
14
15#include <linux/config.h>
16
17#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_MDA_CONSOLE)
18
19#define VT_BUF_HAVE_RW
20/*
21 * These are only needed for supporting VGA or MDA text mode, which use little
22 * endian byte ordering.
23 * In other cases, we can optimize by using native byte ordering and
24 * <linux/vt_buffer.h> has already done the right job for us.
25 */
26
27static inline void scr_writew(u16 val, volatile u16 *addr)
28{
29 st_le16(addr, val);
30}
31
32static inline u16 scr_readw(volatile const u16 *addr)
33{
34 return ld_le16(addr);
35}
36
37#define VT_BUF_HAVE_MEMCPYW
38#define scr_memcpyw memcpy
39
40#endif /* !CONFIG_VGA_CONSOLE && !CONFIG_MDA_CONSOLE */
41
42extern unsigned long vgacon_remap_base;
43
44#ifdef __powerpc64__
45#define VGA_MAP_MEM(x) ((unsigned long) ioremap((x), 0))
46#else
47#define VGA_MAP_MEM(x) (x + vgacon_remap_base)
48#endif
49
50#define vga_readb(x) (*(x))
51#define vga_writeb(x,y) (*(y) = (x))
52
53#endif /* __KERNEL__ */
54#endif /* _ASM_POWERPC_VGA_H_ */
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
new file mode 100644
index 000000000000..ca5f33277e0c
--- /dev/null
+++ b/include/asm-powerpc/xmon.h
@@ -0,0 +1,12 @@
1#ifndef __PPC_XMON_H
2#define __PPC_XMON_H
3#ifdef __KERNEL__
4
5struct pt_regs;
6
7extern void xmon(struct pt_regs *excp);
8extern void xmon_printf(const char *fmt, ...);
9extern void xmon_init(int);
10
11#endif
12#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 20:46:02 -0500