22 files changed, 422 insertions, 100 deletions

diff --git a/include/asm-powerpc/atomic.h b/include/asm-powerpc/atomic.h
index bb3c0ab7e667..53283e2540b3 100644
--- a/include/asm-powerpc/atomic.h
+++ b/include/asm-powerpc/atomic.h
@@ -27,8 +27,8 @@ static __inline__ void atomic_add(int a, atomic_t *v)
         PPC405_ERR77(0,%3)
 "       stwcx.  %0,0,%3 \n\
         bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (a), "r" (&v->counter), "m" (v->counter)
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (a), "r" (&v->counter)
         : "cc");
 }
 
@@ -63,8 +63,8 @@ static __inline__ void atomic_sub(int a, atomic_t *v)
         PPC405_ERR77(0,%3)
 "       stwcx.  %0,0,%3 \n\
         bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (a), "r" (&v->counter), "m" (v->counter)
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (a), "r" (&v->counter)
         : "cc");
 }
 
@@ -97,8 +97,8 @@ static __inline__ void atomic_inc(atomic_t *v)
         PPC405_ERR77(0,%2)
 "       stwcx.  %0,0,%2 \n\
         bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (&v->counter), "m" (v->counter)
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (&v->counter)
         : "cc");
 }
 
@@ -141,8 +141,8 @@ static __inline__ void atomic_dec(atomic_t *v)
         PPC405_ERR77(0,%2)\
 "       stwcx.  %0,0,%2\n\
         bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (&v->counter), "m" (v->counter)
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (&v->counter)
         : "cc");
 }
 
@@ -253,8 +253,8 @@ static __inline__ void atomic64_add(long a, atomic64_t *v)
         add     %0,%2,%0\n\
         stdcx.  %0,0,%3 \n\
         bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (a), "r" (&v->counter), "m" (v->counter)
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (a), "r" (&v->counter)
         : "cc");
 }
 
@@ -287,8 +287,8 @@ static __inline__ void atomic64_sub(long a, atomic64_t *v)
         subf    %0,%2,%0\n\
         stdcx.  %0,0,%3 \n\
         bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (a), "r" (&v->counter), "m" (v->counter)
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (a), "r" (&v->counter)
         : "cc");
 }
 
@@ -319,8 +319,8 @@ static __inline__ void atomic64_inc(atomic64_t *v)
         addic   %0,%0,1\n\
         stdcx.  %0,0,%2 \n\
         bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (&v->counter), "m" (v->counter)
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (&v->counter)
         : "cc");
 }
 
@@ -361,8 +361,8 @@ static __inline__ void atomic64_dec(atomic64_t *v)
         addic   %0,%0,-1\n\
         stdcx.  %0,0,%2\n\
         bne-    1b"
-        : "=&r" (t), "=m" (v->counter)
-        : "r" (&v->counter), "m" (v->counter)
+        : "=&r" (t), "+m" (v->counter)
+        : "r" (&v->counter)
         : "cc");
 }
 
diff --git a/include/asm-powerpc/backlight.h b/include/asm-powerpc/backlight.h
index a5e9e656e332..8cf5c37c3817 100644
--- a/include/asm-powerpc/backlight.h
+++ b/include/asm-powerpc/backlight.h
@@ -16,16 +16,26 @@
 extern struct backlight_device *pmac_backlight;
 extern struct mutex pmac_backlight_mutex;
 
-extern void pmac_backlight_calc_curve(struct fb_info*);
 extern int pmac_backlight_curve_lookup(struct fb_info *info, int value);
 
 extern int pmac_has_backlight_type(const char *type);
 
-extern void pmac_backlight_key_up(void);
-extern void pmac_backlight_key_down(void);
+extern void pmac_backlight_key(int direction);
+static inline void pmac_backlight_key_up(void)
+{
+        pmac_backlight_key(0);
+}
+static inline void pmac_backlight_key_down(void)
+{
+        pmac_backlight_key(1);
+}
 
+extern void pmac_backlight_set_legacy_brightness_pmu(int brightness);
 extern int pmac_backlight_set_legacy_brightness(int brightness);
 extern int pmac_backlight_get_legacy_brightness(void);
 
+extern void pmac_backlight_enable(void);
+extern void pmac_backlight_disable(void);
+
 #endif /* __KERNEL__ */
 #endif
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
index 76e2f08c3c83..c341063d0804 100644
--- a/include/asm-powerpc/bitops.h
+++ b/include/asm-powerpc/bitops.h
@@ -65,8 +65,8 @@ static __inline__ void set_bit(int nr, volatile unsigned long *addr)
         PPC405_ERR77(0,%3)
         PPC_STLCX "%0,0,%3\n"
         "bne-   1b"
-        : "=&r"(old), "=m"(*p)
-        : "r"(mask), "r"(p), "m"(*p)
+        : "=&r" (old), "+m" (*p)
+        : "r" (mask), "r" (p)
         : "cc" );
 }
 
@@ -82,8 +82,8 @@ static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
         PPC405_ERR77(0,%3)
         PPC_STLCX "%0,0,%3\n"
         "bne-   1b"
-        : "=&r"(old), "=m"(*p)
-        : "r"(mask), "r"(p), "m"(*p)
+        : "=&r" (old), "+m" (*p)
+        : "r" (mask), "r" (p)
         : "cc" );
 }
 
@@ -99,8 +99,8 @@ static __inline__ void change_bit(int nr, volatile unsigned long *addr)
         PPC405_ERR77(0,%3)
         PPC_STLCX "%0,0,%3\n"
         "bne-   1b"
-        : "=&r"(old), "=m"(*p)
-        : "r"(mask), "r"(p), "m"(*p)
+        : "=&r" (old), "+m" (*p)
+        : "r" (mask), "r" (p)
         : "cc" );
 }
 
@@ -179,8 +179,8 @@ static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
         "or     %0,%0,%2\n"
         PPC_STLCX "%0,0,%3\n"
         "bne-   1b"
-        : "=&r" (old), "=m" (*addr)
-        : "r" (mask), "r" (addr), "m" (*addr)
+        : "=&r" (old), "+m" (*addr)
+        : "r" (mask), "r" (addr)
         : "cc");
 }
 
diff --git a/include/asm-powerpc/eeh.h b/include/asm-powerpc/eeh.h
index 4df3e80118f4..6a784396660b 100644
--- a/include/asm-powerpc/eeh.h
+++ b/include/asm-powerpc/eeh.h
@@ -205,6 +205,7 @@ static inline void eeh_memset_io(volatile void __iomem *addr, int c,
         lc |= lc << 8;
         lc |= lc << 16;
 
+        __asm__ __volatile__ ("sync" : : : "memory");
         while(n && !EEH_CHECK_ALIGN(p, 4)) {
                 *((volatile u8 *)p) = c;
                 p++;
@@ -229,6 +230,7 @@ static inline void eeh_memcpy_fromio(void *dest, const volatile void __iomem *sr
         void *destsave = dest;
         unsigned long nsave = n;
 
+        __asm__ __volatile__ ("sync" : : : "memory");
         while(n && (!EEH_CHECK_ALIGN(vsrc, 4) || !EEH_CHECK_ALIGN(dest, 4))) {
                 *((u8 *)dest) = *((volatile u8 *)vsrc);
                 __asm__ __volatile__ ("eieio" : : : "memory");
@@ -266,6 +268,7 @@ static inline void eeh_memcpy_toio(volatile void __iomem *dest, const void *src,
 {
         void *vdest = (void __force *) dest;
 
+        __asm__ __volatile__ ("sync" : : : "memory");
         while(n && (!EEH_CHECK_ALIGN(vdest, 4) || !EEH_CHECK_ALIGN(src, 4))) {
                 *((volatile u8 *)vdest) = *((u8 *)src);
                 src++;
diff --git a/include/asm-powerpc/futex.h b/include/asm-powerpc/futex.h
index f1b3c00bc1ce..936422e54891 100644
--- a/include/asm-powerpc/futex.h
+++ b/include/asm-powerpc/futex.h
@@ -84,7 +84,33 @@ static inline int futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
 static inline int
 futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
 {
-        return -ENOSYS;
+        int prev;
+
+        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
+                return -EFAULT;
+
+        __asm__ __volatile__ (
+        LWSYNC_ON_SMP
+"1:     lwarx   %0,0,%2         # futex_atomic_cmpxchg_inatomic\n\
+        cmpw    0,%0,%3\n\
+        bne-    3f\n"
+        PPC405_ERR77(0,%2)
+"2:     stwcx.  %4,0,%2\n\
+        bne-    1b\n"
+        ISYNC_ON_SMP
+"3:     .section .fixup,\"ax\"\n\
+4:      li      %0,%5\n\
+        b       3b\n\
+        .previous\n\
+        .section __ex_table,\"a\"\n\
+        .align 3\n\
+        " PPC_LONG "1b,4b,2b,4b\n\
+        .previous" \
+        : "=&r" (prev), "+m" (*uaddr)
+        : "r" (uaddr), "r" (oldval), "r" (newval), "i" (-EFAULT)
+        : "cc", "memory");
+
+        return prev;
 }
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index a9496f34b048..212428db0d8b 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -19,6 +19,7 @@ extern int check_legacy_ioport(unsigned long base_port);
 #include <linux/compiler.h>
 #include <asm/page.h>
 #include <asm/byteorder.h>
+#include <asm/paca.h>
 #ifdef CONFIG_PPC_ISERIES 
 #include <asm/iseries/iseries_io.h>
 #endif  
@@ -72,6 +73,9 @@ extern unsigned long pci_io_base;
  * Neither do the standard versions now, these are just here
  * for older code.
  */
+#define insb(port, buf, ns)     _insb((u8 __iomem *)((port)+pci_io_base), (buf), (ns))
+#define insw(port, buf, ns)     _insw_ns((u8 __iomem *)((port)+pci_io_base), (buf), (ns))
+#define insl(port, buf, nl)     _insl_ns((u8 __iomem *)((port)+pci_io_base), (buf), (nl))
 #define insw_ns(port, buf, ns)  _insw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
 #define insl_ns(port, buf, nl)  _insl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
 #else
@@ -137,12 +141,12 @@ static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
 #define insw_ns(port, buf, ns)  eeh_insw_ns((port), (buf), (ns))
 #define insl_ns(port, buf, nl)  eeh_insl_ns((port), (buf), (nl))
 
+#endif
+
 #define outsb(port, buf, ns)  _outsb((u8 __iomem *)((port)+pci_io_base), (buf), (ns))
 #define outsw(port, buf, ns)  _outsw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
 #define outsl(port, buf, nl)  _outsl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
 
-#endif
-
 #define readb_relaxed(addr) readb(addr)
 #define readw_relaxed(addr) readw(addr)
 #define readl_relaxed(addr) readl(addr)
@@ -159,7 +163,11 @@ extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, int ns);
 extern void _insl_ns(volatile u32 __iomem *port, void *buf, int nl);
 extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, int nl);
 
-#define mmiowb()
+static inline void mmiowb(void)
+{
+        __asm__ __volatile__ ("sync" : : : "memory");
+        get_paca()->io_sync = 0;
+}
 
 /*
  * output pause versions need a delay at least for the
@@ -275,22 +283,23 @@ static inline int in_8(const volatile unsigned char __iomem *addr)
 {
         int ret;
 
-        __asm__ __volatile__("lbz%U1%X1 %0,%1; twi 0,%0,0; isync"
+        __asm__ __volatile__("sync; lbz%U1%X1 %0,%1; twi 0,%0,0; isync"
                              : "=r" (ret) : "m" (*addr));
         return ret;
 }
 
 static inline void out_8(volatile unsigned char __iomem *addr, int val)
 {
-        __asm__ __volatile__("stb%U0%X0 %1,%0; sync"
+        __asm__ __volatile__("sync; stb%U0%X0 %1,%0"
                              : "=m" (*addr) : "r" (val));
+        get_paca()->io_sync = 1;
 }
 
 static inline int in_le16(const volatile unsigned short __iomem *addr)
 {
         int ret;
 
-        __asm__ __volatile__("lhbrx %0,0,%1; twi 0,%0,0; isync"
+        __asm__ __volatile__("sync; lhbrx %0,0,%1; twi 0,%0,0; isync"
                              : "=r" (ret) : "r" (addr), "m" (*addr));
         return ret;
 }
@@ -299,28 +308,30 @@ static inline int in_be16(const volatile unsigned short __iomem *addr)
 {
         int ret;
 
-        __asm__ __volatile__("lhz%U1%X1 %0,%1; twi 0,%0,0; isync"
+        __asm__ __volatile__("sync; lhz%U1%X1 %0,%1; twi 0,%0,0; isync"
                              : "=r" (ret) : "m" (*addr));
         return ret;
 }
 
 static inline void out_le16(volatile unsigned short __iomem *addr, int val)
 {
-        __asm__ __volatile__("sthbrx %1,0,%2; sync"
+        __asm__ __volatile__("sync; sthbrx %1,0,%2"
                              : "=m" (*addr) : "r" (val), "r" (addr));
+        get_paca()->io_sync = 1;
 }
 
 static inline void out_be16(volatile unsigned short __iomem *addr, int val)
 {
-        __asm__ __volatile__("sth%U0%X0 %1,%0; sync"
+        __asm__ __volatile__("sync; sth%U0%X0 %1,%0"
                              : "=m" (*addr) : "r" (val));
+        get_paca()->io_sync = 1;
 }
 
 static inline unsigned in_le32(const volatile unsigned __iomem *addr)
 {
         unsigned ret;
 
-        __asm__ __volatile__("lwbrx %0,0,%1; twi 0,%0,0; isync"
+        __asm__ __volatile__("sync; lwbrx %0,0,%1; twi 0,%0,0; isync"
                              : "=r" (ret) : "r" (addr), "m" (*addr));
         return ret;
 }
@@ -329,21 +340,23 @@ static inline unsigned in_be32(const volatile unsigned __iomem *addr)
 {
         unsigned ret;
 
-        __asm__ __volatile__("lwz%U1%X1 %0,%1; twi 0,%0,0; isync"
+        __asm__ __volatile__("sync; lwz%U1%X1 %0,%1; twi 0,%0,0; isync"
                              : "=r" (ret) : "m" (*addr));
         return ret;
 }
 
 static inline void out_le32(volatile unsigned __iomem *addr, int val)
 {
-        __asm__ __volatile__("stwbrx %1,0,%2; sync" : "=m" (*addr)
+        __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr)
                              : "r" (val), "r" (addr));
+        get_paca()->io_sync = 1;
 }
 
 static inline void out_be32(volatile unsigned __iomem *addr, int val)
 {
-        __asm__ __volatile__("stw%U0%X0 %1,%0; sync"
+        __asm__ __volatile__("sync; stw%U0%X0 %1,%0"
                              : "=m" (*addr) : "r" (val));
+        get_paca()->io_sync = 1;
 }
 
 static inline unsigned long in_le64(const volatile unsigned long __iomem *addr)
@@ -351,6 +364,7 @@ static inline unsigned long in_le64(const volatile unsigned long __iomem *addr)
         unsigned long tmp, ret;
 
         __asm__ __volatile__(
+                             "sync\n"
                              "ld %1,0(%2)\n"
                              "twi 0,%1,0\n"
                              "isync\n"
@@ -369,7 +383,7 @@ static inline unsigned long in_be64(const volatile unsigned long __iomem *addr)
 {
         unsigned long ret;
 
-        __asm__ __volatile__("ld%U1%X1 %0,%1; twi 0,%0,0; isync"
+        __asm__ __volatile__("sync; ld%U1%X1 %0,%1; twi 0,%0,0; isync"
                              : "=r" (ret) : "m" (*addr));
         return ret;
 }
@@ -386,14 +400,16 @@ static inline void out_le64(volatile unsigned long __iomem *addr, unsigned long
                              "rldicl %1,%1,32,0\n"
                              "rlwimi %0,%1,8,8,31\n"
                              "rlwimi %0,%1,24,16,23\n"
-                             "std %0,0(%3)\n"
-                             "sync"
+                             "sync\n"
+                             "std %0,0(%3)"
                              : "=&r" (tmp) , "=&r" (val) : "1" (val) , "b" (addr) , "m" (*addr));
+        get_paca()->io_sync = 1;
 }
 
 static inline void out_be64(volatile unsigned long __iomem *addr, unsigned long val)
 {
-        __asm__ __volatile__("std%U0%X0 %1,%0; sync" : "=m" (*addr) : "r" (val));
+        __asm__ __volatile__("sync; std%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
+        get_paca()->io_sync = 1;
 }
 
 #ifndef CONFIG_PPC_ISERIES 
diff --git a/include/asm-powerpc/ipic.h b/include/asm-powerpc/ipic.h
index 0fe396a2b666..53079ec3a515 100644
--- a/include/asm-powerpc/ipic.h
+++ b/include/asm-powerpc/ipic.h
@@ -69,9 +69,6 @@ enum ipic_mcp_irq {
         IPIC_MCP_MU   = 7,
 };
 
-extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
-                unsigned int irq_offset,
-                unsigned char *senses, unsigned int senses_count);
 extern int ipic_set_priority(unsigned int irq, unsigned int priority);
 extern void ipic_set_highest_priority(unsigned int irq);
 extern void ipic_set_default_priority(void);
@@ -79,7 +76,16 @@ extern void ipic_enable_mcp(enum ipic_mcp_irq mcp_irq);
 extern void ipic_disable_mcp(enum ipic_mcp_irq mcp_irq);
 extern u32 ipic_get_mcp_status(void);
 extern void ipic_clear_mcp_status(u32 mask);
+
+#ifdef CONFIG_PPC_MERGE
+extern void ipic_init(struct device_node *node, unsigned int flags);
+extern unsigned int ipic_get_irq(struct pt_regs *regs);
+#else
+extern void ipic_init(phys_addr_t phys_addr, unsigned int flags,
+                unsigned int irq_offset,
+                unsigned char *senses, unsigned int senses_count);
 extern int ipic_get_irq(struct pt_regs *regs);
+#endif
 
 #endif /* __ASM_IPIC_H__ */
 #endif /* __KERNEL__ */
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index e05754752028..d903a62959da 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -83,25 +83,24 @@ struct irq_host_ops {
         int (*match)(struct irq_host *h, struct device_node *node);
 
         /* Create or update a mapping between a virtual irq number and a hw
-         * irq number. This can be called several times for the same mapping
-         * but with different flags, though unmap shall always be called
-         * before the virq->hw mapping is changed.
+         * irq number. This is called only once for a given mapping.
          */
-        int (*map)(struct irq_host *h, unsigned int virq,
-                   irq_hw_number_t hw, unsigned int flags);
+        int (*map)(struct irq_host *h, unsigned int virq, irq_hw_number_t hw);
 
         /* Dispose of such a mapping */
         void (*unmap)(struct irq_host *h, unsigned int virq);
 
         /* Translate device-tree interrupt specifier from raw format coming
          * from the firmware to a irq_hw_number_t (interrupt line number) and
-         * trigger flags that can be passed to irq_create_mapping().
-         * If no translation is provided, raw format is assumed to be one cell
-         * for interrupt line and default sense.
+         * type (sense) that can be passed to set_irq_type(). In the absence
+         * of this callback, irq_create_of_mapping() and irq_of_parse_and_map()
+         * will return the hw number in the first cell and IRQ_TYPE_NONE for
+         * the type (which amount to keeping whatever default value the
+         * interrupt controller has for that line)
          */
         int (*xlate)(struct irq_host *h, struct device_node *ctrler,
                      u32 *intspec, unsigned int intsize,
-                     irq_hw_number_t *out_hwirq, unsigned int *out_flags);
+                     irq_hw_number_t *out_hwirq, unsigned int *out_type);
 };
 
 struct irq_host {
@@ -193,25 +192,14 @@ extern void irq_set_virq_count(unsigned int count);
  * irq_create_mapping - Map a hardware interrupt into linux virq space
  * @host: host owning this hardware interrupt or NULL for default host
  * @hwirq: hardware irq number in that host space
- * @flags: flags passed to the controller. contains the trigger type among
- *         others. Use IRQ_TYPE_* defined in include/linux/irq.h
  *
  * Only one mapping per hardware interrupt is permitted. Returns a linux
- * virq number. The flags can be used to provide sense information to the
- * controller (typically extracted from the device-tree). If no information
- * is passed, the controller defaults will apply (for example, xics can only
- * do edge so flags are irrelevant for some pseries specific irqs).
- *
- * The device-tree generally contains the trigger info in an encoding that is
- * specific to a given type of controller. In that case, you can directly use
- * host->ops->trigger_xlate() to translate that.
- *
- * It is recommended that new PICs that don't have existing OF bindings chose
- * to use a representation of triggers identical to linux.
+ * virq number.
+ * If the sense/trigger is to be specified, set_irq_type() should be called
+ * on the number returned from that call.
  */
 extern unsigned int irq_create_mapping(struct irq_host *host,
-                                       irq_hw_number_t hwirq,
-                                       unsigned int flags);
+                                       irq_hw_number_t hwirq);
 
 
 /***
@@ -295,7 +283,7 @@ extern void irq_free_virt(unsigned int virq, unsigned int count);
  *
  * This function is identical to irq_create_mapping except that it takes
  * as input informations straight from the device-tree (typically the results
- * of the of_irq_map_*() functions
+ * of the of_irq_map_*() functions.
  */
 extern unsigned int irq_create_of_mapping(struct device_node *controller,
                                           u32 *intspec, unsigned int intsize);
diff --git a/include/asm-powerpc/kdump.h b/include/asm-powerpc/kdump.h
index dc1574c945f8..10e8eb1e6f4f 100644
--- a/include/asm-powerpc/kdump.h
+++ b/include/asm-powerpc/kdump.h
@@ -7,7 +7,7 @@
 /* How many bytes to reserve at zero for kdump. The reserve limit should
  * be greater or equal to the trampoline's end address.
  * Reserve to the end of the FWNMI area, see head_64.S */
-#define KDUMP_RESERVE_LIMIT     0x8000
+#define KDUMP_RESERVE_LIMIT     0x10000 /* 64K */
 
 #ifdef CONFIG_CRASH_DUMP
 
diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h
index 8f7fd5cfec34..11cbdf81fd2e 100644
--- a/include/asm-powerpc/kexec.h
+++ b/include/asm-powerpc/kexec.h
@@ -32,6 +32,7 @@
 #endif
 
 #ifndef __ASSEMBLY__
+#include <linux/cpumask.h>
 
 #ifdef CONFIG_KEXEC
 
@@ -109,7 +110,6 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
 
 #define MAX_NOTE_BYTES 1024
 
-#ifdef __powerpc64__
 extern void kexec_smp_wait(void);       /* get and clear naca physid, wait for
                                           master to copy new code to 0 */
 extern int crashing_cpu;
@@ -119,7 +119,6 @@ static inline int kexec_sr_activated(int cpu)
 {
         return cpu_isset(cpu,cpus_in_sr);
 }
-#endif /* __powerpc64 __ */
 
 struct kimage;
 struct pt_regs;
diff --git a/include/asm-powerpc/kprobes.h b/include/asm-powerpc/kprobes.h
index 2d0af52c823d..34e1f89a5fa0 100644
--- a/include/asm-powerpc/kprobes.h
+++ b/include/asm-powerpc/kprobes.h
@@ -51,6 +51,7 @@ typedef unsigned int kprobe_opcode_t;
 
 #define ARCH_SUPPORTS_KRETPROBES
 #define  ARCH_INACTIVE_KPROBE_COUNT 1
+#define flush_insn_slot(p)      do { } while (0)
 
 void kretprobe_trampoline(void);
 extern void arch_remove_kprobe(struct kprobe *p);
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
index f260382739fa..b85df45b1a84 100644
--- a/include/asm-powerpc/mpc86xx.h
+++ b/include/asm-powerpc/mpc86xx.h
@@ -23,8 +23,6 @@
 #define _ISA_MEM_BASE   isa_mem_base
 #ifdef CONFIG_PCI
 #define PCI_DRAM_OFFSET pci_dram_offset
-#else
-#define PCI_DRAM_OFFSET 0
 #endif
 
 #define CPU0_BOOT_RELEASE 0x01000000
@@ -33,7 +31,6 @@
 #define MCM_PORT_CONFIG_OFFSET 0x1010
 
 /* Offset from CCSRBAR */
-#define MPC86xx_OPENPIC_OFFSET  (0x40000)
 #define MPC86xx_MCM_OFFSET      (0x00000)
 #define MPC86xx_MCM_SIZE        (0x02000)
 
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index eb241c99c457..a9f9604b9eff 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -41,6 +41,7 @@
 #define MPIC_GREG_IPI_VECTOR_PRI_1      0x000b0
 #define MPIC_GREG_IPI_VECTOR_PRI_2      0x000c0
 #define MPIC_GREG_IPI_VECTOR_PRI_3      0x000d0
+#define MPIC_GREG_IPI_STRIDE            0x10
 #define MPIC_GREG_SPURIOUS              0x000e0
 #define MPIC_GREG_TIMER_FREQ            0x000f0
 
@@ -68,6 +69,7 @@
 #define MPIC_CPU_IPI_DISPATCH_1         0x00050
 #define MPIC_CPU_IPI_DISPATCH_2         0x00060
 #define MPIC_CPU_IPI_DISPATCH_3         0x00070
+#define MPIC_CPU_IPI_DISPATCH_STRIDE    0x00010
 #define MPIC_CPU_CURRENT_TASK_PRI       0x00080
 #define         MPIC_CPU_TASKPRI_MASK                   0x0000000f
 #define MPIC_CPU_WHOAMI                 0x00090
@@ -114,6 +116,103 @@
 #define MPIC_VEC_TIMER_1        248
 #define MPIC_VEC_TIMER_0        247
 
+/*
+ * Tsi108 implementation of MPIC has many differences from the original one
+ */
+
+/*
+ * Global registers
+ */
+
+#define TSI108_GREG_BASE                0x00000
+#define TSI108_GREG_FEATURE_0           0x00000
+#define TSI108_GREG_GLOBAL_CONF_0       0x00004
+#define TSI108_GREG_VENDOR_ID           0x0000c
+#define TSI108_GREG_IPI_VECTOR_PRI_0    0x00204         /* Doorbell 0 */
+#define TSI108_GREG_IPI_STRIDE          0x0c
+#define TSI108_GREG_SPURIOUS            0x00010
+#define TSI108_GREG_TIMER_FREQ          0x00014
+
+/*
+ * Timer registers
+ */
+#define TSI108_TIMER_BASE               0x0030
+#define TSI108_TIMER_STRIDE             0x10
+#define TSI108_TIMER_CURRENT_CNT        0x00000
+#define TSI108_TIMER_BASE_CNT           0x00004
+#define TSI108_TIMER_VECTOR_PRI         0x00008
+#define TSI108_TIMER_DESTINATION        0x0000c
+
+/*
+ * Per-Processor registers
+ */
+#define TSI108_CPU_BASE                 0x00300
+#define TSI108_CPU_STRIDE               0x00040
+#define TSI108_CPU_IPI_DISPATCH_0       0x00200
+#define TSI108_CPU_IPI_DISPATCH_STRIDE  0x00000
+#define TSI108_CPU_CURRENT_TASK_PRI     0x00000
+#define TSI108_CPU_WHOAMI               0xffffffff
+#define TSI108_CPU_INTACK               0x00004
+#define TSI108_CPU_EOI                  0x00008
+
+/*
+ * Per-source registers
+ */
+#define TSI108_IRQ_BASE                 0x00100
+#define TSI108_IRQ_STRIDE               0x00008
+#define TSI108_IRQ_VECTOR_PRI           0x00000
+#define TSI108_VECPRI_VECTOR_MASK       0x000000ff
+#define TSI108_VECPRI_POLARITY_POSITIVE 0x01000000
+#define TSI108_VECPRI_POLARITY_NEGATIVE 0x00000000
+#define TSI108_VECPRI_SENSE_LEVEL       0x02000000
+#define TSI108_VECPRI_SENSE_EDGE        0x00000000
+#define TSI108_VECPRI_POLARITY_MASK     0x01000000
+#define TSI108_VECPRI_SENSE_MASK        0x02000000
+#define TSI108_IRQ_DESTINATION          0x00004
+
+/* weird mpic register indices and mask bits in the HW info array */
+enum {
+        MPIC_IDX_GREG_BASE = 0,
+        MPIC_IDX_GREG_FEATURE_0,
+        MPIC_IDX_GREG_GLOBAL_CONF_0,
+        MPIC_IDX_GREG_VENDOR_ID,
+        MPIC_IDX_GREG_IPI_VECTOR_PRI_0,
+        MPIC_IDX_GREG_IPI_STRIDE,
+        MPIC_IDX_GREG_SPURIOUS,
+        MPIC_IDX_GREG_TIMER_FREQ,
+
+        MPIC_IDX_TIMER_BASE,
+        MPIC_IDX_TIMER_STRIDE,
+        MPIC_IDX_TIMER_CURRENT_CNT,
+        MPIC_IDX_TIMER_BASE_CNT,
+        MPIC_IDX_TIMER_VECTOR_PRI,
+        MPIC_IDX_TIMER_DESTINATION,
+
+        MPIC_IDX_CPU_BASE,
+        MPIC_IDX_CPU_STRIDE,
+        MPIC_IDX_CPU_IPI_DISPATCH_0,
+        MPIC_IDX_CPU_IPI_DISPATCH_STRIDE,
+        MPIC_IDX_CPU_CURRENT_TASK_PRI,
+        MPIC_IDX_CPU_WHOAMI,
+        MPIC_IDX_CPU_INTACK,
+        MPIC_IDX_CPU_EOI,
+
+        MPIC_IDX_IRQ_BASE,
+        MPIC_IDX_IRQ_STRIDE,
+        MPIC_IDX_IRQ_VECTOR_PRI,
+
+        MPIC_IDX_VECPRI_VECTOR_MASK,
+        MPIC_IDX_VECPRI_POLARITY_POSITIVE,
+        MPIC_IDX_VECPRI_POLARITY_NEGATIVE,
+        MPIC_IDX_VECPRI_SENSE_LEVEL,
+        MPIC_IDX_VECPRI_SENSE_EDGE,
+        MPIC_IDX_VECPRI_POLARITY_MASK,
+        MPIC_IDX_VECPRI_SENSE_MASK,
+        MPIC_IDX_IRQ_DESTINATION,
+        MPIC_IDX_END
+};
+
+
 #ifdef CONFIG_MPIC_BROKEN_U3
 /* Fixup table entry */
 struct mpic_irq_fixup
@@ -171,15 +270,29 @@ struct mpic
         volatile u32 __iomem    *cpuregs[MPIC_MAX_CPUS];
         volatile u32 __iomem    *isus[MPIC_MAX_ISU];
 
+#ifdef CONFIG_MPIC_WEIRD
+        /* Pointer to HW info array */
+        u32                     *hw_set;
+#endif
+
         /* link */
         struct mpic             *next;
 };
 
+/*
+ * MPIC flags (passed to mpic_alloc)
+ *
+ * The top 4 bits contain an MPIC bhw id that is used to index the
+ * register offsets and some masks when CONFIG_MPIC_WEIRD is set.
+ * Note setting any ID (leaving those bits to 0) means standard MPIC
+ */
+
 /* This is the primary controller, only that one has IPIs and
  * has afinity control. A non-primary MPIC always uses CPU0
  * registers only
  */
 #define MPIC_PRIMARY                    0x00000001
+
 /* Set this for a big-endian MPIC */
 #define MPIC_BIG_ENDIAN                 0x00000002
 /* Broken U3 MPIC */
@@ -188,6 +301,18 @@ struct mpic
 #define MPIC_BROKEN_IPI                 0x00000008
 /* MPIC wants a reset */
 #define MPIC_WANTS_RESET                0x00000010
+/* Spurious vector requires EOI */
+#define MPIC_SPV_EOI                    0x00000020
+/* No passthrough disable */
+#define MPIC_NO_PTHROU_DIS              0x00000040
+
+/* MPIC HW modification ID */
+#define MPIC_REGSET_MASK                0xf0000000
+#define MPIC_REGSET(val)                (((val) & 0xf ) << 28)
+#define MPIC_GET_REGSET(flags)          (((flags) >> 28) & 0xf)
+
+#define MPIC_REGSET_STANDARD            MPIC_REGSET(0)  /* Original MPIC */
+#define MPIC_REGSET_TSI108              MPIC_REGSET(1)  /* Tsi108/109 PIC */
 
 /* Allocate the controller structure and setup the linux irq descs
  * for the range if interrupts passed in. No HW initialization is
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
index 2d4585f06209..3d5d590bc4b0 100644
--- a/include/asm-powerpc/paca.h
+++ b/include/asm-powerpc/paca.h
@@ -93,6 +93,7 @@ struct paca_struct {
         u64 saved_r1;                   /* r1 save for RTAS calls */
         u64 saved_msr;                  /* MSR saved here by enter_rtas */
         u8 proc_enabled;                /* irq soft-enable flag */
+        u8 io_sync;                     /* writel() needs spin_unlock sync */
 
         /* Stuff for accurate time accounting */
         u64 user_time;                  /* accumulated usermode TB ticks */
diff --git a/include/asm-powerpc/pgalloc.h b/include/asm-powerpc/pgalloc.h
index 9f0917c68659..ae63db7b3e7d 100644
--- a/include/asm-powerpc/pgalloc.h
+++ b/include/asm-powerpc/pgalloc.h
@@ -117,7 +117,7 @@ static inline void pte_free(struct page *ptepage)
         pte_free_kernel(page_address(ptepage));
 }
 
-#define PGF_CACHENUM_MASK       0xf
+#define PGF_CACHENUM_MASK       0x3
 
 typedef struct pgtable_free {
         unsigned long val;
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index b095a285c84b..d0fa1b9aed35 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -276,6 +276,7 @@ extern void of_irq_map_init(unsigned int flags);
  * of_irq_map_raw - Low level interrupt tree parsing
  * @parent:     the device interrupt parent
  * @intspec:    interrupt specifier ("interrupts" property of the device)
+ * @ointsize:   size of the passed in interrupt specifier
  * @addr:       address specifier (start of "reg" property of the device)
  * @out_irq:    structure of_irq filled by this function
  *
@@ -288,7 +289,8 @@ extern void of_irq_map_init(unsigned int flags);
  *
  */
 
-extern int of_irq_map_raw(struct device_node *parent, u32 *intspec, u32 *addr,
+extern int of_irq_map_raw(struct device_node *parent, u32 *intspec,
+                          u32 ointsize, u32 *addr,
                           struct of_irq *out_irq);
 
 
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
index a33c6acffa61..82a27e9a041f 100644
--- a/include/asm-powerpc/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -170,6 +170,7 @@ extern int rtas_get_sensor(int sensor, int index, int *state);
 extern int rtas_get_power_level(int powerdomain, int *level);
 extern int rtas_set_power_level(int powerdomain, int level, int *setlevel);
 extern int rtas_set_indicator(int indicator, int index, int new_value);
+extern int rtas_set_indicator_fast(int indicator, int index, int new_value);
 extern void rtas_progress(char *s, unsigned short hex);
 extern void rtas_initialize(void);
 
diff --git a/include/asm-powerpc/spinlock.h b/include/asm-powerpc/spinlock.h
index 895cb6d3a42a..c31e4382a775 100644
--- a/include/asm-powerpc/spinlock.h
+++ b/include/asm-powerpc/spinlock.h
@@ -36,6 +36,19 @@
 #define LOCK_TOKEN      1
 #endif
 
+#if defined(CONFIG_PPC64) && defined(CONFIG_SMP)
+#define CLEAR_IO_SYNC   (get_paca()->io_sync = 0)
+#define SYNC_IO         do {                                            \
+                                if (unlikely(get_paca()->io_sync)) {    \
+                                        mb();                           \
+                                        get_paca()->io_sync = 0;        \
+                                }                                       \
+                        } while (0)
+#else
+#define CLEAR_IO_SYNC
+#define SYNC_IO
+#endif
+
 /*
  * This returns the old value in the lock, so we succeeded
  * in getting the lock if the return value is 0.
@@ -61,6 +74,7 @@ static __inline__ unsigned long __spin_trylock(raw_spinlock_t *lock)
 
 static int __inline__ __raw_spin_trylock(raw_spinlock_t *lock)
 {
+        CLEAR_IO_SYNC;
         return __spin_trylock(lock) == 0;
 }
 
@@ -91,6 +105,7 @@ extern void __rw_yield(raw_rwlock_t *lock);
 
 static void __inline__ __raw_spin_lock(raw_spinlock_t *lock)
 {
+        CLEAR_IO_SYNC;
         while (1) {
                 if (likely(__spin_trylock(lock) == 0))
                         break;
@@ -107,6 +122,7 @@ static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long
 {
         unsigned long flags_dis;
 
+        CLEAR_IO_SYNC;
         while (1) {
                 if (likely(__spin_trylock(lock) == 0))
                         break;
@@ -124,6 +140,7 @@ static void __inline__ __raw_spin_lock_flags(raw_spinlock_t *lock, unsigned long
 
 static __inline__ void __raw_spin_unlock(raw_spinlock_t *lock)
 {
+        SYNC_IO;
         __asm__ __volatile__("# __raw_spin_unlock\n\t"
                                 LWSYNC_ON_SMP: : :"memory");
         lock->slock = 0;
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index d075725bf444..4c9f5229e833 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -39,7 +39,6 @@
 #define read_barrier_depends()  do { } while(0)
 
 #define set_mb(var, value)      do { var = value; mb(); } while (0)
-#define set_wmb(var, value)     do { var = value; wmb(); } while (0)
 
 #ifdef __KERNEL__
 #ifdef CONFIG_SMP
@@ -54,6 +53,15 @@
 #define smp_read_barrier_depends()      do { } while(0)
 #endif /* CONFIG_SMP */
 
+/*
+ * This is a barrier which prevents following instructions from being
+ * started until the value of the argument x is known.  For example, if
+ * x is a variable loaded from memory, this prevents following
+ * instructions from being executed until the load has been performed.
+ */
+#define data_barrier(x) \
+        asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
+
 struct task_struct;
 struct pt_regs;
 
@@ -220,8 +228,8 @@ __xchg_u32(volatile void *p, unsigned long val)
 "       stwcx.  %3,0,%2 \n\
         bne-    1b"
         ISYNC_ON_SMP
-        : "=&r" (prev), "=m" (*(volatile unsigned int *)p)
-        : "r" (p), "r" (val), "m" (*(volatile unsigned int *)p)
+        : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
+        : "r" (p), "r" (val)
         : "cc", "memory");
 
         return prev;
@@ -240,8 +248,8 @@ __xchg_u64(volatile void *p, unsigned long val)
 "       stdcx.  %3,0,%2 \n\
         bne-    1b"
         ISYNC_ON_SMP
-        : "=&r" (prev), "=m" (*(volatile unsigned long *)p)
-        : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p)
+        : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
+        : "r" (p), "r" (val)
         : "cc", "memory");
 
         return prev;
@@ -299,8 +307,8 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
         ISYNC_ON_SMP
         "\n\
 2:"
-        : "=&r" (prev), "=m" (*p)
-        : "r" (p), "r" (old), "r" (new), "m" (*p)
+        : "=&r" (prev), "+m" (*p)
+        : "r" (p), "r" (old), "r" (new)
         : "cc", "memory");
 
         return prev;
@@ -322,8 +330,8 @@ __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
         ISYNC_ON_SMP
         "\n\
 2:"
-        : "=&r" (prev), "=m" (*p)
-        : "r" (p), "r" (old), "r" (new), "m" (*p)
+        : "=&r" (prev), "+m" (*p)
+        : "r" (p), "r" (old), "r" (new)
         : "cc", "memory");
 
         return prev;
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
index dcde4410348d..5785ac4737b5 100644
--- a/include/asm-powerpc/time.h
+++ b/include/asm-powerpc/time.h
@@ -30,10 +30,6 @@ extern unsigned long tb_ticks_per_usec;
 extern unsigned long tb_ticks_per_sec;
 extern u64 tb_to_xs;
 extern unsigned      tb_to_us;
-extern unsigned long tb_last_stamp;
-extern u64 tb_last_jiffy;
-
-DECLARE_PER_CPU(unsigned long, last_jiffy);
 
 struct rtc_time;
 extern void to_tm(int tim, struct rtc_time * tm);
diff --git a/include/asm-powerpc/tsi108.h b/include/asm-powerpc/tsi108.h
index c4c278d72f71..2c702d35a7cf 100644
--- a/include/asm-powerpc/tsi108.h
+++ b/include/asm-powerpc/tsi108.h
@@ -1,16 +1,18 @@
 /*
- * include/asm-ppc/tsi108.h
- *
  * common routine and memory layout for Tundra TSI108(Grendel) host bridge
  * memory controller.
  *
  * Author: Jacob Pan (jacob.pan@freescale.com)
  *         Alex Bounine (alexandreb@tundra.com)
- * 2004 (c) Freescale Semiconductor Inc.  This file is licensed under
- * the terms of the GNU General Public License version 2.  This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
+ *
+ * Copyright 2004-2006 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
  */
+
 #ifndef __PPC_KERNEL_TSI108_H
 #define __PPC_KERNEL_TSI108_H
 
diff --git a/include/asm-powerpc/tsi108_irq.h b/include/asm-powerpc/tsi108_irq.h
new file mode 100644
index 000000000000..3e4d04effa57
--- /dev/null
+++ b/include/asm-powerpc/tsi108_irq.h
@@ -0,0 +1,124 @@
+/*
+ * (C) Copyright 2005 Tundra Semiconductor Corp.
+ * Alex Bounine, <alexandreb at tundra.com).
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * definitions for interrupt controller initialization and external interrupt
+ * demultiplexing on TSI108EMU/SVB boards.
+ */
+
+#ifndef _ASM_PPC_TSI108_IRQ_H
+#define _ASM_PPC_TSI108_IRQ_H
+
+/*
+ * Tsi108 interrupts
+ */
+#ifndef TSI108_IRQ_REG_BASE
+#define TSI108_IRQ_REG_BASE             0
+#endif
+
+#define TSI108_IRQ(x)           (TSI108_IRQ_REG_BASE + (x))
+
+#define TSI108_MAX_VECTORS      (36 + 4)        /* 36 sources + PCI INT demux */
+#define MAX_TASK_PRIO   0xF
+
+#define TSI108_IRQ_SPURIOUS     (TSI108_MAX_VECTORS)
+
+#define DEFAULT_PRIO_LVL        10      /* initial priority level */
+
+/* Interrupt vectors assignment to external and internal
+ * sources of requests. */
+
+/* EXTERNAL INTERRUPT SOURCES */
+
+#define IRQ_TSI108_EXT_INT0     TSI108_IRQ(0)   /* External Source at INT[0] */
+#define IRQ_TSI108_EXT_INT1     TSI108_IRQ(1)   /* External Source at INT[1] */
+#define IRQ_TSI108_EXT_INT2     TSI108_IRQ(2)   /* External Source at INT[2] */
+#define IRQ_TSI108_EXT_INT3     TSI108_IRQ(3)   /* External Source at INT[3] */
+
+/* INTERNAL INTERRUPT SOURCES */
+
+#define IRQ_TSI108_RESERVED0    TSI108_IRQ(4)   /* Reserved IRQ */
+#define IRQ_TSI108_RESERVED1    TSI108_IRQ(5)   /* Reserved IRQ */
+#define IRQ_TSI108_RESERVED2    TSI108_IRQ(6)   /* Reserved IRQ */
+#define IRQ_TSI108_RESERVED3    TSI108_IRQ(7)   /* Reserved IRQ */
+#define IRQ_TSI108_DMA0         TSI108_IRQ(8)   /* DMA0 */
+#define IRQ_TSI108_DMA1         TSI108_IRQ(9)   /* DMA1 */
+#define IRQ_TSI108_DMA2         TSI108_IRQ(10)  /* DMA2 */
+#define IRQ_TSI108_DMA3         TSI108_IRQ(11)  /* DMA3 */
+#define IRQ_TSI108_UART0        TSI108_IRQ(12)  /* UART0 */
+#define IRQ_TSI108_UART1        TSI108_IRQ(13)  /* UART1 */
+#define IRQ_TSI108_I2C          TSI108_IRQ(14)  /* I2C */
+#define IRQ_TSI108_GPIO         TSI108_IRQ(15)  /* GPIO */
+#define IRQ_TSI108_GIGE0        TSI108_IRQ(16)  /* GIGE0 */
+#define IRQ_TSI108_GIGE1        TSI108_IRQ(17)  /* GIGE1 */
+#define IRQ_TSI108_RESERVED4    TSI108_IRQ(18)  /* Reserved IRQ */
+#define IRQ_TSI108_HLP          TSI108_IRQ(19)  /* HLP */
+#define IRQ_TSI108_SDRAM        TSI108_IRQ(20)  /* SDC */
+#define IRQ_TSI108_PROC_IF      TSI108_IRQ(21)  /* Processor IF */
+#define IRQ_TSI108_RESERVED5    TSI108_IRQ(22)  /* Reserved IRQ */
+#define IRQ_TSI108_PCI          TSI108_IRQ(23)  /* PCI/X block */
+
+#define IRQ_TSI108_MBOX0        TSI108_IRQ(24)  /* Mailbox 0 register */
+#define IRQ_TSI108_MBOX1        TSI108_IRQ(25)  /* Mailbox 1 register */
+#define IRQ_TSI108_MBOX2        TSI108_IRQ(26)  /* Mailbox 2 register */
+#define IRQ_TSI108_MBOX3        TSI108_IRQ(27)  /* Mailbox 3 register */
+
+#define IRQ_TSI108_DBELL0       TSI108_IRQ(28)  /* Doorbell 0 */
+#define IRQ_TSI108_DBELL1       TSI108_IRQ(29)  /* Doorbell 1 */
+#define IRQ_TSI108_DBELL2       TSI108_IRQ(30)  /* Doorbell 2 */
+#define IRQ_TSI108_DBELL3       TSI108_IRQ(31)  /* Doorbell 3 */
+
+#define IRQ_TSI108_TIMER0       TSI108_IRQ(32)  /* Global Timer 0 */
+#define IRQ_TSI108_TIMER1       TSI108_IRQ(33)  /* Global Timer 1 */
+#define IRQ_TSI108_TIMER2       TSI108_IRQ(34)  /* Global Timer 2 */
+#define IRQ_TSI108_TIMER3       TSI108_IRQ(35)  /* Global Timer 3 */
+
+/*
+ * PCI bus INTA# - INTD# lines demultiplexor
+ */
+#define IRQ_PCI_INTAD_BASE      TSI108_IRQ(36)
+#define IRQ_PCI_INTA            (IRQ_PCI_INTAD_BASE + 0)
+#define IRQ_PCI_INTB            (IRQ_PCI_INTAD_BASE + 1)
+#define IRQ_PCI_INTC            (IRQ_PCI_INTAD_BASE + 2)
+#define IRQ_PCI_INTD            (IRQ_PCI_INTAD_BASE + 3)
+#define NUM_PCI_IRQS            (4)
+
+/* number of entries in vector dispatch table */
+#define IRQ_TSI108_TAB_SIZE     (TSI108_MAX_VECTORS + 1)
+
+/* Mapping of MPIC outputs to processors' interrupt pins */
+
+#define IDIR_INT_OUT0           0x1
+#define IDIR_INT_OUT1           0x2
+#define IDIR_INT_OUT2           0x4
+#define IDIR_INT_OUT3           0x8
+
+/*---------------------------------------------------------------
+ * IRQ line configuration parameters */
+
+/* Interrupt delivery modes */
+typedef enum {
+        TSI108_IRQ_DIRECTED,
+        TSI108_IRQ_DISTRIBUTED,
+} TSI108_IRQ_MODE;
+#endif                          /*  _ASM_PPC_TSI108_IRQ_H */