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-rw-r--r--include/asm-powerpc/cputable.h48
-rw-r--r--include/asm-powerpc/iseries/it_lp_queue.h40
-rw-r--r--include/asm-powerpc/kdump.h2
-rw-r--r--include/asm-powerpc/kexec.h9
-rw-r--r--include/asm-powerpc/machdep.h2
-rw-r--r--include/asm-powerpc/mmu.h1
-rw-r--r--include/asm-powerpc/mmu_context.h7
-rw-r--r--include/asm-powerpc/mpc86xx.h5
-rw-r--r--include/asm-powerpc/rtas.h3
-rw-r--r--include/asm-powerpc/time.h6
-rw-r--r--include/asm-powerpc/todc.h487
-rw-r--r--include/asm-powerpc/tsi108.h109
-rw-r--r--include/asm-powerpc/udbg.h3
13 files changed, 663 insertions, 59 deletions
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index fab41c280aa1..1ba3c9983614 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -117,38 +117,30 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
117#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) 117#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
118#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) 118#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
119 119
120/*
121 * Add the 64-bit processor unique features in the top half of the word;
122 * on 32-bit, make the names available but defined to be 0.
123 */
120#ifdef __powerpc64__ 124#ifdef __powerpc64__
121/* Add the 64b processor unique features in the top half of the word */ 125#define LONG_ASM_CONST(x) ASM_CONST(x)
122#define CPU_FTR_SLB ASM_CONST(0x0000000100000000)
123#define CPU_FTR_16M_PAGE ASM_CONST(0x0000000200000000)
124#define CPU_FTR_TLBIEL ASM_CONST(0x0000000400000000)
125#define CPU_FTR_NOEXECUTE ASM_CONST(0x0000000800000000)
126#define CPU_FTR_IABR ASM_CONST(0x0000002000000000)
127#define CPU_FTR_MMCRA ASM_CONST(0x0000004000000000)
128#define CPU_FTR_CTRL ASM_CONST(0x0000008000000000)
129#define CPU_FTR_SMT ASM_CONST(0x0000010000000000)
130#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000020000000000)
131#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0000040000000000)
132#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0000100000000000)
133#define CPU_FTR_PAUSE_ZERO ASM_CONST(0x0000200000000000)
134#define CPU_FTR_PURR ASM_CONST(0x0000400000000000)
135#else 126#else
136/* ensure on 32b processors the flags are available for compiling but 127#define LONG_ASM_CONST(x) 0
137 * don't do anything */
138#define CPU_FTR_SLB ASM_CONST(0x0)
139#define CPU_FTR_16M_PAGE ASM_CONST(0x0)
140#define CPU_FTR_TLBIEL ASM_CONST(0x0)
141#define CPU_FTR_NOEXECUTE ASM_CONST(0x0)
142#define CPU_FTR_IABR ASM_CONST(0x0)
143#define CPU_FTR_MMCRA ASM_CONST(0x0)
144#define CPU_FTR_CTRL ASM_CONST(0x0)
145#define CPU_FTR_SMT ASM_CONST(0x0)
146#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0)
147#define CPU_FTR_LOCKLESS_TLBIE ASM_CONST(0x0)
148#define CPU_FTR_CI_LARGE_PAGE ASM_CONST(0x0)
149#define CPU_FTR_PURR ASM_CONST(0x0)
150#endif 128#endif
151 129
130#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
131#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
132#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
133#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
134#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
135#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
136#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
137#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
138#define CPU_FTR_COHERENT_ICACHE LONG_ASM_CONST(0x0000020000000000)
139#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
140#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
141#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
142#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
143
152#ifndef __ASSEMBLY__ 144#ifndef __ASSEMBLY__
153 145
154#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \ 146#define CPU_FTR_PPCAS_ARCH_V2_BASE (CPU_FTR_SLB | \
diff --git a/include/asm-powerpc/iseries/it_lp_queue.h b/include/asm-powerpc/iseries/it_lp_queue.h
index b7c6fc12cce2..284c5a7db3ac 100644
--- a/include/asm-powerpc/iseries/it_lp_queue.h
+++ b/include/asm-powerpc/iseries/it_lp_queue.h
@@ -29,20 +29,20 @@
29 29
30struct HvLpEvent; 30struct HvLpEvent;
31 31
32#define ITMaxLpQueues 8 32#define IT_LP_MAX_QUEUES 8
33 33
34#define NotUsed 0 // Queue will not be used by PLIC 34#define IT_LP_NOT_USED 0 /* Queue will not be used by PLIC */
35#define DedicatedIo 1 // Queue dedicated to IO processor specified 35#define IT_LP_DEDICATED_IO 1 /* Queue dedicated to IO processor specified */
36#define DedicatedLp 2 // Queue dedicated to LP specified 36#define IT_LP_DEDICATED_LP 2 /* Queue dedicated to LP specified */
37#define Shared 3 // Queue shared for both IO and LP 37#define IT_LP_SHARED 3 /* Queue shared for both IO and LP */
38 38
39#define LpEventStackSize 4096 39#define IT_LP_EVENT_STACK_SIZE 4096
40#define LpEventMaxSize 256 40#define IT_LP_EVENT_MAX_SIZE 256
41#define LpEventAlign 64 41#define IT_LP_EVENT_ALIGN 64
42 42
43struct hvlpevent_queue { 43struct hvlpevent_queue {
44/* 44/*
45 * The xSlicCurEventPtr is the pointer to the next event stack entry 45 * The hq_current_event is the pointer to the next event stack entry
46 * that will become valid. The OS must peek at this entry to determine 46 * that will become valid. The OS must peek at this entry to determine
47 * if it is valid. PLIC will set the valid indicator as the very last 47 * if it is valid. PLIC will set the valid indicator as the very last
48 * store into that entry. 48 * store into that entry.
@@ -52,23 +52,23 @@ struct hvlpevent_queue {
52 * location again. 52 * location again.
53 * 53 *
54 * If the event stack fills and there are overflow events, then PLIC 54 * If the event stack fills and there are overflow events, then PLIC
55 * will set the xPlicOverflowIntPending flag in which case the OS will 55 * will set the hq_overflow_pending flag in which case the OS will
56 * have to fetch the additional LP events once they have drained the 56 * have to fetch the additional LP events once they have drained the
57 * event stack. 57 * event stack.
58 * 58 *
59 * The first 16-bytes are known by both the OS and PLIC. The remainder 59 * The first 16-bytes are known by both the OS and PLIC. The remainder
60 * of the cache line is for use by the OS. 60 * of the cache line is for use by the OS.
61 */ 61 */
62 u8 xPlicOverflowIntPending;// 0x00 Overflow events are pending 62 u8 hq_overflow_pending; /* 0x00 Overflow events are pending */
63 u8 xPlicStatus; // 0x01 DedicatedIo or DedicatedLp or NotUsed 63 u8 hq_status; /* 0x01 DedicatedIo or DedicatedLp or NotUsed */
64 u16 xSlicLogicalProcIndex; // 0x02 Logical Proc Index for correlation 64 u16 hq_proc_index; /* 0x02 Logical Proc Index for correlation */
65 u8 xPlicRsvd[12]; // 0x04 65 u8 hq_reserved1[12]; /* 0x04 */
66 char *xSlicCurEventPtr; // 0x10 66 char *hq_current_event; /* 0x10 */
67 char *xSlicLastValidEventPtr; // 0x18 67 char *hq_last_event; /* 0x18 */
68 char *xSlicEventStackPtr; // 0x20 68 char *hq_event_stack; /* 0x20 */
69 u8 xIndex; // 0x28 unique sequential index. 69 u8 hq_index; /* 0x28 unique sequential index. */
70 u8 xSlicRsvd[3]; // 0x29-2b 70 u8 hq_reserved2[3]; /* 0x29-2b */
71 spinlock_t lock; 71 spinlock_t hq_lock;
72}; 72};
73 73
74extern struct hvlpevent_queue hvlpevent_queue; 74extern struct hvlpevent_queue hvlpevent_queue;
diff --git a/include/asm-powerpc/kdump.h b/include/asm-powerpc/kdump.h
index 5a5c3b5ab1e0..dc1574c945f8 100644
--- a/include/asm-powerpc/kdump.h
+++ b/include/asm-powerpc/kdump.h
@@ -15,6 +15,8 @@
15#define KDUMP_TRAMPOLINE_START 0x0100 15#define KDUMP_TRAMPOLINE_START 0x0100
16#define KDUMP_TRAMPOLINE_END 0x3000 16#define KDUMP_TRAMPOLINE_END 0x3000
17 17
18#define KDUMP_MIN_TCE_ENTRIES 2048
19
18#else /* !CONFIG_CRASH_DUMP */ 20#else /* !CONFIG_CRASH_DUMP */
19 21
20#define PHYSICAL_START 0x0 22#define PHYSICAL_START 0x0
diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h
index efe8872ec583..8f7fd5cfec34 100644
--- a/include/asm-powerpc/kexec.h
+++ b/include/asm-powerpc/kexec.h
@@ -112,9 +112,13 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
112#ifdef __powerpc64__ 112#ifdef __powerpc64__
113extern void kexec_smp_wait(void); /* get and clear naca physid, wait for 113extern void kexec_smp_wait(void); /* get and clear naca physid, wait for
114 master to copy new code to 0 */ 114 master to copy new code to 0 */
115extern void __init kexec_setup(void);
116extern int crashing_cpu; 115extern int crashing_cpu;
117extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *)); 116extern void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *));
117extern cpumask_t cpus_in_sr;
118static inline int kexec_sr_activated(int cpu)
119{
120 return cpu_isset(cpu,cpus_in_sr);
121}
118#endif /* __powerpc64 __ */ 122#endif /* __powerpc64 __ */
119 123
120struct kimage; 124struct kimage;
@@ -124,10 +128,13 @@ extern int default_machine_kexec_prepare(struct kimage *image);
124extern void default_machine_crash_shutdown(struct pt_regs *regs); 128extern void default_machine_crash_shutdown(struct pt_regs *regs);
125 129
126extern void machine_kexec_simple(struct kimage *image); 130extern void machine_kexec_simple(struct kimage *image);
131extern void crash_kexec_secondary(struct pt_regs *regs);
127extern int overlaps_crashkernel(unsigned long start, unsigned long size); 132extern int overlaps_crashkernel(unsigned long start, unsigned long size);
128extern void reserve_crashkernel(void); 133extern void reserve_crashkernel(void);
129 134
130#else /* !CONFIG_KEXEC */ 135#else /* !CONFIG_KEXEC */
136static inline int kexec_sr_activated(int cpu) { return 0; }
137static inline void crash_kexec_secondary(struct pt_regs *regs) { }
131 138
132static inline int overlaps_crashkernel(unsigned long start, unsigned long size) 139static inline int overlaps_crashkernel(unsigned long start, unsigned long size)
133{ 140{
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index 73db1f71329d..eba133d149a7 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -81,6 +81,8 @@ struct machdep_calls {
81 void (*tce_free)(struct iommu_table *tbl, 81 void (*tce_free)(struct iommu_table *tbl,
82 long index, 82 long index,
83 long npages); 83 long npages);
84 unsigned long (*tce_get)(struct iommu_table *tbl,
85 long index);
84 void (*tce_flush)(struct iommu_table *tbl); 86 void (*tce_flush)(struct iommu_table *tbl);
85 void (*iommu_dev_setup)(struct pci_dev *dev); 87 void (*iommu_dev_setup)(struct pci_dev *dev);
86 void (*iommu_bus_setup)(struct pci_bus *bus); 88 void (*iommu_bus_setup)(struct pci_bus *bus);
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index 3a5ebe229af5..c3fc7a28e3cd 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -238,7 +238,6 @@ extern int hash_huge_page(struct mm_struct *mm, unsigned long access,
238 unsigned long ea, unsigned long vsid, int local, 238 unsigned long ea, unsigned long vsid, int local,
239 unsigned long trap); 239 unsigned long trap);
240 240
241extern void htab_finish_init(void);
242extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend, 241extern int htab_bolt_mapping(unsigned long vstart, unsigned long vend,
243 unsigned long pstart, unsigned long mode, 242 unsigned long pstart, unsigned long mode,
244 int psize); 243 int psize);
diff --git a/include/asm-powerpc/mmu_context.h b/include/asm-powerpc/mmu_context.h
index 8c6b1a6d944f..083ac917bd29 100644
--- a/include/asm-powerpc/mmu_context.h
+++ b/include/asm-powerpc/mmu_context.h
@@ -25,8 +25,13 @@ static inline void enter_lazy_tlb(struct mm_struct *mm,
25{ 25{
26} 26}
27 27
28/*
29 * The proto-VSID space has 2^35 - 1 segments available for user mappings.
30 * Each segment contains 2^28 bytes. Each context maps 2^44 bytes,
31 * so we can support 2^19-1 contexts (19 == 35 + 28 - 44).
32 */
28#define NO_CONTEXT 0 33#define NO_CONTEXT 0
29#define MAX_CONTEXT (0x100000-1) 34#define MAX_CONTEXT ((1UL << 19) - 1)
30 35
31extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm); 36extern int init_new_context(struct task_struct *tsk, struct mm_struct *mm);
32extern void destroy_context(struct mm_struct *mm); 37extern void destroy_context(struct mm_struct *mm);
diff --git a/include/asm-powerpc/mpc86xx.h b/include/asm-powerpc/mpc86xx.h
index d0a6718d188b..f260382739fa 100644
--- a/include/asm-powerpc/mpc86xx.h
+++ b/include/asm-powerpc/mpc86xx.h
@@ -15,15 +15,10 @@
15#ifndef __ASM_POWERPC_MPC86xx_H__ 15#ifndef __ASM_POWERPC_MPC86xx_H__
16#define __ASM_POWERPC_MPC86xx_H__ 16#define __ASM_POWERPC_MPC86xx_H__
17 17
18#include <linux/config.h>
19#include <asm/mmu.h> 18#include <asm/mmu.h>
20 19
21#ifdef CONFIG_PPC_86xx 20#ifdef CONFIG_PPC_86xx
22 21
23#ifdef CONFIG_MPC8641_HPCN
24#include <platforms/86xx/mpc8641_hpcn.h>
25#endif
26
27#define _IO_BASE isa_io_base 22#define _IO_BASE isa_io_base
28#define _ISA_MEM_BASE isa_mem_base 23#define _ISA_MEM_BASE isa_mem_base
29#ifdef CONFIG_PCI 24#ifdef CONFIG_PCI
diff --git a/include/asm-powerpc/rtas.h b/include/asm-powerpc/rtas.h
index 02e213e3d69f..a33c6acffa61 100644
--- a/include/asm-powerpc/rtas.h
+++ b/include/asm-powerpc/rtas.h
@@ -181,6 +181,9 @@ extern int rtas_set_rtc_time(struct rtc_time *rtc_time);
181extern unsigned int rtas_busy_delay_time(int status); 181extern unsigned int rtas_busy_delay_time(int status);
182extern unsigned int rtas_busy_delay(int status); 182extern unsigned int rtas_busy_delay(int status);
183 183
184extern int early_init_dt_scan_rtas(unsigned long node,
185 const char *uname, int depth, void *data);
186
184extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal); 187extern void pSeries_log_error(char *buf, unsigned int err_type, int fatal);
185 188
186/* Error types logged. */ 189/* Error types logged. */
diff --git a/include/asm-powerpc/time.h b/include/asm-powerpc/time.h
index 4463148c659f..dcde4410348d 100644
--- a/include/asm-powerpc/time.h
+++ b/include/asm-powerpc/time.h
@@ -18,8 +18,9 @@
18#include <linux/percpu.h> 18#include <linux/percpu.h>
19 19
20#include <asm/processor.h> 20#include <asm/processor.h>
21#ifdef CONFIG_PPC64 21#ifdef CONFIG_PPC_ISERIES
22#include <asm/paca.h> 22#include <asm/paca.h>
23#include <asm/firmware.h>
23#include <asm/iseries/hv_call.h> 24#include <asm/iseries/hv_call.h>
24#endif 25#endif
25 26
@@ -177,7 +178,8 @@ static inline void set_dec(int val)
177#ifdef CONFIG_PPC_ISERIES 178#ifdef CONFIG_PPC_ISERIES
178 int cur_dec; 179 int cur_dec;
179 180
180 if (get_lppaca()->shared_proc) { 181 if (firmware_has_feature(FW_FEATURE_ISERIES) &&
182 get_lppaca()->shared_proc) {
181 get_lppaca()->virtual_decr = val; 183 get_lppaca()->virtual_decr = val;
182 cur_dec = get_dec(); 184 cur_dec = get_dec();
183 if (cur_dec > val) 185 if (cur_dec > val)
diff --git a/include/asm-powerpc/todc.h b/include/asm-powerpc/todc.h
new file mode 100644
index 000000000000..60a8c39b8c11
--- /dev/null
+++ b/include/asm-powerpc/todc.h
@@ -0,0 +1,487 @@
1/*
2 * Definitions for the M48Txx and mc146818 series of Time of day/Real Time
3 * Clock chips.
4 *
5 * Author: Mark A. Greer <mgreer@mvista.com>
6 *
7 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 */
12
13/*
14 * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips.
15 * Purpose is to make one generic file that handles all of these chips instead
16 * of every platform implementing the same code over & over again.
17 */
18
19#ifndef __PPC_KERNEL_TODC_H
20#define __PPC_KERNEL_TODC_H
21
22typedef struct {
23 uint rtc_type; /* your particular chip */
24
25 /*
26 * Following are the addresses of the AS0, AS1, and DATA registers
27 * of these chips. Note that these are board-specific.
28 */
29 unsigned int nvram_as0;
30 unsigned int nvram_as1;
31 unsigned int nvram_data;
32
33 /*
34 * Define bits to stop external set of regs from changing so
35 * the chip can be read/written reliably.
36 */
37 unsigned char enable_read;
38 unsigned char enable_write;
39
40 /*
41 * Following is the number of AS0 address bits. This is normally
42 * 8 but some bad hardware routes address lines incorrectly.
43 */
44 int as0_bits;
45
46 int nvram_size; /* Size of NVRAM on chip */
47 int sw_flags; /* Software control flags */
48
49 /* Following are the register offsets for the particular chip */
50 int year;
51 int month;
52 int day_of_month;
53 int day_of_week;
54 int hours;
55 int minutes;
56 int seconds;
57 int control_b;
58 int control_a;
59 int watchdog;
60 int interrupts;
61 int alarm_date;
62 int alarm_hour;
63 int alarm_minutes;
64 int alarm_seconds;
65 int century;
66 int flags;
67
68 /*
69 * Some RTC chips have their NVRAM buried behind a addr/data pair of
70 * regs on the first level/clock registers. The following fields
71 * are the addresses for those addr/data regs.
72 */
73 int nvram_addr_reg;
74 int nvram_data_reg;
75} todc_info_t;
76
77/*
78 * Define the types of TODC/RTC variants that are supported in
79 * arch/ppc/kernel/todc_time.c
80 * Make a new one of these for any chip somehow differs from what's already
81 * defined. That way, if you ever need to put in code to touch those
82 * bits/registers in todc_time.c, you can put it inside an
83 * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break
84 * anyone else.
85 */
86#define TODC_TYPE_MK48T35 1
87#define TODC_TYPE_MK48T37 2
88#define TODC_TYPE_MK48T59 3
89#define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */
90#define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */
91#define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */
92#define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */
93#define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */
94#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */
95#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */
96#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */
97#define TODC_TYPE_DS17285 12 /* Dallas DS17285 RTC */
98#define TODC_TYPE_DS1553 13 /* Dallas DS1553 RTC */
99#define TODC_TYPE_MC146818 100 /* Leave room for m48txx's */
100
101/*
102 * Bit to clear/set to enable reads/writes to the chip
103 */
104#define TODC_MK48TXX_CNTL_A_R 0x40
105#define TODC_MK48TXX_CNTL_A_W 0x80
106#define TODC_MK48TXX_DAY_CB 0x80
107
108#define TODC_DS1501_CNTL_B_TE 0x80
109
110/*
111 * Define flag bits used by todc routines.
112 */
113#define TODC_FLAG_2_LEVEL_NVRAM 0x00000001
114
115/*
116 * Define the values for the various RTC's that should to into the todc_info
117 * table.
118 * Note: The XXX_NVRAM_SIZE, XXX_NVRAM_ADDR_REG, and XXX_NVRAM_DATA_REG only
119 * matter if XXX_SW_FLAGS has TODC_FLAG_2_LEVEL_NVRAM set.
120 */
121#define TODC_TYPE_MK48T35_NVRAM_SIZE 0x7ff8
122#define TODC_TYPE_MK48T35_SW_FLAGS 0
123#define TODC_TYPE_MK48T35_YEAR 0x7fff
124#define TODC_TYPE_MK48T35_MONTH 0x7ffe
125#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */
126#define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */
127#define TODC_TYPE_MK48T35_HOURS 0x7ffb
128#define TODC_TYPE_MK48T35_MINUTES 0x7ffa
129#define TODC_TYPE_MK48T35_SECONDS 0x7ff9
130#define TODC_TYPE_MK48T35_CNTL_B 0x7ff9
131#define TODC_TYPE_MK48T35_CNTL_A 0x7ff8
132#define TODC_TYPE_MK48T35_WATCHDOG 0x0000
133#define TODC_TYPE_MK48T35_INTERRUPTS 0x0000
134#define TODC_TYPE_MK48T35_ALARM_DATE 0x0000
135#define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000
136#define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000
137#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000
138#define TODC_TYPE_MK48T35_CENTURY 0x0000
139#define TODC_TYPE_MK48T35_FLAGS 0x0000
140#define TODC_TYPE_MK48T35_NVRAM_ADDR_REG 0
141#define TODC_TYPE_MK48T35_NVRAM_DATA_REG 0
142
143#define TODC_TYPE_MK48T37_NVRAM_SIZE 0x7ff0
144#define TODC_TYPE_MK48T37_SW_FLAGS 0
145#define TODC_TYPE_MK48T37_YEAR 0x7fff
146#define TODC_TYPE_MK48T37_MONTH 0x7ffe
147#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */
148#define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */
149#define TODC_TYPE_MK48T37_HOURS 0x7ffb
150#define TODC_TYPE_MK48T37_MINUTES 0x7ffa
151#define TODC_TYPE_MK48T37_SECONDS 0x7ff9
152#define TODC_TYPE_MK48T37_CNTL_B 0x7ff9
153#define TODC_TYPE_MK48T37_CNTL_A 0x7ff8
154#define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7
155#define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6
156#define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5
157#define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4
158#define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3
159#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2
160#define TODC_TYPE_MK48T37_CENTURY 0x7ff1
161#define TODC_TYPE_MK48T37_FLAGS 0x7ff0
162#define TODC_TYPE_MK48T37_NVRAM_ADDR_REG 0
163#define TODC_TYPE_MK48T37_NVRAM_DATA_REG 0
164
165#define TODC_TYPE_MK48T59_NVRAM_SIZE 0x1ff0
166#define TODC_TYPE_MK48T59_SW_FLAGS 0
167#define TODC_TYPE_MK48T59_YEAR 0x1fff
168#define TODC_TYPE_MK48T59_MONTH 0x1ffe
169#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */
170#define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */
171#define TODC_TYPE_MK48T59_HOURS 0x1ffb
172#define TODC_TYPE_MK48T59_MINUTES 0x1ffa
173#define TODC_TYPE_MK48T59_SECONDS 0x1ff9
174#define TODC_TYPE_MK48T59_CNTL_B 0x1ff9
175#define TODC_TYPE_MK48T59_CNTL_A 0x1ff8
176#define TODC_TYPE_MK48T59_WATCHDOG 0x1fff
177#define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff
178#define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff
179#define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff
180#define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff
181#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff
182#define TODC_TYPE_MK48T59_CENTURY 0x1fff
183#define TODC_TYPE_MK48T59_FLAGS 0x1fff
184#define TODC_TYPE_MK48T59_NVRAM_ADDR_REG 0
185#define TODC_TYPE_MK48T59_NVRAM_DATA_REG 0
186
187#define TODC_TYPE_DS1501_NVRAM_SIZE 0x100
188#define TODC_TYPE_DS1501_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
189#define TODC_TYPE_DS1501_YEAR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x06)
190#define TODC_TYPE_DS1501_MONTH (TODC_TYPE_DS1501_NVRAM_SIZE + 0x05)
191#define TODC_TYPE_DS1501_DOM (TODC_TYPE_DS1501_NVRAM_SIZE + 0x04)
192#define TODC_TYPE_DS1501_DOW (TODC_TYPE_DS1501_NVRAM_SIZE + 0x03)
193#define TODC_TYPE_DS1501_HOURS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x02)
194#define TODC_TYPE_DS1501_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x01)
195#define TODC_TYPE_DS1501_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x00)
196#define TODC_TYPE_DS1501_CNTL_B (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
197#define TODC_TYPE_DS1501_CNTL_A (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0f)
198#define TODC_TYPE_DS1501_WATCHDOG (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
199#define TODC_TYPE_DS1501_INTERRUPTS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
200#define TODC_TYPE_DS1501_ALARM_DATE (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0b)
201#define TODC_TYPE_DS1501_ALARM_HOUR (TODC_TYPE_DS1501_NVRAM_SIZE + 0x0a)
202#define TODC_TYPE_DS1501_ALARM_MINUTES (TODC_TYPE_DS1501_NVRAM_SIZE + 0x09)
203#define TODC_TYPE_DS1501_ALARM_SECONDS (TODC_TYPE_DS1501_NVRAM_SIZE + 0x08)
204#define TODC_TYPE_DS1501_CENTURY (TODC_TYPE_DS1501_NVRAM_SIZE + 0x07)
205#define TODC_TYPE_DS1501_FLAGS (TODC_TYPE_DS1501_NVRAM_SIZE + 0xff)
206#define TODC_TYPE_DS1501_NVRAM_ADDR_REG 0x10
207#define TODC_TYPE_DS1501_NVRAM_DATA_REG 0x13
208
209#define TODC_TYPE_DS1553_NVRAM_SIZE 0x1ff0
210#define TODC_TYPE_DS1553_SW_FLAGS 0
211#define TODC_TYPE_DS1553_YEAR 0x1fff
212#define TODC_TYPE_DS1553_MONTH 0x1ffe
213#define TODC_TYPE_DS1553_DOM 0x1ffd /* Day of Month */
214#define TODC_TYPE_DS1553_DOW 0x1ffc /* Day of Week */
215#define TODC_TYPE_DS1553_HOURS 0x1ffb
216#define TODC_TYPE_DS1553_MINUTES 0x1ffa
217#define TODC_TYPE_DS1553_SECONDS 0x1ff9
218#define TODC_TYPE_DS1553_CNTL_B 0x1ff9
219#define TODC_TYPE_DS1553_CNTL_A 0x1ff8 /* control_a R/W regs */
220#define TODC_TYPE_DS1553_WATCHDOG 0x1ff7
221#define TODC_TYPE_DS1553_INTERRUPTS 0x1ff6
222#define TODC_TYPE_DS1553_ALARM_DATE 0x1ff5
223#define TODC_TYPE_DS1553_ALARM_HOUR 0x1ff4
224#define TODC_TYPE_DS1553_ALARM_MINUTES 0x1ff3
225#define TODC_TYPE_DS1553_ALARM_SECONDS 0x1ff2
226#define TODC_TYPE_DS1553_CENTURY 0x1ff8
227#define TODC_TYPE_DS1553_FLAGS 0x1ff0
228#define TODC_TYPE_DS1553_NVRAM_ADDR_REG 0
229#define TODC_TYPE_DS1553_NVRAM_DATA_REG 0
230
231#define TODC_TYPE_DS1557_NVRAM_SIZE 0x7fff0
232#define TODC_TYPE_DS1557_SW_FLAGS 0
233#define TODC_TYPE_DS1557_YEAR 0x7ffff
234#define TODC_TYPE_DS1557_MONTH 0x7fffe
235#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */
236#define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */
237#define TODC_TYPE_DS1557_HOURS 0x7fffb
238#define TODC_TYPE_DS1557_MINUTES 0x7fffa
239#define TODC_TYPE_DS1557_SECONDS 0x7fff9
240#define TODC_TYPE_DS1557_CNTL_B 0x7fff9
241#define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */
242#define TODC_TYPE_DS1557_WATCHDOG 0x7fff7
243#define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6
244#define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5
245#define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4
246#define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3
247#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2
248#define TODC_TYPE_DS1557_CENTURY 0x7fff8
249#define TODC_TYPE_DS1557_FLAGS 0x7fff0
250#define TODC_TYPE_DS1557_NVRAM_ADDR_REG 0
251#define TODC_TYPE_DS1557_NVRAM_DATA_REG 0
252
253#define TODC_TYPE_DS1643_NVRAM_SIZE 0x1ff8
254#define TODC_TYPE_DS1643_SW_FLAGS 0
255#define TODC_TYPE_DS1643_YEAR 0x1fff
256#define TODC_TYPE_DS1643_MONTH 0x1ffe
257#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */
258#define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */
259#define TODC_TYPE_DS1643_HOURS 0x1ffb
260#define TODC_TYPE_DS1643_MINUTES 0x1ffa
261#define TODC_TYPE_DS1643_SECONDS 0x1ff9
262#define TODC_TYPE_DS1643_CNTL_B 0x1ff9
263#define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */
264#define TODC_TYPE_DS1643_WATCHDOG 0x1fff
265#define TODC_TYPE_DS1643_INTERRUPTS 0x1fff
266#define TODC_TYPE_DS1643_ALARM_DATE 0x1fff
267#define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff
268#define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff
269#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff
270#define TODC_TYPE_DS1643_CENTURY 0x1ff8
271#define TODC_TYPE_DS1643_FLAGS 0x1fff
272#define TODC_TYPE_DS1643_NVRAM_ADDR_REG 0
273#define TODC_TYPE_DS1643_NVRAM_DATA_REG 0
274
275#define TODC_TYPE_DS1693_NVRAM_SIZE 0 /* Not handled yet */
276#define TODC_TYPE_DS1693_SW_FLAGS 0
277#define TODC_TYPE_DS1693_YEAR 0x09
278#define TODC_TYPE_DS1693_MONTH 0x08
279#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */
280#define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */
281#define TODC_TYPE_DS1693_HOURS 0x04
282#define TODC_TYPE_DS1693_MINUTES 0x02
283#define TODC_TYPE_DS1693_SECONDS 0x00
284#define TODC_TYPE_DS1693_CNTL_B 0x0b
285#define TODC_TYPE_DS1693_CNTL_A 0x0a
286#define TODC_TYPE_DS1693_WATCHDOG 0xff
287#define TODC_TYPE_DS1693_INTERRUPTS 0xff
288#define TODC_TYPE_DS1693_ALARM_DATE 0x49
289#define TODC_TYPE_DS1693_ALARM_HOUR 0x05
290#define TODC_TYPE_DS1693_ALARM_MINUTES 0x03
291#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01
292#define TODC_TYPE_DS1693_CENTURY 0x48
293#define TODC_TYPE_DS1693_FLAGS 0xff
294#define TODC_TYPE_DS1693_NVRAM_ADDR_REG 0
295#define TODC_TYPE_DS1693_NVRAM_DATA_REG 0
296
297#define TODC_TYPE_DS1743_NVRAM_SIZE 0x1ff8
298#define TODC_TYPE_DS1743_SW_FLAGS 0
299#define TODC_TYPE_DS1743_YEAR 0x1fff
300#define TODC_TYPE_DS1743_MONTH 0x1ffe
301#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */
302#define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */
303#define TODC_TYPE_DS1743_HOURS 0x1ffb
304#define TODC_TYPE_DS1743_MINUTES 0x1ffa
305#define TODC_TYPE_DS1743_SECONDS 0x1ff9
306#define TODC_TYPE_DS1743_CNTL_B 0x1ff9
307#define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */
308#define TODC_TYPE_DS1743_WATCHDOG 0x1fff
309#define TODC_TYPE_DS1743_INTERRUPTS 0x1fff
310#define TODC_TYPE_DS1743_ALARM_DATE 0x1fff
311#define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff
312#define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff
313#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff
314#define TODC_TYPE_DS1743_CENTURY 0x1ff8
315#define TODC_TYPE_DS1743_FLAGS 0x1fff
316#define TODC_TYPE_DS1743_NVRAM_ADDR_REG 0
317#define TODC_TYPE_DS1743_NVRAM_DATA_REG 0
318
319#define TODC_TYPE_DS1746_NVRAM_SIZE 0x1fff8
320#define TODC_TYPE_DS1746_SW_FLAGS 0
321#define TODC_TYPE_DS1746_YEAR 0x1ffff
322#define TODC_TYPE_DS1746_MONTH 0x1fffe
323#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */
324#define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */
325#define TODC_TYPE_DS1746_HOURS 0x1fffb
326#define TODC_TYPE_DS1746_MINUTES 0x1fffa
327#define TODC_TYPE_DS1746_SECONDS 0x1fff9
328#define TODC_TYPE_DS1746_CNTL_B 0x1fff9
329#define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */
330#define TODC_TYPE_DS1746_WATCHDOG 0x00000
331#define TODC_TYPE_DS1746_INTERRUPTS 0x00000
332#define TODC_TYPE_DS1746_ALARM_DATE 0x00000
333#define TODC_TYPE_DS1746_ALARM_HOUR 0x00000
334#define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000
335#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000
336#define TODC_TYPE_DS1746_CENTURY 0x00000
337#define TODC_TYPE_DS1746_FLAGS 0x00000
338#define TODC_TYPE_DS1746_NVRAM_ADDR_REG 0
339#define TODC_TYPE_DS1746_NVRAM_DATA_REG 0
340
341#define TODC_TYPE_DS1747_NVRAM_SIZE 0x7fff8
342#define TODC_TYPE_DS1747_SW_FLAGS 0
343#define TODC_TYPE_DS1747_YEAR 0x7ffff
344#define TODC_TYPE_DS1747_MONTH 0x7fffe
345#define TODC_TYPE_DS1747_DOM 0x7fffd /* Day of Month */
346#define TODC_TYPE_DS1747_DOW 0x7fffc /* Day of Week */
347#define TODC_TYPE_DS1747_HOURS 0x7fffb
348#define TODC_TYPE_DS1747_MINUTES 0x7fffa
349#define TODC_TYPE_DS1747_SECONDS 0x7fff9
350#define TODC_TYPE_DS1747_CNTL_B 0x7fff9
351#define TODC_TYPE_DS1747_CNTL_A 0x7fff8 /* control_a R/W regs */
352#define TODC_TYPE_DS1747_WATCHDOG 0x00000
353#define TODC_TYPE_DS1747_INTERRUPTS 0x00000
354#define TODC_TYPE_DS1747_ALARM_DATE 0x00000
355#define TODC_TYPE_DS1747_ALARM_HOUR 0x00000
356#define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000
357#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000
358#define TODC_TYPE_DS1747_CENTURY 0x00000
359#define TODC_TYPE_DS1747_FLAGS 0x00000
360#define TODC_TYPE_DS1747_NVRAM_ADDR_REG 0
361#define TODC_TYPE_DS1747_NVRAM_DATA_REG 0
362
363#define TODC_TYPE_DS17285_NVRAM_SIZE (0x1000-0x80) /* 4Kx8 NVRAM (minus RTC regs) */
364#define TODC_TYPE_DS17285_SW_FLAGS TODC_FLAG_2_LEVEL_NVRAM
365#define TODC_TYPE_DS17285_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x00)
366#define TODC_TYPE_DS17285_ALARM_SECONDS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x01)
367#define TODC_TYPE_DS17285_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x02)
368#define TODC_TYPE_DS17285_ALARM_MINUTES (TODC_TYPE_DS17285_NVRAM_SIZE + 0x03)
369#define TODC_TYPE_DS17285_HOURS (TODC_TYPE_DS17285_NVRAM_SIZE + 0x04)
370#define TODC_TYPE_DS17285_ALARM_HOUR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x05)
371#define TODC_TYPE_DS17285_DOW (TODC_TYPE_DS17285_NVRAM_SIZE + 0x06)
372#define TODC_TYPE_DS17285_DOM (TODC_TYPE_DS17285_NVRAM_SIZE + 0x07)
373#define TODC_TYPE_DS17285_MONTH (TODC_TYPE_DS17285_NVRAM_SIZE + 0x08)
374#define TODC_TYPE_DS17285_YEAR (TODC_TYPE_DS17285_NVRAM_SIZE + 0x09)
375#define TODC_TYPE_DS17285_CNTL_A (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0A)
376#define TODC_TYPE_DS17285_CNTL_B (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0B)
377#define TODC_TYPE_DS17285_CNTL_C (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0C)
378#define TODC_TYPE_DS17285_CNTL_D (TODC_TYPE_DS17285_NVRAM_SIZE + 0x0D)
379#define TODC_TYPE_DS17285_WATCHDOG 0
380#define TODC_TYPE_DS17285_INTERRUPTS 0
381#define TODC_TYPE_DS17285_ALARM_DATE 0
382#define TODC_TYPE_DS17285_CENTURY 0
383#define TODC_TYPE_DS17285_FLAGS 0
384#define TODC_TYPE_DS17285_NVRAM_ADDR_REG 0x50
385#define TODC_TYPE_DS17285_NVRAM_DATA_REG 0x53
386
387#define TODC_TYPE_MC146818_NVRAM_SIZE 0 /* XXXX */
388#define TODC_TYPE_MC146818_SW_FLAGS 0
389#define TODC_TYPE_MC146818_YEAR 0x09
390#define TODC_TYPE_MC146818_MONTH 0x08
391#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */
392#define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */
393#define TODC_TYPE_MC146818_HOURS 0x04
394#define TODC_TYPE_MC146818_MINUTES 0x02
395#define TODC_TYPE_MC146818_SECONDS 0x00
396#define TODC_TYPE_MC146818_CNTL_B 0x0a
397#define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */
398#define TODC_TYPE_MC146818_WATCHDOG 0
399#define TODC_TYPE_MC146818_INTERRUPTS 0x0c
400#define TODC_TYPE_MC146818_ALARM_DATE 0xff
401#define TODC_TYPE_MC146818_ALARM_HOUR 0x05
402#define TODC_TYPE_MC146818_ALARM_MINUTES 0x03
403#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01
404#define TODC_TYPE_MC146818_CENTURY 0xff
405#define TODC_TYPE_MC146818_FLAGS 0xff
406#define TODC_TYPE_MC146818_NVRAM_ADDR_REG 0
407#define TODC_TYPE_MC146818_NVRAM_DATA_REG 0
408
409#define TODC_TYPE_PC97307_NVRAM_SIZE 0 /* No NVRAM? */
410#define TODC_TYPE_PC97307_SW_FLAGS 0
411#define TODC_TYPE_PC97307_YEAR 0x09
412#define TODC_TYPE_PC97307_MONTH 0x08
413#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */
414#define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */
415#define TODC_TYPE_PC97307_HOURS 0x04
416#define TODC_TYPE_PC97307_MINUTES 0x02
417#define TODC_TYPE_PC97307_SECONDS 0x00
418#define TODC_TYPE_PC97307_CNTL_B 0x0a
419#define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */
420#define TODC_TYPE_PC97307_WATCHDOG 0x0c
421#define TODC_TYPE_PC97307_INTERRUPTS 0x0d
422#define TODC_TYPE_PC97307_ALARM_DATE 0xff
423#define TODC_TYPE_PC97307_ALARM_HOUR 0x05
424#define TODC_TYPE_PC97307_ALARM_MINUTES 0x03
425#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01
426#define TODC_TYPE_PC97307_CENTURY 0xff
427#define TODC_TYPE_PC97307_FLAGS 0xff
428#define TODC_TYPE_PC97307_NVRAM_ADDR_REG 0
429#define TODC_TYPE_PC97307_NVRAM_DATA_REG 0
430
431/*
432 * Define macros to allocate and init the todc_info_t table that will
433 * be used by the todc_time.c routines.
434 */
435#define TODC_ALLOC() \
436 static todc_info_t todc_info_alloc; \
437 todc_info_t *todc_info = &todc_info_alloc;
438
439#define TODC_INIT(clock_type, as0, as1, data, bits) { \
440 todc_info->rtc_type = clock_type; \
441 \
442 todc_info->nvram_as0 = (unsigned int)(as0); \
443 todc_info->nvram_as1 = (unsigned int)(as1); \
444 todc_info->nvram_data = (unsigned int)(data); \
445 \
446 todc_info->as0_bits = (bits); \
447 \
448 todc_info->nvram_size = clock_type ##_NVRAM_SIZE; \
449 todc_info->sw_flags = clock_type ##_SW_FLAGS; \
450 \
451 todc_info->year = clock_type ##_YEAR; \
452 todc_info->month = clock_type ##_MONTH; \
453 todc_info->day_of_month = clock_type ##_DOM; \
454 todc_info->day_of_week = clock_type ##_DOW; \
455 todc_info->hours = clock_type ##_HOURS; \
456 todc_info->minutes = clock_type ##_MINUTES; \
457 todc_info->seconds = clock_type ##_SECONDS; \
458 todc_info->control_b = clock_type ##_CNTL_B; \
459 todc_info->control_a = clock_type ##_CNTL_A; \
460 todc_info->watchdog = clock_type ##_WATCHDOG; \
461 todc_info->interrupts = clock_type ##_INTERRUPTS; \
462 todc_info->alarm_date = clock_type ##_ALARM_DATE; \
463 todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \
464 todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \
465 todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \
466 todc_info->century = clock_type ##_CENTURY; \
467 todc_info->flags = clock_type ##_FLAGS; \
468 \
469 todc_info->nvram_addr_reg = clock_type ##_NVRAM_ADDR_REG; \
470 todc_info->nvram_data_reg = clock_type ##_NVRAM_DATA_REG; \
471}
472
473extern todc_info_t *todc_info;
474
475unsigned char todc_direct_read_val(int addr);
476void todc_direct_write_val(int addr, unsigned char val);
477unsigned char todc_m48txx_read_val(int addr);
478void todc_m48txx_write_val(int addr, unsigned char val);
479unsigned char todc_mc146818_read_val(int addr);
480void todc_mc146818_write_val(int addr, unsigned char val);
481
482long todc_time_init(void);
483void todc_get_rtc_time(struct rtc_time *);
484int todc_set_rtc_time(struct rtc_time *);
485void todc_calibrate_decr(void);
486
487#endif /* __PPC_KERNEL_TODC_H */
diff --git a/include/asm-powerpc/tsi108.h b/include/asm-powerpc/tsi108.h
new file mode 100644
index 000000000000..c4c278d72f71
--- /dev/null
+++ b/include/asm-powerpc/tsi108.h
@@ -0,0 +1,109 @@
1/*
2 * include/asm-ppc/tsi108.h
3 *
4 * common routine and memory layout for Tundra TSI108(Grendel) host bridge
5 * memory controller.
6 *
7 * Author: Jacob Pan (jacob.pan@freescale.com)
8 * Alex Bounine (alexandreb@tundra.com)
9 * 2004 (c) Freescale Semiconductor Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14#ifndef __PPC_KERNEL_TSI108_H
15#define __PPC_KERNEL_TSI108_H
16
17#include <asm/pci-bridge.h>
18
19/* Size of entire register space */
20#define TSI108_REG_SIZE (0x10000)
21
22/* Sizes of register spaces for individual blocks */
23#define TSI108_HLP_SIZE 0x1000
24#define TSI108_PCI_SIZE 0x1000
25#define TSI108_CLK_SIZE 0x1000
26#define TSI108_PB_SIZE 0x1000
27#define TSI108_SD_SIZE 0x1000
28#define TSI108_DMA_SIZE 0x1000
29#define TSI108_ETH_SIZE 0x1000
30#define TSI108_I2C_SIZE 0x400
31#define TSI108_MPIC_SIZE 0x400
32#define TSI108_UART0_SIZE 0x200
33#define TSI108_GPIO_SIZE 0x200
34#define TSI108_UART1_SIZE 0x200
35
36/* Offsets within Tsi108(A) CSR space for individual blocks */
37#define TSI108_HLP_OFFSET 0x0000
38#define TSI108_PCI_OFFSET 0x1000
39#define TSI108_CLK_OFFSET 0x2000
40#define TSI108_PB_OFFSET 0x3000
41#define TSI108_SD_OFFSET 0x4000
42#define TSI108_DMA_OFFSET 0x5000
43#define TSI108_ETH_OFFSET 0x6000
44#define TSI108_I2C_OFFSET 0x7000
45#define TSI108_MPIC_OFFSET 0x7400
46#define TSI108_UART0_OFFSET 0x7800
47#define TSI108_GPIO_OFFSET 0x7A00
48#define TSI108_UART1_OFFSET 0x7C00
49
50/* Tsi108 registers used by common code components */
51#define TSI108_PCI_CSR (0x004)
52#define TSI108_PCI_IRP_CFG_CTL (0x180)
53#define TSI108_PCI_IRP_STAT (0x184)
54#define TSI108_PCI_IRP_ENABLE (0x188)
55#define TSI108_PCI_IRP_INTAD (0x18C)
56
57#define TSI108_PCI_IRP_STAT_P_INT (0x00400000)
58#define TSI108_PCI_IRP_ENABLE_P_INT (0x00400000)
59
60#define TSI108_CG_PWRUP_STATUS (0x234)
61
62#define TSI108_PB_ISR (0x00C)
63#define TSI108_PB_ERRCS (0x404)
64#define TSI108_PB_AERR (0x408)
65
66#define TSI108_PB_ERRCS_ES (1 << 1)
67#define TSI108_PB_ISR_PBS_RD_ERR (1 << 8)
68
69#define TSI108_PCI_CFG_BASE_PHYS (0xfb000000)
70#define TSI108_PCI_CFG_SIZE (0x01000000)
71/* Global variables */
72
73extern u32 tsi108_pci_cfg_base;
74/* Exported functions */
75
76extern int tsi108_bridge_init(struct pci_controller *hose, uint phys_csr_base);
77extern unsigned long tsi108_get_mem_size(void);
78extern unsigned long tsi108_get_cpu_clk(void);
79extern unsigned long tsi108_get_sdc_clk(void);
80extern int tsi108_direct_write_config(struct pci_bus *bus, unsigned int devfn,
81 int offset, int len, u32 val);
82extern int tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn,
83 int offset, int len, u32 * val);
84extern void tsi108_clear_pci_error(u32 pci_cfg_base);
85
86extern phys_addr_t get_csrbase(void);
87
88typedef struct {
89 u32 regs; /* hw registers base address */
90 u32 phyregs; /* phy registers base address */
91 u16 phy; /* phy address */
92 u16 irq_num; /* irq number */
93 u8 mac_addr[6]; /* phy mac address */
94} hw_info;
95
96extern u32 get_vir_csrbase(void);
97extern u32 tsi108_csr_vir_base;
98
99extern inline u32 tsi108_read_reg(u32 reg_offset)
100{
101 return in_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset));
102}
103
104extern inline void tsi108_write_reg(u32 reg_offset, u32 val)
105{
106 out_be32((volatile u32 *)(tsi108_csr_vir_base + reg_offset), val);
107}
108
109#endif /* __PPC_KERNEL_TSI108_H */
diff --git a/include/asm-powerpc/udbg.h b/include/asm-powerpc/udbg.h
index 19a1517ac43b..55e57844fa78 100644
--- a/include/asm-powerpc/udbg.h
+++ b/include/asm-powerpc/udbg.h
@@ -42,7 +42,8 @@ extern void __init udbg_init_debug_lpar(void);
42extern void __init udbg_init_pmac_realmode(void); 42extern void __init udbg_init_pmac_realmode(void);
43extern void __init udbg_init_maple_realmode(void); 43extern void __init udbg_init_maple_realmode(void);
44extern void __init udbg_init_iseries(void); 44extern void __init udbg_init_iseries(void);
45extern void __init udbg_init_rtas(void); 45extern void __init udbg_init_rtas_panel(void);
46extern void __init udbg_init_rtas_console(void);
46 47
47#endif /* __KERNEL__ */ 48#endif /* __KERNEL__ */
48#endif /* _ASM_POWERPC_UDBG_H */ 49#endif /* _ASM_POWERPC_UDBG_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-23 00:53:54 -0500