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-rw-r--r--include/asm-powerpc/abs_addr.h73
-rw-r--r--include/asm-powerpc/asm-compat.h55
-rw-r--r--include/asm-powerpc/atomic.h188
-rw-r--r--include/asm-powerpc/bitops.h41
-rw-r--r--include/asm-powerpc/bug.h19
-rw-r--r--include/asm-powerpc/cache.h40
-rw-r--r--include/asm-powerpc/cacheflush.h68
-rw-r--r--include/asm-powerpc/compat.h205
-rw-r--r--include/asm-powerpc/cputable.h6
-rw-r--r--include/asm-powerpc/current.h27
-rw-r--r--include/asm-powerpc/eeh_event.h52
-rw-r--r--include/asm-powerpc/firmware.h6
-rw-r--r--include/asm-powerpc/futex.h5
-rw-r--r--include/asm-powerpc/hvcall.h173
-rw-r--r--include/asm-powerpc/hw_irq.h1
-rw-r--r--include/asm-powerpc/irq.h5
-rw-r--r--include/asm-powerpc/lppaca.h131
-rw-r--r--include/asm-powerpc/paca.h120
-rw-r--r--include/asm-powerpc/ppc-pci.h52
-rw-r--r--include/asm-powerpc/ppc_asm.h39
-rw-r--r--include/asm-powerpc/processor.h70
-rw-r--r--include/asm-powerpc/reg.h7
-rw-r--r--include/asm-powerpc/reg_8xx.h42
-rw-r--r--include/asm-powerpc/signal.h150
-rw-r--r--include/asm-powerpc/sparsemem.h4
-rw-r--r--include/asm-powerpc/system.h2
-rw-r--r--include/asm-powerpc/systemcfg.h64
-rw-r--r--include/asm-powerpc/tce.h64
-rw-r--r--include/asm-powerpc/uaccess.h40
-rw-r--r--include/asm-powerpc/xmon.h1
30 files changed, 1602 insertions, 148 deletions
diff --git a/include/asm-powerpc/abs_addr.h b/include/asm-powerpc/abs_addr.h
new file mode 100644
index 000000000000..18415108fc56
--- /dev/null
+++ b/include/asm-powerpc/abs_addr.h
@@ -0,0 +1,73 @@
1#ifndef _ASM_POWERPC_ABS_ADDR_H
2#define _ASM_POWERPC_ABS_ADDR_H
3
4#include <linux/config.h>
5
6/*
7 * c 2001 PPC 64 Team, IBM Corp
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
13 */
14
15#include <asm/types.h>
16#include <asm/page.h>
17#include <asm/prom.h>
18#include <asm/lmb.h>
19#include <asm/firmware.h>
20
21struct mschunks_map {
22 unsigned long num_chunks;
23 unsigned long chunk_size;
24 unsigned long chunk_shift;
25 unsigned long chunk_mask;
26 u32 *mapping;
27};
28
29extern struct mschunks_map mschunks_map;
30
31/* Chunks are 256 KB */
32#define MSCHUNKS_CHUNK_SHIFT (18)
33#define MSCHUNKS_CHUNK_SIZE (1UL << MSCHUNKS_CHUNK_SHIFT)
34#define MSCHUNKS_OFFSET_MASK (MSCHUNKS_CHUNK_SIZE - 1)
35
36static inline unsigned long chunk_to_addr(unsigned long chunk)
37{
38 return chunk << MSCHUNKS_CHUNK_SHIFT;
39}
40
41static inline unsigned long addr_to_chunk(unsigned long addr)
42{
43 return addr >> MSCHUNKS_CHUNK_SHIFT;
44}
45
46static inline unsigned long phys_to_abs(unsigned long pa)
47{
48 unsigned long chunk;
49
50 /* This is a no-op on non-iSeries */
51 if (!firmware_has_feature(FW_FEATURE_ISERIES))
52 return pa;
53
54 chunk = addr_to_chunk(pa);
55
56 if (chunk < mschunks_map.num_chunks)
57 chunk = mschunks_map.mapping[chunk];
58
59 return chunk_to_addr(chunk) + (pa & MSCHUNKS_OFFSET_MASK);
60}
61
62/* Convenience macros */
63#define virt_to_abs(va) phys_to_abs(__pa(va))
64#define abs_to_virt(aa) __va(aa)
65
66/*
67 * Converts Virtual Address to Real Address for
68 * Legacy iSeries Hypervisor calls
69 */
70#define iseries_hv_addr(virtaddr) \
71 (0x8000000000000000 | virt_to_abs(virtaddr))
72
73#endif /* _ASM_POWERPC_ABS_ADDR_H */
diff --git a/include/asm-powerpc/asm-compat.h b/include/asm-powerpc/asm-compat.h
new file mode 100644
index 000000000000..8b133efc9f79
--- /dev/null
+++ b/include/asm-powerpc/asm-compat.h
@@ -0,0 +1,55 @@
1#ifndef _ASM_POWERPC_ASM_COMPAT_H
2#define _ASM_POWERPC_ASM_COMPAT_H
3
4#include <linux/config.h>
5#include <asm/types.h>
6
7#ifdef __ASSEMBLY__
8# define stringify_in_c(...) __VA_ARGS__
9# define ASM_CONST(x) x
10#else
11/* This version of stringify will deal with commas... */
12# define __stringify_in_c(...) #__VA_ARGS__
13# define stringify_in_c(...) __stringify_in_c(__VA_ARGS__) " "
14# define __ASM_CONST(x) x##UL
15# define ASM_CONST(x) __ASM_CONST(x)
16#endif
17
18#ifdef __powerpc64__
19
20/* operations for longs and pointers */
21#define PPC_LL stringify_in_c(ld)
22#define PPC_STL stringify_in_c(std)
23#define PPC_LCMPI stringify_in_c(cmpdi)
24#define PPC_LONG stringify_in_c(.llong)
25#define PPC_TLNEI stringify_in_c(tdnei)
26#define PPC_LLARX stringify_in_c(ldarx)
27#define PPC_STLCX stringify_in_c(stdcx.)
28#define PPC_CNTLZL stringify_in_c(cntlzd)
29
30#else /* 32-bit */
31
32/* operations for longs and pointers */
33#define PPC_LL stringify_in_c(lwz)
34#define PPC_STL stringify_in_c(stw)
35#define PPC_LCMPI stringify_in_c(cmpwi)
36#define PPC_LONG stringify_in_c(.long)
37#define PPC_TLNEI stringify_in_c(twnei)
38#define PPC_LLARX stringify_in_c(lwarx)
39#define PPC_STLCX stringify_in_c(stwcx.)
40#define PPC_CNTLZL stringify_in_c(cntlzw)
41
42#endif
43
44#ifdef CONFIG_IBM405_ERR77
45/* Erratum #77 on the 405 means we need a sync or dcbt before every
46 * stwcx. The old ATOMIC_SYNC_FIX covered some but not all of this.
47 */
48#define PPC405_ERR77(ra,rb) stringify_in_c(dcbt ra, rb;)
49#define PPC405_ERR77_SYNC stringify_in_c(sync;)
50#else
51#define PPC405_ERR77(ra,rb)
52#define PPC405_ERR77_SYNC
53#endif
54
55#endif /* _ASM_POWERPC_ASM_COMPAT_H */
diff --git a/include/asm-powerpc/atomic.h b/include/asm-powerpc/atomic.h
index ed4b345ed75d..9c0b372a46e1 100644
--- a/include/asm-powerpc/atomic.h
+++ b/include/asm-powerpc/atomic.h
@@ -9,21 +9,13 @@ typedef struct { volatile int counter; } atomic_t;
9 9
10#ifdef __KERNEL__ 10#ifdef __KERNEL__
11#include <asm/synch.h> 11#include <asm/synch.h>
12#include <asm/asm-compat.h>
12 13
13#define ATOMIC_INIT(i) { (i) } 14#define ATOMIC_INIT(i) { (i) }
14 15
15#define atomic_read(v) ((v)->counter) 16#define atomic_read(v) ((v)->counter)
16#define atomic_set(v,i) (((v)->counter) = (i)) 17#define atomic_set(v,i) (((v)->counter) = (i))
17 18
18/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx.
19 * The old ATOMIC_SYNC_FIX covered some but not all of this.
20 */
21#ifdef CONFIG_IBM405_ERR77
22#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";"
23#else
24#define PPC405_ERR77(ra,rb)
25#endif
26
27static __inline__ void atomic_add(int a, atomic_t *v) 19static __inline__ void atomic_add(int a, atomic_t *v)
28{ 20{
29 int t; 21 int t;
@@ -205,5 +197,183 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
205#define smp_mb__before_atomic_inc() smp_mb() 197#define smp_mb__before_atomic_inc() smp_mb()
206#define smp_mb__after_atomic_inc() smp_mb() 198#define smp_mb__after_atomic_inc() smp_mb()
207 199
200#ifdef __powerpc64__
201
202typedef struct { volatile long counter; } atomic64_t;
203
204#define ATOMIC64_INIT(i) { (i) }
205
206#define atomic64_read(v) ((v)->counter)
207#define atomic64_set(v,i) (((v)->counter) = (i))
208
209static __inline__ void atomic64_add(long a, atomic64_t *v)
210{
211 long t;
212
213 __asm__ __volatile__(
214"1: ldarx %0,0,%3 # atomic64_add\n\
215 add %0,%2,%0\n\
216 stdcx. %0,0,%3 \n\
217 bne- 1b"
218 : "=&r" (t), "=m" (v->counter)
219 : "r" (a), "r" (&v->counter), "m" (v->counter)
220 : "cc");
221}
222
223static __inline__ long atomic64_add_return(long a, atomic64_t *v)
224{
225 long t;
226
227 __asm__ __volatile__(
228 EIEIO_ON_SMP
229"1: ldarx %0,0,%2 # atomic64_add_return\n\
230 add %0,%1,%0\n\
231 stdcx. %0,0,%2 \n\
232 bne- 1b"
233 ISYNC_ON_SMP
234 : "=&r" (t)
235 : "r" (a), "r" (&v->counter)
236 : "cc", "memory");
237
238 return t;
239}
240
241#define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
242
243static __inline__ void atomic64_sub(long a, atomic64_t *v)
244{
245 long t;
246
247 __asm__ __volatile__(
248"1: ldarx %0,0,%3 # atomic64_sub\n\
249 subf %0,%2,%0\n\
250 stdcx. %0,0,%3 \n\
251 bne- 1b"
252 : "=&r" (t), "=m" (v->counter)
253 : "r" (a), "r" (&v->counter), "m" (v->counter)
254 : "cc");
255}
256
257static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
258{
259 long t;
260
261 __asm__ __volatile__(
262 EIEIO_ON_SMP
263"1: ldarx %0,0,%2 # atomic64_sub_return\n\
264 subf %0,%1,%0\n\
265 stdcx. %0,0,%2 \n\
266 bne- 1b"
267 ISYNC_ON_SMP
268 : "=&r" (t)
269 : "r" (a), "r" (&v->counter)
270 : "cc", "memory");
271
272 return t;
273}
274
275static __inline__ void atomic64_inc(atomic64_t *v)
276{
277 long t;
278
279 __asm__ __volatile__(
280"1: ldarx %0,0,%2 # atomic64_inc\n\
281 addic %0,%0,1\n\
282 stdcx. %0,0,%2 \n\
283 bne- 1b"
284 : "=&r" (t), "=m" (v->counter)
285 : "r" (&v->counter), "m" (v->counter)
286 : "cc");
287}
288
289static __inline__ long atomic64_inc_return(atomic64_t *v)
290{
291 long t;
292
293 __asm__ __volatile__(
294 EIEIO_ON_SMP
295"1: ldarx %0,0,%1 # atomic64_inc_return\n\
296 addic %0,%0,1\n\
297 stdcx. %0,0,%1 \n\
298 bne- 1b"
299 ISYNC_ON_SMP
300 : "=&r" (t)
301 : "r" (&v->counter)
302 : "cc", "memory");
303
304 return t;
305}
306
307/*
308 * atomic64_inc_and_test - increment and test
309 * @v: pointer of type atomic64_t
310 *
311 * Atomically increments @v by 1
312 * and returns true if the result is zero, or false for all
313 * other cases.
314 */
315#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
316
317static __inline__ void atomic64_dec(atomic64_t *v)
318{
319 long t;
320
321 __asm__ __volatile__(
322"1: ldarx %0,0,%2 # atomic64_dec\n\
323 addic %0,%0,-1\n\
324 stdcx. %0,0,%2\n\
325 bne- 1b"
326 : "=&r" (t), "=m" (v->counter)
327 : "r" (&v->counter), "m" (v->counter)
328 : "cc");
329}
330
331static __inline__ long atomic64_dec_return(atomic64_t *v)
332{
333 long t;
334
335 __asm__ __volatile__(
336 EIEIO_ON_SMP
337"1: ldarx %0,0,%1 # atomic64_dec_return\n\
338 addic %0,%0,-1\n\
339 stdcx. %0,0,%1\n\
340 bne- 1b"
341 ISYNC_ON_SMP
342 : "=&r" (t)
343 : "r" (&v->counter)
344 : "cc", "memory");
345
346 return t;
347}
348
349#define atomic64_sub_and_test(a, v) (atomic64_sub_return((a), (v)) == 0)
350#define atomic64_dec_and_test(v) (atomic64_dec_return((v)) == 0)
351
352/*
353 * Atomically test *v and decrement if it is greater than 0.
354 * The function returns the old value of *v minus 1.
355 */
356static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
357{
358 long t;
359
360 __asm__ __volatile__(
361 EIEIO_ON_SMP
362"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
363 addic. %0,%0,-1\n\
364 blt- 2f\n\
365 stdcx. %0,0,%1\n\
366 bne- 1b"
367 ISYNC_ON_SMP
368 "\n\
3692:" : "=&r" (t)
370 : "r" (&v->counter)
371 : "cc", "memory");
372
373 return t;
374}
375
376#endif /* __powerpc64__ */
377
208#endif /* __KERNEL__ */ 378#endif /* __KERNEL__ */
209#endif /* _ASM_POWERPC_ATOMIC_H_ */ 379#endif /* _ASM_POWERPC_ATOMIC_H_ */
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
index dc25c53704d5..5727229b0444 100644
--- a/include/asm-powerpc/bitops.h
+++ b/include/asm-powerpc/bitops.h
@@ -40,6 +40,7 @@
40 40
41#include <linux/compiler.h> 41#include <linux/compiler.h>
42#include <asm/atomic.h> 42#include <asm/atomic.h>
43#include <asm/asm-compat.h>
43#include <asm/synch.h> 44#include <asm/synch.h>
44 45
45/* 46/*
@@ -52,16 +53,6 @@
52#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG) 53#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
53#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7) 54#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
54 55
55#ifdef CONFIG_PPC64
56#define LARXL "ldarx"
57#define STCXL "stdcx."
58#define CNTLZL "cntlzd"
59#else
60#define LARXL "lwarx"
61#define STCXL "stwcx."
62#define CNTLZL "cntlzw"
63#endif
64
65static __inline__ void set_bit(int nr, volatile unsigned long *addr) 56static __inline__ void set_bit(int nr, volatile unsigned long *addr)
66{ 57{
67 unsigned long old; 58 unsigned long old;
@@ -69,10 +60,10 @@ static __inline__ void set_bit(int nr, volatile unsigned long *addr)
69 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); 60 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
70 61
71 __asm__ __volatile__( 62 __asm__ __volatile__(
72"1:" LARXL " %0,0,%3 # set_bit\n" 63"1:" PPC_LLARX "%0,0,%3 # set_bit\n"
73 "or %0,%0,%2\n" 64 "or %0,%0,%2\n"
74 PPC405_ERR77(0,%3) 65 PPC405_ERR77(0,%3)
75 STCXL " %0,0,%3\n" 66 PPC_STLCX "%0,0,%3\n"
76 "bne- 1b" 67 "bne- 1b"
77 : "=&r"(old), "=m"(*p) 68 : "=&r"(old), "=m"(*p)
78 : "r"(mask), "r"(p), "m"(*p) 69 : "r"(mask), "r"(p), "m"(*p)
@@ -86,10 +77,10 @@ static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
86 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); 77 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
87 78
88 __asm__ __volatile__( 79 __asm__ __volatile__(
89"1:" LARXL " %0,0,%3 # set_bit\n" 80"1:" PPC_LLARX "%0,0,%3 # clear_bit\n"
90 "andc %0,%0,%2\n" 81 "andc %0,%0,%2\n"
91 PPC405_ERR77(0,%3) 82 PPC405_ERR77(0,%3)
92 STCXL " %0,0,%3\n" 83 PPC_STLCX "%0,0,%3\n"
93 "bne- 1b" 84 "bne- 1b"
94 : "=&r"(old), "=m"(*p) 85 : "=&r"(old), "=m"(*p)
95 : "r"(mask), "r"(p), "m"(*p) 86 : "r"(mask), "r"(p), "m"(*p)
@@ -103,10 +94,10 @@ static __inline__ void change_bit(int nr, volatile unsigned long *addr)
103 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr); 94 unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
104 95
105 __asm__ __volatile__( 96 __asm__ __volatile__(
106"1:" LARXL " %0,0,%3 # set_bit\n" 97"1:" PPC_LLARX "%0,0,%3 # change_bit\n"
107 "xor %0,%0,%2\n" 98 "xor %0,%0,%2\n"
108 PPC405_ERR77(0,%3) 99 PPC405_ERR77(0,%3)
109 STCXL " %0,0,%3\n" 100 PPC_STLCX "%0,0,%3\n"
110 "bne- 1b" 101 "bne- 1b"
111 : "=&r"(old), "=m"(*p) 102 : "=&r"(old), "=m"(*p)
112 : "r"(mask), "r"(p), "m"(*p) 103 : "r"(mask), "r"(p), "m"(*p)
@@ -122,10 +113,10 @@ static __inline__ int test_and_set_bit(unsigned long nr,
122 113
123 __asm__ __volatile__( 114 __asm__ __volatile__(
124 EIEIO_ON_SMP 115 EIEIO_ON_SMP
125"1:" LARXL " %0,0,%3 # test_and_set_bit\n" 116"1:" PPC_LLARX "%0,0,%3 # test_and_set_bit\n"
126 "or %1,%0,%2 \n" 117 "or %1,%0,%2 \n"
127 PPC405_ERR77(0,%3) 118 PPC405_ERR77(0,%3)
128 STCXL " %1,0,%3 \n" 119 PPC_STLCX "%1,0,%3 \n"
129 "bne- 1b" 120 "bne- 1b"
130 ISYNC_ON_SMP 121 ISYNC_ON_SMP
131 : "=&r" (old), "=&r" (t) 122 : "=&r" (old), "=&r" (t)
@@ -144,10 +135,10 @@ static __inline__ int test_and_clear_bit(unsigned long nr,
144 135
145 __asm__ __volatile__( 136 __asm__ __volatile__(
146 EIEIO_ON_SMP 137 EIEIO_ON_SMP
147"1:" LARXL " %0,0,%3 # test_and_clear_bit\n" 138"1:" PPC_LLARX "%0,0,%3 # test_and_clear_bit\n"
148 "andc %1,%0,%2 \n" 139 "andc %1,%0,%2 \n"
149 PPC405_ERR77(0,%3) 140 PPC405_ERR77(0,%3)
150 STCXL " %1,0,%3 \n" 141 PPC_STLCX "%1,0,%3 \n"
151 "bne- 1b" 142 "bne- 1b"
152 ISYNC_ON_SMP 143 ISYNC_ON_SMP
153 : "=&r" (old), "=&r" (t) 144 : "=&r" (old), "=&r" (t)
@@ -166,10 +157,10 @@ static __inline__ int test_and_change_bit(unsigned long nr,
166 157
167 __asm__ __volatile__( 158 __asm__ __volatile__(
168 EIEIO_ON_SMP 159 EIEIO_ON_SMP
169"1:" LARXL " %0,0,%3 # test_and_change_bit\n" 160"1:" PPC_LLARX "%0,0,%3 # test_and_change_bit\n"
170 "xor %1,%0,%2 \n" 161 "xor %1,%0,%2 \n"
171 PPC405_ERR77(0,%3) 162 PPC405_ERR77(0,%3)
172 STCXL " %1,0,%3 \n" 163 PPC_STLCX "%1,0,%3 \n"
173 "bne- 1b" 164 "bne- 1b"
174 ISYNC_ON_SMP 165 ISYNC_ON_SMP
175 : "=&r" (old), "=&r" (t) 166 : "=&r" (old), "=&r" (t)
@@ -184,9 +175,9 @@ static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
184 unsigned long old; 175 unsigned long old;
185 176
186 __asm__ __volatile__( 177 __asm__ __volatile__(
187"1:" LARXL " %0,0,%3 # set_bit\n" 178"1:" PPC_LLARX "%0,0,%3 # set_bits\n"
188 "or %0,%0,%2\n" 179 "or %0,%0,%2\n"
189 STCXL " %0,0,%3\n" 180 PPC_STLCX "%0,0,%3\n"
190 "bne- 1b" 181 "bne- 1b"
191 : "=&r" (old), "=m" (*addr) 182 : "=&r" (old), "=m" (*addr)
192 : "r" (mask), "r" (addr), "m" (*addr) 183 : "r" (mask), "r" (addr), "m" (*addr)
@@ -268,7 +259,7 @@ static __inline__ int __ilog2(unsigned long x)
268{ 259{
269 int lz; 260 int lz;
270 261
271 asm (CNTLZL " %0,%1" : "=r" (lz) : "r" (x)); 262 asm (PPC_CNTLZL "%0,%1" : "=r" (lz) : "r" (x));
272 return BITS_PER_LONG - 1 - lz; 263 return BITS_PER_LONG - 1 - lz;
273} 264}
274 265
diff --git a/include/asm-powerpc/bug.h b/include/asm-powerpc/bug.h
index d625ee55f957..b001ecb3cd99 100644
--- a/include/asm-powerpc/bug.h
+++ b/include/asm-powerpc/bug.h
@@ -1,6 +1,7 @@
1#ifndef _ASM_POWERPC_BUG_H 1#ifndef _ASM_POWERPC_BUG_H
2#define _ASM_POWERPC_BUG_H 2#define _ASM_POWERPC_BUG_H
3 3
4#include <asm/asm-compat.h>
4/* 5/*
5 * Define an illegal instr to trap on the bug. 6 * Define an illegal instr to trap on the bug.
6 * We don't use 0 because that marks the end of a function 7 * We don't use 0 because that marks the end of a function
@@ -11,14 +12,6 @@
11 12
12#ifndef __ASSEMBLY__ 13#ifndef __ASSEMBLY__
13 14
14#ifdef __powerpc64__
15#define BUG_TABLE_ENTRY ".llong"
16#define BUG_TRAP_OP "tdnei"
17#else
18#define BUG_TABLE_ENTRY ".long"
19#define BUG_TRAP_OP "twnei"
20#endif /* __powerpc64__ */
21
22struct bug_entry { 15struct bug_entry {
23 unsigned long bug_addr; 16 unsigned long bug_addr;
24 long line; 17 long line;
@@ -40,16 +33,16 @@ struct bug_entry *find_bug(unsigned long bugaddr);
40 __asm__ __volatile__( \ 33 __asm__ __volatile__( \
41 "1: twi 31,0,0\n" \ 34 "1: twi 31,0,0\n" \
42 ".section __bug_table,\"a\"\n" \ 35 ".section __bug_table,\"a\"\n" \
43 "\t"BUG_TABLE_ENTRY" 1b,%0,%1,%2\n" \ 36 "\t"PPC_LONG" 1b,%0,%1,%2\n" \
44 ".previous" \ 37 ".previous" \
45 : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \ 38 : : "i" (__LINE__), "i" (__FILE__), "i" (__FUNCTION__)); \
46} while (0) 39} while (0)
47 40
48#define BUG_ON(x) do { \ 41#define BUG_ON(x) do { \
49 __asm__ __volatile__( \ 42 __asm__ __volatile__( \
50 "1: "BUG_TRAP_OP" %0,0\n" \ 43 "1: "PPC_TLNEI" %0,0\n" \
51 ".section __bug_table,\"a\"\n" \ 44 ".section __bug_table,\"a\"\n" \
52 "\t"BUG_TABLE_ENTRY" 1b,%1,%2,%3\n" \ 45 "\t"PPC_LONG" 1b,%1,%2,%3\n" \
53 ".previous" \ 46 ".previous" \
54 : : "r" ((long)(x)), "i" (__LINE__), \ 47 : : "r" ((long)(x)), "i" (__LINE__), \
55 "i" (__FILE__), "i" (__FUNCTION__)); \ 48 "i" (__FILE__), "i" (__FUNCTION__)); \
@@ -57,9 +50,9 @@ struct bug_entry *find_bug(unsigned long bugaddr);
57 50
58#define WARN_ON(x) do { \ 51#define WARN_ON(x) do { \
59 __asm__ __volatile__( \ 52 __asm__ __volatile__( \
60 "1: "BUG_TRAP_OP" %0,0\n" \ 53 "1: "PPC_TLNEI" %0,0\n" \
61 ".section __bug_table,\"a\"\n" \ 54 ".section __bug_table,\"a\"\n" \
62 "\t"BUG_TABLE_ENTRY" 1b,%1,%2,%3\n" \ 55 "\t"PPC_LONG" 1b,%1,%2,%3\n" \
63 ".previous" \ 56 ".previous" \
64 : : "r" ((long)(x)), \ 57 : : "r" ((long)(x)), \
65 "i" (__LINE__ + BUG_WARNING_TRAP), \ 58 "i" (__LINE__ + BUG_WARNING_TRAP), \
diff --git a/include/asm-powerpc/cache.h b/include/asm-powerpc/cache.h
new file mode 100644
index 000000000000..26ce502e76e8
--- /dev/null
+++ b/include/asm-powerpc/cache.h
@@ -0,0 +1,40 @@
1#ifndef _ASM_POWERPC_CACHE_H
2#define _ASM_POWERPC_CACHE_H
3
4#ifdef __KERNEL__
5
6#include <linux/config.h>
7
8/* bytes per L1 cache line */
9#if defined(CONFIG_8xx) || defined(CONFIG_403GCX)
10#define L1_CACHE_SHIFT 4
11#define MAX_COPY_PREFETCH 1
12#elif defined(CONFIG_PPC32)
13#define L1_CACHE_SHIFT 5
14#define MAX_COPY_PREFETCH 4
15#else /* CONFIG_PPC64 */
16#define L1_CACHE_SHIFT 7
17#endif
18
19#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
20
21#define SMP_CACHE_BYTES L1_CACHE_BYTES
22#define L1_CACHE_SHIFT_MAX 7 /* largest L1 which this arch supports */
23
24#if defined(__powerpc64__) && !defined(__ASSEMBLY__)
25struct ppc64_caches {
26 u32 dsize; /* L1 d-cache size */
27 u32 dline_size; /* L1 d-cache line size */
28 u32 log_dline_size;
29 u32 dlines_per_page;
30 u32 isize; /* L1 i-cache size */
31 u32 iline_size; /* L1 i-cache line size */
32 u32 log_iline_size;
33 u32 ilines_per_page;
34};
35
36extern struct ppc64_caches ppc64_caches;
37#endif /* __powerpc64__ && ! __ASSEMBLY__ */
38
39#endif /* __KERNEL__ */
40#endif /* _ASM_POWERPC_CACHE_H */
diff --git a/include/asm-powerpc/cacheflush.h b/include/asm-powerpc/cacheflush.h
new file mode 100644
index 000000000000..8a740c88d93d
--- /dev/null
+++ b/include/asm-powerpc/cacheflush.h
@@ -0,0 +1,68 @@
1/*
2 * This program is free software; you can redistribute it and/or
3 * modify it under the terms of the GNU General Public License
4 * as published by the Free Software Foundation; either version
5 * 2 of the License, or (at your option) any later version.
6 */
7#ifndef _ASM_POWERPC_CACHEFLUSH_H
8#define _ASM_POWERPC_CACHEFLUSH_H
9
10#ifdef __KERNEL__
11
12#include <linux/mm.h>
13#include <asm/cputable.h>
14
15/*
16 * No cache flushing is required when address mappings are changed,
17 * because the caches on PowerPCs are physically addressed.
18 */
19#define flush_cache_all() do { } while (0)
20#define flush_cache_mm(mm) do { } while (0)
21#define flush_cache_range(vma, start, end) do { } while (0)
22#define flush_cache_page(vma, vmaddr, pfn) do { } while (0)
23#define flush_icache_page(vma, page) do { } while (0)
24#define flush_cache_vmap(start, end) do { } while (0)
25#define flush_cache_vunmap(start, end) do { } while (0)
26
27extern void flush_dcache_page(struct page *page);
28#define flush_dcache_mmap_lock(mapping) do { } while (0)
29#define flush_dcache_mmap_unlock(mapping) do { } while (0)
30
31extern void __flush_icache_range(unsigned long, unsigned long);
32static inline void flush_icache_range(unsigned long start, unsigned long stop)
33{
34 if (!cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
35 __flush_icache_range(start, stop);
36}
37
38extern void flush_icache_user_range(struct vm_area_struct *vma,
39 struct page *page, unsigned long addr,
40 int len);
41extern void __flush_dcache_icache(void *page_va);
42extern void flush_dcache_icache_page(struct page *page);
43#if defined(CONFIG_PPC32) && !defined(CONFIG_BOOKE)
44extern void __flush_dcache_icache_phys(unsigned long physaddr);
45#endif /* CONFIG_PPC32 && !CONFIG_BOOKE */
46
47extern void flush_dcache_range(unsigned long start, unsigned long stop);
48#ifdef CONFIG_PPC32
49extern void clean_dcache_range(unsigned long start, unsigned long stop);
50extern void invalidate_dcache_range(unsigned long start, unsigned long stop);
51#endif /* CONFIG_PPC32 */
52#ifdef CONFIG_PPC64
53extern void flush_inval_dcache_range(unsigned long start, unsigned long stop);
54extern void flush_dcache_phys_range(unsigned long start, unsigned long stop);
55#endif
56
57#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
58 do { \
59 memcpy(dst, src, len); \
60 flush_icache_user_range(vma, page, vaddr, len); \
61 } while (0)
62#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
63 memcpy(dst, src, len)
64
65
66#endif /* __KERNEL__ */
67
68#endif /* _ASM_POWERPC_CACHEFLUSH_H */
diff --git a/include/asm-powerpc/compat.h b/include/asm-powerpc/compat.h
new file mode 100644
index 000000000000..4db4360c4d4a
--- /dev/null
+++ b/include/asm-powerpc/compat.h
@@ -0,0 +1,205 @@
1#ifndef _ASM_POWERPC_COMPAT_H
2#define _ASM_POWERPC_COMPAT_H
3/*
4 * Architecture specific compatibility types
5 */
6#include <linux/types.h>
7#include <linux/sched.h>
8
9#define COMPAT_USER_HZ 100
10
11typedef u32 compat_size_t;
12typedef s32 compat_ssize_t;
13typedef s32 compat_time_t;
14typedef s32 compat_clock_t;
15typedef s32 compat_pid_t;
16typedef u32 __compat_uid_t;
17typedef u32 __compat_gid_t;
18typedef u32 __compat_uid32_t;
19typedef u32 __compat_gid32_t;
20typedef u32 compat_mode_t;
21typedef u32 compat_ino_t;
22typedef u32 compat_dev_t;
23typedef s32 compat_off_t;
24typedef s64 compat_loff_t;
25typedef s16 compat_nlink_t;
26typedef u16 compat_ipc_pid_t;
27typedef s32 compat_daddr_t;
28typedef u32 compat_caddr_t;
29typedef __kernel_fsid_t compat_fsid_t;
30typedef s32 compat_key_t;
31typedef s32 compat_timer_t;
32
33typedef s32 compat_int_t;
34typedef s32 compat_long_t;
35typedef u32 compat_uint_t;
36typedef u32 compat_ulong_t;
37
38struct compat_timespec {
39 compat_time_t tv_sec;
40 s32 tv_nsec;
41};
42
43struct compat_timeval {
44 compat_time_t tv_sec;
45 s32 tv_usec;
46};
47
48struct compat_stat {
49 compat_dev_t st_dev;
50 compat_ino_t st_ino;
51 compat_mode_t st_mode;
52 compat_nlink_t st_nlink;
53 __compat_uid32_t st_uid;
54 __compat_gid32_t st_gid;
55 compat_dev_t st_rdev;
56 compat_off_t st_size;
57 compat_off_t st_blksize;
58 compat_off_t st_blocks;
59 compat_time_t st_atime;
60 u32 st_atime_nsec;
61 compat_time_t st_mtime;
62 u32 st_mtime_nsec;
63 compat_time_t st_ctime;
64 u32 st_ctime_nsec;
65 u32 __unused4[2];
66};
67
68struct compat_flock {
69 short l_type;
70 short l_whence;
71 compat_off_t l_start;
72 compat_off_t l_len;
73 compat_pid_t l_pid;
74};
75
76#define F_GETLK64 12 /* using 'struct flock64' */
77#define F_SETLK64 13
78#define F_SETLKW64 14
79
80struct compat_flock64 {
81 short l_type;
82 short l_whence;
83 compat_loff_t l_start;
84 compat_loff_t l_len;
85 compat_pid_t l_pid;
86};
87
88struct compat_statfs {
89 int f_type;
90 int f_bsize;
91 int f_blocks;
92 int f_bfree;
93 int f_bavail;
94 int f_files;
95 int f_ffree;
96 compat_fsid_t f_fsid;
97 int f_namelen; /* SunOS ignores this field. */
98 int f_frsize;
99 int f_spare[5];
100};
101
102#define COMPAT_RLIM_OLD_INFINITY 0x7fffffff
103#define COMPAT_RLIM_INFINITY 0xffffffff
104
105typedef u32 compat_old_sigset_t;
106
107#define _COMPAT_NSIG 64
108#define _COMPAT_NSIG_BPW 32
109
110typedef u32 compat_sigset_word;
111
112#define COMPAT_OFF_T_MAX 0x7fffffff
113#define COMPAT_LOFF_T_MAX 0x7fffffffffffffffL
114
115/*
116 * A pointer passed in from user mode. This should not
117 * be used for syscall parameters, just declare them
118 * as pointers because the syscall entry code will have
119 * appropriately comverted them already.
120 */
121typedef u32 compat_uptr_t;
122
123static inline void __user *compat_ptr(compat_uptr_t uptr)
124{
125 return (void __user *)(unsigned long)uptr;
126}
127
128static inline void __user *compat_alloc_user_space(long len)
129{
130 struct pt_regs *regs = current->thread.regs;
131 unsigned long usp = regs->gpr[1];
132
133 /*
134 * We cant access below the stack pointer in the 32bit ABI and
135 * can access 288 bytes in the 64bit ABI
136 */
137 if (!(test_thread_flag(TIF_32BIT)))
138 usp -= 288;
139
140 return (void __user *) (usp - len);
141}
142
143/*
144 * ipc64_perm is actually 32/64bit clean but since the compat layer refers to
145 * it we may as well define it.
146 */
147struct compat_ipc64_perm {
148 compat_key_t key;
149 __compat_uid_t uid;
150 __compat_gid_t gid;
151 __compat_uid_t cuid;
152 __compat_gid_t cgid;
153 compat_mode_t mode;
154 unsigned int seq;
155 unsigned int __pad2;
156 unsigned long __unused1; /* yes they really are 64bit pads */
157 unsigned long __unused2;
158};
159
160struct compat_semid64_ds {
161 struct compat_ipc64_perm sem_perm;
162 unsigned int __unused1;
163 compat_time_t sem_otime;
164 unsigned int __unused2;
165 compat_time_t sem_ctime;
166 compat_ulong_t sem_nsems;
167 compat_ulong_t __unused3;
168 compat_ulong_t __unused4;
169};
170
171struct compat_msqid64_ds {
172 struct compat_ipc64_perm msg_perm;
173 unsigned int __unused1;
174 compat_time_t msg_stime;
175 unsigned int __unused2;
176 compat_time_t msg_rtime;
177 unsigned int __unused3;
178 compat_time_t msg_ctime;
179 compat_ulong_t msg_cbytes;
180 compat_ulong_t msg_qnum;
181 compat_ulong_t msg_qbytes;
182 compat_pid_t msg_lspid;
183 compat_pid_t msg_lrpid;
184 compat_ulong_t __unused4;
185 compat_ulong_t __unused5;
186};
187
188struct compat_shmid64_ds {
189 struct compat_ipc64_perm shm_perm;
190 unsigned int __unused1;
191 compat_time_t shm_atime;
192 unsigned int __unused2;
193 compat_time_t shm_dtime;
194 unsigned int __unused3;
195 compat_time_t shm_ctime;
196 unsigned int __unused4;
197 compat_size_t shm_segsz;
198 compat_pid_t shm_cpid;
199 compat_pid_t shm_lpid;
200 compat_ulong_t shm_nattch;
201 compat_ulong_t __unused5;
202 compat_ulong_t __unused6;
203};
204
205#endif /* _ASM_POWERPC_COMPAT_H */
diff --git a/include/asm-powerpc/cputable.h b/include/asm-powerpc/cputable.h
index 79a0556a0ab8..04e2726002cf 100644
--- a/include/asm-powerpc/cputable.h
+++ b/include/asm-powerpc/cputable.h
@@ -2,7 +2,7 @@
2#define __ASM_POWERPC_CPUTABLE_H 2#define __ASM_POWERPC_CPUTABLE_H
3 3
4#include <linux/config.h> 4#include <linux/config.h>
5#include <asm/ppc_asm.h> /* for ASM_CONST */ 5#include <asm/asm-compat.h>
6 6
7#define PPC_FEATURE_32 0x80000000 7#define PPC_FEATURE_32 0x80000000
8#define PPC_FEATURE_64 0x40000000 8#define PPC_FEATURE_64 0x40000000
@@ -16,6 +16,10 @@
16#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 16#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
17#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 17#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
18#define PPC_FEATURE_NO_TB 0x00100000 18#define PPC_FEATURE_NO_TB 0x00100000
19#define PPC_FEATURE_POWER4 0x00080000
20#define PPC_FEATURE_POWER5 0x00040000
21#define PPC_FEATURE_POWER5_PLUS 0x00020000
22#define PPC_FEATURE_CELL 0x00010000
19 23
20#ifdef __KERNEL__ 24#ifdef __KERNEL__
21#ifndef __ASSEMBLY__ 25#ifndef __ASSEMBLY__
diff --git a/include/asm-powerpc/current.h b/include/asm-powerpc/current.h
new file mode 100644
index 000000000000..82cd4a9ca99a
--- /dev/null
+++ b/include/asm-powerpc/current.h
@@ -0,0 +1,27 @@
1#ifndef _ASM_POWERPC_CURRENT_H
2#define _ASM_POWERPC_CURRENT_H
3
4/*
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
9 */
10
11struct task_struct;
12
13#ifdef __powerpc64__
14#include <asm/paca.h>
15
16#define current (get_paca()->__current)
17
18#else
19
20/*
21 * We keep `current' in r2 for speed.
22 */
23register struct task_struct *current asm ("r2");
24
25#endif
26
27#endif /* _ASM_POWERPC_CURRENT_H */
diff --git a/include/asm-powerpc/eeh_event.h b/include/asm-powerpc/eeh_event.h
new file mode 100644
index 000000000000..d168a30b3866
--- /dev/null
+++ b/include/asm-powerpc/eeh_event.h
@@ -0,0 +1,52 @@
1/*
2 * eeh_event.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 *
18 * Copyright (c) 2005 Linas Vepstas <linas@linas.org>
19 */
20
21#ifndef ASM_PPC64_EEH_EVENT_H
22#define ASM_PPC64_EEH_EVENT_H
23
24/** EEH event -- structure holding pci controller data that describes
25 * a change in the isolation status of a PCI slot. A pointer
26 * to this struct is passed as the data pointer in a notify callback.
27 */
28struct eeh_event {
29 struct list_head list;
30 struct device_node *dn; /* struct device node */
31 struct pci_dev *dev; /* affected device */
32 int state;
33 int time_unavail; /* milliseconds until device might be available */
34};
35
36/**
37 * eeh_send_failure_event - generate a PCI error event
38 * @dev pci device
39 *
40 * This routine builds a PCI error event which will be delivered
41 * to all listeners on the peh_notifier_chain.
42 *
43 * This routine can be called within an interrupt context;
44 * the actual event will be delivered in a normal context
45 * (from a workqueue).
46 */
47int eeh_send_failure_event (struct device_node *dn,
48 struct pci_dev *dev,
49 int reset_state,
50 int time_unavail);
51
52#endif /* ASM_PPC64_EEH_EVENT_H */
diff --git a/include/asm-powerpc/firmware.h b/include/asm-powerpc/firmware.h
index 806c142ae9ea..12fabbcb04f0 100644
--- a/include/asm-powerpc/firmware.h
+++ b/include/asm-powerpc/firmware.h
@@ -43,6 +43,7 @@
43#define FW_FEATURE_ISERIES (1UL<<21) 43#define FW_FEATURE_ISERIES (1UL<<21)
44 44
45enum { 45enum {
46#ifdef CONFIG_PPC64
46 FW_FEATURE_PSERIES_POSSIBLE = FW_FEATURE_PFT | FW_FEATURE_TCE | 47 FW_FEATURE_PSERIES_POSSIBLE = FW_FEATURE_PFT | FW_FEATURE_TCE |
47 FW_FEATURE_SPRG0 | FW_FEATURE_DABR | FW_FEATURE_COPY | 48 FW_FEATURE_SPRG0 | FW_FEATURE_DABR | FW_FEATURE_COPY |
48 FW_FEATURE_ASR | FW_FEATURE_DEBUG | FW_FEATURE_TERM | 49 FW_FEATURE_ASR | FW_FEATURE_DEBUG | FW_FEATURE_TERM |
@@ -70,6 +71,11 @@ enum {
70 FW_FEATURE_ISERIES_ALWAYS & 71 FW_FEATURE_ISERIES_ALWAYS &
71#endif 72#endif
72 FW_FEATURE_POSSIBLE, 73 FW_FEATURE_POSSIBLE,
74
75#else /* CONFIG_PPC64 */
76 FW_FEATURE_POSSIBLE = 0,
77 FW_FEATURE_ALWAYS = 0,
78#endif
73}; 79};
74 80
75/* This is used to identify firmware features which are available 81/* This is used to identify firmware features which are available
diff --git a/include/asm-powerpc/futex.h b/include/asm-powerpc/futex.h
index 37c94e52ab6d..f0319d50b129 100644
--- a/include/asm-powerpc/futex.h
+++ b/include/asm-powerpc/futex.h
@@ -7,13 +7,14 @@
7#include <asm/errno.h> 7#include <asm/errno.h>
8#include <asm/synch.h> 8#include <asm/synch.h>
9#include <asm/uaccess.h> 9#include <asm/uaccess.h>
10#include <asm/ppc_asm.h> 10#include <asm/asm-compat.h>
11 11
12#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ 12#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
13 __asm__ __volatile ( \ 13 __asm__ __volatile ( \
14 SYNC_ON_SMP \ 14 SYNC_ON_SMP \
15"1: lwarx %0,0,%2\n" \ 15"1: lwarx %0,0,%2\n" \
16 insn \ 16 insn \
17 PPC405_ERR77(0, %2) \
17"2: stwcx. %1,0,%2\n" \ 18"2: stwcx. %1,0,%2\n" \
18 "bne- 1b\n" \ 19 "bne- 1b\n" \
19 "li %1,0\n" \ 20 "li %1,0\n" \
@@ -23,7 +24,7 @@
23 ".previous\n" \ 24 ".previous\n" \
24 ".section __ex_table,\"a\"\n" \ 25 ".section __ex_table,\"a\"\n" \
25 ".align 3\n" \ 26 ".align 3\n" \
26 DATAL " 1b,4b,2b,4b\n" \ 27 PPC_LONG "1b,4b,2b,4b\n" \
27 ".previous" \ 28 ".previous" \
28 : "=&r" (oldval), "=&r" (ret) \ 29 : "=&r" (oldval), "=&r" (ret) \
29 : "b" (uaddr), "i" (-EFAULT), "1" (oparg) \ 30 : "b" (uaddr), "i" (-EFAULT), "1" (oparg) \
diff --git a/include/asm-powerpc/hvcall.h b/include/asm-powerpc/hvcall.h
new file mode 100644
index 000000000000..d36da61dbc53
--- /dev/null
+++ b/include/asm-powerpc/hvcall.h
@@ -0,0 +1,173 @@
1#ifndef _ASM_POWERPC_HVCALL_H
2#define _ASM_POWERPC_HVCALL_H
3
4#define HVSC .long 0x44000022
5
6#define H_Success 0
7#define H_Busy 1 /* Hardware busy -- retry later */
8#define H_Constrained 4 /* Resource request constrained to max allowed */
9#define H_LongBusyStartRange 9900 /* Start of long busy range */
10#define H_LongBusyOrder1msec 9900 /* Long busy, hint that 1msec is a good time to retry */
11#define H_LongBusyOrder10msec 9901 /* Long busy, hint that 10msec is a good time to retry */
12#define H_LongBusyOrder100msec 9902 /* Long busy, hint that 100msec is a good time to retry */
13#define H_LongBusyOrder1sec 9903 /* Long busy, hint that 1sec is a good time to retry */
14#define H_LongBusyOrder10sec 9904 /* Long busy, hint that 10sec is a good time to retry */
15#define H_LongBusyOrder100sec 9905 /* Long busy, hint that 100sec is a good time to retry */
16#define H_LongBusyEndRange 9905 /* End of long busy range */
17#define H_Hardware -1 /* Hardware error */
18#define H_Function -2 /* Function not supported */
19#define H_Privilege -3 /* Caller not privileged */
20#define H_Parameter -4 /* Parameter invalid, out-of-range or conflicting */
21#define H_Bad_Mode -5 /* Illegal msr value */
22#define H_PTEG_Full -6 /* PTEG is full */
23#define H_Not_Found -7 /* PTE was not found" */
24#define H_Reserved_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
25#define H_NoMem -9
26#define H_Authority -10
27#define H_Permission -11
28#define H_Dropped -12
29#define H_SourceParm -13
30#define H_DestParm -14
31#define H_RemoteParm -15
32#define H_Resource -16
33
34/* Long Busy is a condition that can be returned by the firmware
35 * when a call cannot be completed now, but the identical call
36 * should be retried later. This prevents calls blocking in the
37 * firmware for long periods of time. Annoyingly the firmware can return
38 * a range of return codes, hinting at how long we should wait before
39 * retrying. If you don't care for the hint, the macro below is a good
40 * way to check for the long_busy return codes
41 */
42#define H_isLongBusy(x) ((x >= H_LongBusyStartRange) && (x <= H_LongBusyEndRange))
43
44/* Flags */
45#define H_LARGE_PAGE (1UL<<(63-16))
46#define H_EXACT (1UL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
47#define H_R_XLATE (1UL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
48#define H_READ_4 (1UL<<(63-26)) /* Return 4 PTEs */
49#define H_AVPN (1UL<<(63-32)) /* An avpn is provided as a sanity test */
50#define H_ANDCOND (1UL<<(63-33))
51#define H_ICACHE_INVALIDATE (1UL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
52#define H_ICACHE_SYNCHRONIZE (1UL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
53#define H_ZERO_PAGE (1UL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
54#define H_COPY_PAGE (1UL<<(63-49))
55#define H_N (1UL<<(63-61))
56#define H_PP1 (1UL<<(63-62))
57#define H_PP2 (1UL<<(63-63))
58
59/* DABRX flags */
60#define H_DABRX_HYPERVISOR (1UL<<(63-61))
61#define H_DABRX_KERNEL (1UL<<(63-62))
62#define H_DABRX_USER (1UL<<(63-63))
63
64/* pSeries hypervisor opcodes */
65#define H_REMOVE 0x04
66#define H_ENTER 0x08
67#define H_READ 0x0c
68#define H_CLEAR_MOD 0x10
69#define H_CLEAR_REF 0x14
70#define H_PROTECT 0x18
71#define H_GET_TCE 0x1c
72#define H_PUT_TCE 0x20
73#define H_SET_SPRG0 0x24
74#define H_SET_DABR 0x28
75#define H_PAGE_INIT 0x2c
76#define H_SET_ASR 0x30
77#define H_ASR_ON 0x34
78#define H_ASR_OFF 0x38
79#define H_LOGICAL_CI_LOAD 0x3c
80#define H_LOGICAL_CI_STORE 0x40
81#define H_LOGICAL_CACHE_LOAD 0x44
82#define H_LOGICAL_CACHE_STORE 0x48
83#define H_LOGICAL_ICBI 0x4c
84#define H_LOGICAL_DCBF 0x50
85#define H_GET_TERM_CHAR 0x54
86#define H_PUT_TERM_CHAR 0x58
87#define H_REAL_TO_LOGICAL 0x5c
88#define H_HYPERVISOR_DATA 0x60
89#define H_EOI 0x64
90#define H_CPPR 0x68
91#define H_IPI 0x6c
92#define H_IPOLL 0x70
93#define H_XIRR 0x74
94#define H_PERFMON 0x7c
95#define H_MIGRATE_DMA 0x78
96#define H_REGISTER_VPA 0xDC
97#define H_CEDE 0xE0
98#define H_CONFER 0xE4
99#define H_PROD 0xE8
100#define H_GET_PPP 0xEC
101#define H_SET_PPP 0xF0
102#define H_PURR 0xF4
103#define H_PIC 0xF8
104#define H_REG_CRQ 0xFC
105#define H_FREE_CRQ 0x100
106#define H_VIO_SIGNAL 0x104
107#define H_SEND_CRQ 0x108
108#define H_COPY_RDMA 0x110
109#define H_SET_XDABR 0x134
110#define H_STUFF_TCE 0x138
111#define H_PUT_TCE_INDIRECT 0x13C
112#define H_VTERM_PARTNER_INFO 0x150
113#define H_REGISTER_VTERM 0x154
114#define H_FREE_VTERM 0x158
115#define H_POLL_PENDING 0x1D8
116
117#ifndef __ASSEMBLY__
118
119/* plpar_hcall() -- Generic call interface using above opcodes
120 *
121 * The actual call interface is a hypervisor call instruction with
122 * the opcode in R3 and input args in R4-R7.
123 * Status is returned in R3 with variable output values in R4-R11.
124 * Only H_PTE_READ with H_READ_4 uses R6-R11 so we ignore it for now
125 * and return only two out args which MUST ALWAYS BE PROVIDED.
126 */
127long plpar_hcall(unsigned long opcode,
128 unsigned long arg1,
129 unsigned long arg2,
130 unsigned long arg3,
131 unsigned long arg4,
132 unsigned long *out1,
133 unsigned long *out2,
134 unsigned long *out3);
135
136/* Same as plpar_hcall but for those opcodes that return no values
137 * other than status. Slightly more efficient.
138 */
139long plpar_hcall_norets(unsigned long opcode, ...);
140
141/*
142 * Special hcall interface for ibmveth support.
143 * Takes 8 input parms. Returns a rc and stores the
144 * R4 return value in *out1.
145 */
146long plpar_hcall_8arg_2ret(unsigned long opcode,
147 unsigned long arg1,
148 unsigned long arg2,
149 unsigned long arg3,
150 unsigned long arg4,
151 unsigned long arg5,
152 unsigned long arg6,
153 unsigned long arg7,
154 unsigned long arg8,
155 unsigned long *out1);
156
157/* plpar_hcall_4out()
158 *
159 * same as plpar_hcall except with 4 output arguments.
160 *
161 */
162long plpar_hcall_4out(unsigned long opcode,
163 unsigned long arg1,
164 unsigned long arg2,
165 unsigned long arg3,
166 unsigned long arg4,
167 unsigned long *out1,
168 unsigned long *out2,
169 unsigned long *out3,
170 unsigned long *out4);
171
172#endif /* __ASSEMBLY__ */
173#endif /* _ASM_POWERPC_HVCALL_H */
diff --git a/include/asm-powerpc/hw_irq.h b/include/asm-powerpc/hw_irq.h
index c37b31b96337..26b89d859c56 100644
--- a/include/asm-powerpc/hw_irq.h
+++ b/include/asm-powerpc/hw_irq.h
@@ -12,7 +12,6 @@
12#include <asm/processor.h> 12#include <asm/processor.h>
13 13
14extern void timer_interrupt(struct pt_regs *); 14extern void timer_interrupt(struct pt_regs *);
15extern void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq);
16 15
17#ifdef CONFIG_PPC_ISERIES 16#ifdef CONFIG_PPC_ISERIES
18 17
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h
index b3935ea28fff..c9fbcede0ef9 100644
--- a/include/asm-powerpc/irq.h
+++ b/include/asm-powerpc/irq.h
@@ -429,7 +429,6 @@ extern u64 ppc64_interrupt_controller;
429#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) 429#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
430/* pedantic: these are long because they are used with set_bit --RR */ 430/* pedantic: these are long because they are used with set_bit --RR */
431extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; 431extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
432extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS];
433extern atomic_t ppc_n_lost_interrupts; 432extern atomic_t ppc_n_lost_interrupts;
434 433
435#define virt_irq_create_mapping(x) (x) 434#define virt_irq_create_mapping(x) (x)
@@ -488,8 +487,8 @@ extern struct thread_info *softirq_ctx[NR_CPUS];
488 487
489extern void irq_ctx_init(void); 488extern void irq_ctx_init(void);
490extern void call_do_softirq(struct thread_info *tp); 489extern void call_do_softirq(struct thread_info *tp);
491extern int call_handle_IRQ_event(int irq, struct pt_regs *regs, 490extern int call___do_IRQ(int irq, struct pt_regs *regs,
492 struct irqaction *action, struct thread_info *tp); 491 struct thread_info *tp);
493 492
494#define __ARCH_HAS_DO_SOFTIRQ 493#define __ARCH_HAS_DO_SOFTIRQ
495 494
diff --git a/include/asm-powerpc/lppaca.h b/include/asm-powerpc/lppaca.h
new file mode 100644
index 000000000000..c1bedab1515b
--- /dev/null
+++ b/include/asm-powerpc/lppaca.h
@@ -0,0 +1,131 @@
1/*
2 * lppaca.h
3 * Copyright (C) 2001 Mike Corrigan IBM Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19#ifndef _ASM_POWERPC_LPPACA_H
20#define _ASM_POWERPC_LPPACA_H
21
22//=============================================================================
23//
24// This control block contains the data that is shared between the
25// hypervisor (PLIC) and the OS.
26//
27//
28//----------------------------------------------------------------------------
29#include <asm/types.h>
30
31struct lppaca {
32//=============================================================================
33// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
34// NOTE: The xDynXyz fields are fields that will be dynamically changed by
35// PLIC when preparing to bring a processor online or when dispatching a
36// virtual processor!
37//=============================================================================
38 u32 desc; // Eye catcher 0xD397D781 x00-x03
39 u16 size; // Size of this struct x04-x05
40 u16 reserved1; // Reserved x06-x07
41 u16 reserved2:14; // Reserved x08-x09
42 u8 shared_proc:1; // Shared processor indicator ...
43 u8 secondary_thread:1; // Secondary thread indicator ...
44 volatile u8 dyn_proc_status:8; // Dynamic Status of this proc x0A-x0A
45 u8 secondary_thread_count; // Secondary thread count x0B-x0B
46 volatile u16 dyn_hv_phys_proc_index;// Dynamic HV Physical Proc Index0C-x0D
47 volatile u16 dyn_hv_log_proc_index;// Dynamic HV Logical Proc Indexx0E-x0F
48 u32 decr_val; // Value for Decr programming x10-x13
49 u32 pmc_val; // Value for PMC regs x14-x17
50 volatile u32 dyn_hw_node_id; // Dynamic Hardware Node id x18-x1B
51 volatile u32 dyn_hw_proc_id; // Dynamic Hardware Proc Id x1C-x1F
52 volatile u32 dyn_pir; // Dynamic ProcIdReg value x20-x23
53 u32 dsei_data; // DSEI data x24-x27
54 u64 sprg3; // SPRG3 value x28-x2F
55 u8 reserved3[80]; // Reserved x30-x7F
56
57//=============================================================================
58// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
59//=============================================================================
60 // This Dword contains a byte for each type of interrupt that can occur.
61 // The IPI is a count while the others are just a binary 1 or 0.
62 union {
63 u64 any_int;
64 struct {
65 u16 reserved; // Reserved - cleared by #mpasmbl
66 u8 xirr_int; // Indicates xXirrValue is valid or Immed IO
67 u8 ipi_cnt; // IPI Count
68 u8 decr_int; // DECR interrupt occurred
69 u8 pdc_int; // PDC interrupt occurred
70 u8 quantum_int; // Interrupt quantum reached
71 u8 old_plic_deferred_ext_int; // Old PLIC has a deferred XIRR pending
72 } fields;
73 } int_dword;
74
75 // Whenever any fields in this Dword are set then PLIC will defer the
76 // processing of external interrupts. Note that PLIC will store the
77 // XIRR directly into the xXirrValue field so that another XIRR will
78 // not be presented until this one clears. The layout of the low
79 // 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
80 // entire Dword is zero or not. A non-zero value in the low order
81 // 2-bytes will result in SLIC being granted the highest thread
82 // priority upon return. A 0 will return to SLIC as medium priority.
83 u64 plic_defer_ints_area; // Entire Dword
84
85 // Used to pass the real SRR0/1 from PLIC to SLIC as well as to
86 // pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
87 u64 saved_srr0; // Saved SRR0 x10-x17
88 u64 saved_srr1; // Saved SRR1 x18-x1F
89
90 // Used to pass parms from the OS to PLIC for SetAsrAndRfid
91 u64 saved_gpr3; // Saved GPR3 x20-x27
92 u64 saved_gpr4; // Saved GPR4 x28-x2F
93 u64 saved_gpr5; // Saved GPR5 x30-x37
94
95 u8 reserved4; // Reserved x38-x38
96 u8 cpuctls_task_attrs; // Task attributes for cpuctls x39-x39
97 u8 fpregs_in_use; // FP regs in use x3A-x3A
98 u8 pmcregs_in_use; // PMC regs in use x3B-x3B
99 volatile u32 saved_decr; // Saved Decr Value x3C-x3F
100 volatile u64 emulated_time_base;// Emulated TB for this thread x40-x47
101 volatile u64 cur_plic_latency; // Unaccounted PLIC latency x48-x4F
102 u64 tot_plic_latency; // Accumulated PLIC latency x50-x57
103 u64 wait_state_cycles; // Wait cycles for this proc x58-x5F
104 u64 end_of_quantum; // TB at end of quantum x60-x67
105 u64 pdc_saved_sprg1; // Saved SPRG1 for PMC int x68-x6F
106 u64 pdc_saved_srr0; // Saved SRR0 for PMC int x70-x77
107 volatile u32 virtual_decr; // Virtual DECR for shared procsx78-x7B
108 u16 slb_count; // # of SLBs to maintain x7C-x7D
109 u8 idle; // Indicate OS is idle x7E
110 u8 vmxregs_in_use; // VMX registers in use x7F
111
112
113//=============================================================================
114// CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
115//=============================================================================
116 // This is the yield_count. An "odd" value (low bit on) means that
117 // the processor is yielded (either because of an OS yield or a PLIC
118 // preempt). An even value implies that the processor is currently
119 // executing.
120 // NOTE: This value will ALWAYS be zero for dedicated processors and
121 // will NEVER be zero for shared processors (ie, initialized to a 1).
122 volatile u32 yield_count; // PLIC increments each dispatchx00-x03
123 u8 reserved6[124]; // Reserved x04-x7F
124
125//=============================================================================
126// CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
127//=============================================================================
128 u8 pmc_save_area[256]; // PMC interrupt Area x00-xFF
129};
130
131#endif /* _ASM_POWERPC_LPPACA_H */
diff --git a/include/asm-powerpc/paca.h b/include/asm-powerpc/paca.h
new file mode 100644
index 000000000000..92c765c35bd0
--- /dev/null
+++ b/include/asm-powerpc/paca.h
@@ -0,0 +1,120 @@
1/*
2 * include/asm-powerpc/paca.h
3 *
4 * This control block defines the PACA which defines the processor
5 * specific data for each logical processor on the system.
6 * There are some pointers defined that are utilized by PLIC.
7 *
8 * C 2001 PPC 64 Team, IBM Corp
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 */
15#ifndef _ASM_POWERPC_PACA_H
16#define _ASM_POWERPC_PACA_H
17
18#include <linux/config.h>
19#include <asm/types.h>
20#include <asm/lppaca.h>
21#include <asm/iseries/it_lp_reg_save.h>
22#include <asm/mmu.h>
23
24register struct paca_struct *local_paca asm("r13");
25#define get_paca() local_paca
26
27struct task_struct;
28
29/*
30 * Defines the layout of the paca.
31 *
32 * This structure is not directly accessed by firmware or the service
33 * processor except for the first two pointers that point to the
34 * lppaca area and the ItLpRegSave area for this CPU. Both the
35 * lppaca and ItLpRegSave objects are currently contained within the
36 * PACA but they do not need to be.
37 */
38struct paca_struct {
39 /*
40 * Because hw_cpu_id, unlike other paca fields, is accessed
41 * routinely from other CPUs (from the IRQ code), we stick to
42 * read-only (after boot) fields in the first cacheline to
43 * avoid cacheline bouncing.
44 */
45
46 /*
47 * MAGIC: These first two pointers can't be moved - they're
48 * accessed by the firmware
49 */
50 struct lppaca *lppaca_ptr; /* Pointer to LpPaca for PLIC */
51 struct ItLpRegSave *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
52
53 /*
54 * MAGIC: the spinlock functions in arch/ppc64/lib/locks.c
55 * load lock_token and paca_index with a single lwz
56 * instruction. They must travel together and be properly
57 * aligned.
58 */
59 u16 lock_token; /* Constant 0x8000, used in locks */
60 u16 paca_index; /* Logical processor number */
61
62 u32 default_decr; /* Default decrementer value */
63 u64 kernel_toc; /* Kernel TOC address */
64 u64 stab_real; /* Absolute address of segment table */
65 u64 stab_addr; /* Virtual address of segment table */
66 void *emergency_sp; /* pointer to emergency stack */
67 s16 hw_cpu_id; /* Physical processor number */
68 u8 cpu_start; /* At startup, processor spins until */
69 /* this becomes non-zero. */
70
71 /*
72 * Now, starting in cacheline 2, the exception save areas
73 */
74 /* used for most interrupts/exceptions */
75 u64 exgen[10] __attribute__((aligned(0x80)));
76 u64 exmc[10]; /* used for machine checks */
77 u64 exslb[10]; /* used for SLB/segment table misses
78 * on the linear mapping */
79#ifdef CONFIG_PPC_64K_PAGES
80 pgd_t *pgdir;
81#endif /* CONFIG_PPC_64K_PAGES */
82
83 mm_context_t context;
84 u16 slb_cache[SLB_CACHE_ENTRIES];
85 u16 slb_cache_ptr;
86
87 /*
88 * then miscellaneous read-write fields
89 */
90 struct task_struct *__current; /* Pointer to current */
91 u64 kstack; /* Saved Kernel stack addr */
92 u64 stab_rr; /* stab/slb round-robin counter */
93 u64 next_jiffy_update_tb; /* TB value for next jiffy update */
94 u64 saved_r1; /* r1 save for RTAS calls */
95 u64 saved_msr; /* MSR saved here by enter_rtas */
96 u8 proc_enabled; /* irq soft-enable flag */
97
98 /* not yet used */
99 u64 exdsi[8]; /* used for linear mapping hash table misses */
100
101 /*
102 * iSeries structure which the hypervisor knows about -
103 * this structure should not cross a page boundary.
104 * The vpa_init/register_vpa call is now known to fail if the
105 * lppaca structure crosses a page boundary.
106 * The lppaca is also used on POWER5 pSeries boxes.
107 * The lppaca is 640 bytes long, and cannot readily change
108 * since the hypervisor knows its layout, so a 1kB
109 * alignment will suffice to ensure that it doesn't
110 * cross a page boundary.
111 */
112 struct lppaca lppaca __attribute__((__aligned__(0x400)));
113#ifdef CONFIG_PPC_ISERIES
114 struct ItLpRegSave reg_save;
115#endif
116};
117
118extern struct paca_struct paca[];
119
120#endif /* _ASM_POWERPC_PACA_H */
diff --git a/include/asm-powerpc/ppc-pci.h b/include/asm-powerpc/ppc-pci.h
index 13aacff755f3..9896fade98a7 100644
--- a/include/asm-powerpc/ppc-pci.h
+++ b/include/asm-powerpc/ppc-pci.h
@@ -26,6 +26,10 @@ extern unsigned long find_and_init_phbs(void);
26 26
27extern struct pci_dev *ppc64_isabridge_dev; /* may be NULL if no ISA bus */ 27extern struct pci_dev *ppc64_isabridge_dev; /* may be NULL if no ISA bus */
28 28
29/** Bus Unit ID macros; get low and hi 32-bits of the 64-bit BUID */
30#define BUID_HI(buid) ((buid) >> 32)
31#define BUID_LO(buid) ((buid) & 0xffffffff)
32
29/* PCI device_node operations */ 33/* PCI device_node operations */
30struct device_node; 34struct device_node;
31typedef void *(*traverse_func)(struct device_node *me, void *data); 35typedef void *(*traverse_func)(struct device_node *me, void *data);
@@ -36,10 +40,6 @@ void pci_devs_phb_init(void);
36void pci_devs_phb_init_dynamic(struct pci_controller *phb); 40void pci_devs_phb_init_dynamic(struct pci_controller *phb);
37void __devinit scan_phb(struct pci_controller *hose); 41void __devinit scan_phb(struct pci_controller *hose);
38 42
39/* PCI address cache management routines */
40void pci_addr_cache_insert_device(struct pci_dev *dev);
41void pci_addr_cache_remove_device(struct pci_dev *dev);
42
43/* From rtas_pci.h */ 43/* From rtas_pci.h */
44void init_pci_config_tokens (void); 44void init_pci_config_tokens (void);
45unsigned long get_phb_buid (struct device_node *); 45unsigned long get_phb_buid (struct device_node *);
@@ -52,4 +52,48 @@ extern unsigned long pci_probe_only;
52extern unsigned long pci_assign_all_buses; 52extern unsigned long pci_assign_all_buses;
53extern int pci_read_irq_line(struct pci_dev *pci_dev); 53extern int pci_read_irq_line(struct pci_dev *pci_dev);
54 54
55/* ---- EEH internal-use-only related routines ---- */
56#ifdef CONFIG_EEH
57/**
58 * rtas_set_slot_reset -- unfreeze a frozen slot
59 *
60 * Clear the EEH-frozen condition on a slot. This routine
61 * does this by asserting the PCI #RST line for 1/8th of
62 * a second; this routine will sleep while the adapter is
63 * being reset.
64 */
65void rtas_set_slot_reset (struct pci_dn *);
66
67/**
68 * eeh_restore_bars - Restore device configuration info.
69 *
70 * A reset of a PCI device will clear out its config space.
71 * This routines will restore the config space for this
72 * device, and is children, to values previously obtained
73 * from the firmware.
74 */
75void eeh_restore_bars(struct pci_dn *);
76
77/**
78 * rtas_configure_bridge -- firmware initialization of pci bridge
79 *
80 * Ask the firmware to configure all PCI bridges devices
81 * located behind the indicated node. Required after a
82 * pci device reset. Does essentially the same hing as
83 * eeh_restore_bars, but for brdges, and lets firmware
84 * do the work.
85 */
86void rtas_configure_bridge(struct pci_dn *);
87
88int rtas_write_config(struct pci_dn *, int where, int size, u32 val);
89
90/**
91 * mark and clear slots: find "partition endpoint" PE and set or
92 * clear the flags for each subnode of the PE.
93 */
94void eeh_mark_slot (struct device_node *dn, int mode_flag);
95void eeh_clear_slot (struct device_node *dn, int mode_flag);
96
97#endif
98
55#endif /* _ASM_POWERPC_PPC_PCI_H */ 99#endif /* _ASM_POWERPC_PPC_PCI_H */
diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
index c534ca41224b..c27baa0563fe 100644
--- a/include/asm-powerpc/ppc_asm.h
+++ b/include/asm-powerpc/ppc_asm.h
@@ -6,8 +6,13 @@
6 6
7#include <linux/stringify.h> 7#include <linux/stringify.h>
8#include <linux/config.h> 8#include <linux/config.h>
9#include <asm/asm-compat.h>
9 10
10#ifdef __ASSEMBLY__ 11#ifndef __ASSEMBLY__
12#error __FILE__ should only be used in assembler files
13#else
14
15#define SZL (BITS_PER_LONG/8)
11 16
12/* 17/*
13 * Macros for storing registers into and loading registers from 18 * Macros for storing registers into and loading registers from
@@ -184,12 +189,6 @@ n:
184 oris reg,reg,(label)@h; \ 189 oris reg,reg,(label)@h; \
185 ori reg,reg,(label)@l; 190 ori reg,reg,(label)@l;
186 191
187/* operations for longs and pointers */
188#define LDL ld
189#define STL std
190#define CMPI cmpdi
191#define SZL 8
192
193/* offsets for stack frame layout */ 192/* offsets for stack frame layout */
194#define LRSAVE 16 193#define LRSAVE 16
195 194
@@ -203,12 +202,6 @@ n:
203 202
204#define OFF(name) name@l 203#define OFF(name) name@l
205 204
206/* operations for longs and pointers */
207#define LDL lwz
208#define STL stw
209#define CMPI cmpwi
210#define SZL 4
211
212/* offsets for stack frame layout */ 205/* offsets for stack frame layout */
213#define LRSAVE 4 206#define LRSAVE 4
214 207
@@ -266,15 +259,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
266#endif 259#endif
267 260
268 261
269#ifdef CONFIG_IBM405_ERR77
270#define PPC405_ERR77(ra,rb) dcbt ra, rb;
271#define PPC405_ERR77_SYNC sync;
272#else
273#define PPC405_ERR77(ra,rb)
274#define PPC405_ERR77_SYNC
275#endif
276
277
278#ifdef CONFIG_IBM440EP_ERR42 262#ifdef CONFIG_IBM440EP_ERR42
279#define PPC440EP_ERR42 isync 263#define PPC440EP_ERR42 isync
280#else 264#else
@@ -502,17 +486,6 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601)
502#define N_SLINE 68 486#define N_SLINE 68
503#define N_SO 100 487#define N_SO 100
504 488
505#define ASM_CONST(x) x
506#else
507 #define __ASM_CONST(x) x##UL
508 #define ASM_CONST(x) __ASM_CONST(x)
509
510#ifdef CONFIG_PPC64
511#define DATAL ".llong"
512#else
513#define DATAL ".long"
514#endif
515
516#endif /* __ASSEMBLY__ */ 489#endif /* __ASSEMBLY__ */
517 490
518#endif /* _ASM_POWERPC_PPC_ASM_H */ 491#endif /* _ASM_POWERPC_PPC_ASM_H */
diff --git a/include/asm-powerpc/processor.h b/include/asm-powerpc/processor.h
index 1dc4bf7b52b3..f6f186b56b0f 100644
--- a/include/asm-powerpc/processor.h
+++ b/include/asm-powerpc/processor.h
@@ -17,65 +17,71 @@
17#include <linux/compiler.h> 17#include <linux/compiler.h>
18#include <asm/ptrace.h> 18#include <asm/ptrace.h>
19#include <asm/types.h> 19#include <asm/types.h>
20#ifdef CONFIG_PPC64
21#include <asm/systemcfg.h>
22#endif
23 20
24#ifdef CONFIG_PPC32 21/* We do _not_ want to define new machine types at all, those must die
25/* 32-bit platform types */ 22 * in favor of using the device-tree
26/* We only need to define a new _MACH_xxx for machines which are part of 23 * -- BenH.
27 * a configuration which supports more than one type of different machine.
28 * This is currently limited to CONFIG_PPC_MULTIPLATFORM and CHRP/PReP/PMac.
29 * -- Tom
30 */ 24 */
31#define _MACH_prep 0x00000001
32#define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */
33#define _MACH_chrp 0x00000004 /* chrp machine */
34 25
35/* see residual.h for these */ 26/* Platforms codes (to be obsoleted) */
27#define PLATFORM_PSERIES 0x0100
28#define PLATFORM_PSERIES_LPAR 0x0101
29#define PLATFORM_ISERIES_LPAR 0x0201
30#define PLATFORM_LPAR 0x0001
31#define PLATFORM_POWERMAC 0x0400
32#define PLATFORM_MAPLE 0x0500
33#define PLATFORM_PREP 0x0600
34#define PLATFORM_CHRP 0x0700
35#define PLATFORM_CELL 0x1000
36
37/* Compat platform codes for 32 bits */
38#define _MACH_prep PLATFORM_PREP
39#define _MACH_Pmac PLATFORM_POWERMAC
40#define _MACH_chrp PLATFORM_CHRP
41
42/* PREP sub-platform types see residual.h for these */
36#define _PREP_Motorola 0x01 /* motorola prep */ 43#define _PREP_Motorola 0x01 /* motorola prep */
37#define _PREP_Firm 0x02 /* firmworks prep */ 44#define _PREP_Firm 0x02 /* firmworks prep */
38#define _PREP_IBM 0x00 /* ibm prep */ 45#define _PREP_IBM 0x00 /* ibm prep */
39#define _PREP_Bull 0x03 /* bull prep */ 46#define _PREP_Bull 0x03 /* bull prep */
40 47
41/* these are arbitrary */ 48/* CHRP sub-platform types. These are arbitrary */
42#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */ 49#define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
43#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ 50#define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
44#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */ 51#define _CHRP_Pegasos 0x06 /* Genesi/bplan's Pegasos and Pegasos2 */
45 52
46#ifdef CONFIG_PPC_MULTIPLATFORM 53#define platform_is_pseries() (_machine == PLATFORM_PSERIES || \
54 _machine == PLATFORM_PSERIES_LPAR)
55#define platform_is_lpar() (!!(_machine & PLATFORM_LPAR))
56
57#if defined(CONFIG_PPC_MULTIPLATFORM)
47extern int _machine; 58extern int _machine;
48 59
60#ifdef CONFIG_PPC32
61
49/* what kind of prep workstation we are */ 62/* what kind of prep workstation we are */
50extern int _prep_type; 63extern int _prep_type;
51extern int _chrp_type; 64extern int _chrp_type;
52 65
53/* 66/*
54 * This is used to identify the board type from a given PReP board 67 * This is used to identify the board type from a given PReP board
55 * vendor. Board revision is also made available. 68 * vendor. Board revision is also made available. This will be moved
69 * elsewhere soon
56 */ 70 */
57extern unsigned char ucSystemType; 71extern unsigned char ucSystemType;
58extern unsigned char ucBoardRev; 72extern unsigned char ucBoardRev;
59extern unsigned char ucBoardRevMaj, ucBoardRevMin; 73extern unsigned char ucBoardRevMaj, ucBoardRevMin;
74
75#endif /* CONFIG_PPC32 */
76
77#elif defined(CONFIG_PPC_ISERIES)
78/*
79 * iSeries is soon to become MULTIPLATFORM hopefully ...
80 */
81#define _machine PLATFORM_ISERIES_LPAR
60#else 82#else
61#define _machine 0 83#define _machine 0
62#endif /* CONFIG_PPC_MULTIPLATFORM */ 84#endif /* CONFIG_PPC_MULTIPLATFORM */
63#endif /* CONFIG_PPC32 */
64
65#ifdef CONFIG_PPC64
66/* Platforms supported by PPC64 */
67#define PLATFORM_PSERIES 0x0100
68#define PLATFORM_PSERIES_LPAR 0x0101
69#define PLATFORM_ISERIES_LPAR 0x0201
70#define PLATFORM_LPAR 0x0001
71#define PLATFORM_POWERMAC 0x0400
72#define PLATFORM_MAPLE 0x0500
73#define PLATFORM_CELL 0x1000
74
75/* Compatibility with drivers coming from PPC32 world */
76#define _machine (systemcfg->platform)
77#define _MACH_Pmac PLATFORM_POWERMAC
78#endif
79 85
80/* 86/*
81 * Default implementation of macro that returns current 87 * Default implementation of macro that returns current
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index 489cf4c99c21..eb392d038ed7 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -16,7 +16,11 @@
16/* Pickup Book E specific registers. */ 16/* Pickup Book E specific registers. */
17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x) 17#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
18#include <asm/reg_booke.h> 18#include <asm/reg_booke.h>
19#endif 19#endif /* CONFIG_BOOKE || CONFIG_40x */
20
21#ifdef CONFIG_8xx
22#include <asm/reg_8xx.h>
23#endif /* CONFIG_8xx */
20 24
21#define MSR_SF_LG 63 /* Enable 64 bit mode */ 25#define MSR_SF_LG 63 /* Enable 64 bit mode */
22#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */ 26#define MSR_ISF_LG 61 /* Interrupt 64b mode valid on 630 */
@@ -359,6 +363,7 @@
359#define SPRN_RPA 0x3D6 /* Required Physical Address Register */ 363#define SPRN_RPA 0x3D6 /* Required Physical Address Register */
360#define SPRN_SDA 0x3BF /* Sampled Data Address Register */ 364#define SPRN_SDA 0x3BF /* Sampled Data Address Register */
361#define SPRN_SDR1 0x019 /* MMU Hash Base Register */ 365#define SPRN_SDR1 0x019 /* MMU Hash Base Register */
366#define SPRN_ASR 0x118 /* Address Space Register */
362#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */ 367#define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
363#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */ 368#define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
364#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ 369#define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
diff --git a/include/asm-powerpc/reg_8xx.h b/include/asm-powerpc/reg_8xx.h
new file mode 100644
index 000000000000..e8ea346b21d3
--- /dev/null
+++ b/include/asm-powerpc/reg_8xx.h
@@ -0,0 +1,42 @@
1/*
2 * Contains register definitions common to PowerPC 8xx CPUs. Notice
3 */
4#ifndef _ASM_POWERPC_REG_8xx_H
5#define _ASM_POWERPC_REG_8xx_H
6
7/* Cache control on the MPC8xx is provided through some additional
8 * special purpose registers.
9 */
10#define SPRN_IC_CST 560 /* Instruction cache control/status */
11#define SPRN_IC_ADR 561 /* Address needed for some commands */
12#define SPRN_IC_DAT 562 /* Read-only data register */
13#define SPRN_DC_CST 568 /* Data cache control/status */
14#define SPRN_DC_ADR 569 /* Address needed for some commands */
15#define SPRN_DC_DAT 570 /* Read-only data register */
16
17/* Commands. Only the first few are available to the instruction cache.
18*/
19#define IDC_ENABLE 0x02000000 /* Cache enable */
20#define IDC_DISABLE 0x04000000 /* Cache disable */
21#define IDC_LDLCK 0x06000000 /* Load and lock */
22#define IDC_UNLINE 0x08000000 /* Unlock line */
23#define IDC_UNALL 0x0a000000 /* Unlock all */
24#define IDC_INVALL 0x0c000000 /* Invalidate all */
25
26#define DC_FLINE 0x0e000000 /* Flush data cache line */
27#define DC_SFWT 0x01000000 /* Set forced writethrough mode */
28#define DC_CFWT 0x03000000 /* Clear forced writethrough mode */
29#define DC_SLES 0x05000000 /* Set little endian swap mode */
30#define DC_CLES 0x07000000 /* Clear little endian swap mode */
31
32/* Status.
33*/
34#define IDC_ENABLED 0x80000000 /* Cache is enabled */
35#define IDC_CERR1 0x00200000 /* Cache error 1 */
36#define IDC_CERR2 0x00100000 /* Cache error 2 */
37#define IDC_CERR3 0x00080000 /* Cache error 3 */
38
39#define DC_DFWT 0x40000000 /* Data cache is forced write through */
40#define DC_LES 0x20000000 /* Caches are little endian mode */
41
42#endif /* _ASM_POWERPC_REG_8xx_H */
diff --git a/include/asm-powerpc/signal.h b/include/asm-powerpc/signal.h
new file mode 100644
index 000000000000..694c8d2dab87
--- /dev/null
+++ b/include/asm-powerpc/signal.h
@@ -0,0 +1,150 @@
1#ifndef _ASM_POWERPC_SIGNAL_H
2#define _ASM_POWERPC_SIGNAL_H
3
4#include <linux/types.h>
5#include <linux/config.h>
6
7#define _NSIG 64
8#define _NSIG_BPW BITS_PER_LONG
9#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
10
11typedef unsigned long old_sigset_t; /* at least 32 bits */
12
13typedef struct {
14 unsigned long sig[_NSIG_WORDS];
15} sigset_t;
16
17#define SIGHUP 1
18#define SIGINT 2
19#define SIGQUIT 3
20#define SIGILL 4
21#define SIGTRAP 5
22#define SIGABRT 6
23#define SIGIOT 6
24#define SIGBUS 7
25#define SIGFPE 8
26#define SIGKILL 9
27#define SIGUSR1 10
28#define SIGSEGV 11
29#define SIGUSR2 12
30#define SIGPIPE 13
31#define SIGALRM 14
32#define SIGTERM 15
33#define SIGSTKFLT 16
34#define SIGCHLD 17
35#define SIGCONT 18
36#define SIGSTOP 19
37#define SIGTSTP 20
38#define SIGTTIN 21
39#define SIGTTOU 22
40#define SIGURG 23
41#define SIGXCPU 24
42#define SIGXFSZ 25
43#define SIGVTALRM 26
44#define SIGPROF 27
45#define SIGWINCH 28
46#define SIGIO 29
47#define SIGPOLL SIGIO
48/*
49#define SIGLOST 29
50*/
51#define SIGPWR 30
52#define SIGSYS 31
53#define SIGUNUSED 31
54
55/* These should not be considered constants from userland. */
56#define SIGRTMIN 32
57#define SIGRTMAX _NSIG
58
59/*
60 * SA_FLAGS values:
61 *
62 * SA_ONSTACK is not currently supported, but will allow sigaltstack(2).
63 * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
64 * SA_RESTART flag to get restarting signals (which were the default long ago)
65 * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
66 * SA_RESETHAND clears the handler when the signal is delivered.
67 * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
68 * SA_NODEFER prevents the current signal from being masked in the handler.
69 *
70 * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
71 * Unix names RESETHAND and NODEFER respectively.
72 */
73#define SA_NOCLDSTOP 0x00000001U
74#define SA_NOCLDWAIT 0x00000002U
75#define SA_SIGINFO 0x00000004U
76#define SA_ONSTACK 0x08000000U
77#define SA_RESTART 0x10000000U
78#define SA_NODEFER 0x40000000U
79#define SA_RESETHAND 0x80000000U
80
81#define SA_NOMASK SA_NODEFER
82#define SA_ONESHOT SA_RESETHAND
83#define SA_INTERRUPT 0x20000000u /* dummy -- ignored */
84
85#define SA_RESTORER 0x04000000U
86
87/*
88 * sigaltstack controls
89 */
90#define SS_ONSTACK 1
91#define SS_DISABLE 2
92
93#define MINSIGSTKSZ 2048
94#define SIGSTKSZ 8192
95
96#include <asm-generic/signal.h>
97
98struct old_sigaction {
99 __sighandler_t sa_handler;
100 old_sigset_t sa_mask;
101 unsigned long sa_flags;
102 __sigrestore_t sa_restorer;
103};
104
105struct sigaction {
106 __sighandler_t sa_handler;
107 unsigned long sa_flags;
108 __sigrestore_t sa_restorer;
109 sigset_t sa_mask; /* mask last for extensibility */
110};
111
112struct k_sigaction {
113 struct sigaction sa;
114};
115
116typedef struct sigaltstack {
117 void __user *ss_sp;
118 int ss_flags;
119 size_t ss_size;
120} stack_t;
121
122#ifdef __KERNEL__
123struct pt_regs;
124extern int do_signal(sigset_t *oldset, struct pt_regs *regs);
125extern int do_signal32(sigset_t *oldset, struct pt_regs *regs);
126#define ptrace_signal_deliver(regs, cookie) do { } while (0)
127#endif /* __KERNEL__ */
128
129#ifndef __powerpc64__
130/*
131 * These are parameters to dbg_sigreturn syscall. They enable or
132 * disable certain debugging things that can be done from signal
133 * handlers. The dbg_sigreturn syscall *must* be called from a
134 * SA_SIGINFO signal so the ucontext can be passed to it. It takes an
135 * array of struct sig_dbg_op, which has the debug operations to
136 * perform before returning from the signal.
137 */
138struct sig_dbg_op {
139 int dbg_type;
140 unsigned long dbg_value;
141};
142
143/* Enable or disable single-stepping. The value sets the state. */
144#define SIG_DBG_SINGLE_STEPPING 1
145
146/* Enable or disable branch tracing. The value sets the state. */
147#define SIG_DBG_BRANCH_TRACING 2
148#endif /* ! __powerpc64__ */
149
150#endif /* _ASM_POWERPC_SIGNAL_H */
diff --git a/include/asm-powerpc/sparsemem.h b/include/asm-powerpc/sparsemem.h
index 1c95ab99deb3..58d2aab416f8 100644
--- a/include/asm-powerpc/sparsemem.h
+++ b/include/asm-powerpc/sparsemem.h
@@ -11,6 +11,10 @@
11#define MAX_PHYSADDR_BITS 38 11#define MAX_PHYSADDR_BITS 38
12#define MAX_PHYSMEM_BITS 36 12#define MAX_PHYSMEM_BITS 36
13 13
14#ifdef CONFIG_MEMORY_HOTPLUG
15extern void create_section_mapping(unsigned long start, unsigned long end);
16#endif /* CONFIG_MEMORY_HOTPLUG */
17
14#endif /* CONFIG_SPARSEMEM */ 18#endif /* CONFIG_SPARSEMEM */
15 19
16#endif /* _ASM_POWERPC_SPARSEMEM_H */ 20#endif /* _ASM_POWERPC_SPARSEMEM_H */
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index 3536a5cd7a2d..5341b75c75cb 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -8,7 +8,6 @@
8#include <linux/kernel.h> 8#include <linux/kernel.h>
9 9
10#include <asm/hw_irq.h> 10#include <asm/hw_irq.h>
11#include <asm/ppc_asm.h>
12#include <asm/atomic.h> 11#include <asm/atomic.h>
13 12
14/* 13/*
@@ -180,6 +179,7 @@ extern struct task_struct *_switch(struct thread_struct *prev,
180extern unsigned int rtas_data; 179extern unsigned int rtas_data;
181extern int mem_init_done; /* set on boot once kmalloc can be called */ 180extern int mem_init_done; /* set on boot once kmalloc can be called */
182extern unsigned long memory_limit; 181extern unsigned long memory_limit;
182extern unsigned long klimit;
183 183
184extern int powersave_nap; /* set if nap mode can be used in idle loop */ 184extern int powersave_nap; /* set if nap mode can be used in idle loop */
185 185
diff --git a/include/asm-powerpc/systemcfg.h b/include/asm-powerpc/systemcfg.h
new file mode 100644
index 000000000000..36b5cbe466f1
--- /dev/null
+++ b/include/asm-powerpc/systemcfg.h
@@ -0,0 +1,64 @@
1#ifndef _SYSTEMCFG_H
2#define _SYSTEMCFG_H
3
4/*
5 * Copyright (C) 2002 Peter Bergner <bergner@vnet.ibm.com>, IBM
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
11 */
12
13/* Change Activity:
14 * 2002/09/30 : bergner : Created
15 * End Change Activity
16 */
17
18/*
19 * If the major version changes we are incompatible.
20 * Minor version changes are a hint.
21 */
22#define SYSTEMCFG_MAJOR 1
23#define SYSTEMCFG_MINOR 1
24
25#ifndef __ASSEMBLY__
26
27#include <linux/unistd.h>
28
29#define SYSCALL_MAP_SIZE ((__NR_syscalls + 31) / 32)
30
31struct systemcfg {
32 __u8 eye_catcher[16]; /* Eyecatcher: SYSTEMCFG:PPC64 0x00 */
33 struct { /* Systemcfg version numbers */
34 __u32 major; /* Major number 0x10 */
35 __u32 minor; /* Minor number 0x14 */
36 } version;
37
38 __u32 platform; /* Platform flags 0x18 */
39 __u32 processor; /* Processor type 0x1C */
40 __u64 processorCount; /* # of physical processors 0x20 */
41 __u64 physicalMemorySize; /* Size of real memory(B) 0x28 */
42 __u64 tb_orig_stamp; /* Timebase at boot 0x30 */
43 __u64 tb_ticks_per_sec; /* Timebase tics / sec 0x38 */
44 __u64 tb_to_xs; /* Inverse of TB to 2^20 0x40 */
45 __u64 stamp_xsec; /* 0x48 */
46 __u64 tb_update_count; /* Timebase atomicity ctr 0x50 */
47 __u32 tz_minuteswest; /* Minutes west of Greenwich 0x58 */
48 __u32 tz_dsttime; /* Type of dst correction 0x5C */
49 /* next four are no longer used except to be exported to /proc */
50 __u32 dcache_size; /* L1 d-cache size 0x60 */
51 __u32 dcache_line_size; /* L1 d-cache line size 0x64 */
52 __u32 icache_size; /* L1 i-cache size 0x68 */
53 __u32 icache_line_size; /* L1 i-cache line size 0x6C */
54 __u32 syscall_map_64[SYSCALL_MAP_SIZE]; /* map of available syscalls 0x70 */
55 __u32 syscall_map_32[SYSCALL_MAP_SIZE]; /* map of available syscalls */
56};
57
58#ifdef __KERNEL__
59extern struct systemcfg *_systemcfg; /* to be renamed */
60#endif
61
62#endif /* __ASSEMBLY__ */
63
64#endif /* _SYSTEMCFG_H */
diff --git a/include/asm-powerpc/tce.h b/include/asm-powerpc/tce.h
new file mode 100644
index 000000000000..d099d5200f9b
--- /dev/null
+++ b/include/asm-powerpc/tce.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
3 * Rewrite, cleanup:
4 * Copyright (C) 2004 Olof Johansson <olof@austin.ibm.com>, IBM Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#ifndef _ASM_POWERPC_TCE_H
22#define _ASM_POWERPC_TCE_H
23
24/*
25 * Tces come in two formats, one for the virtual bus and a different
26 * format for PCI
27 */
28#define TCE_VB 0
29#define TCE_PCI 1
30
31/* TCE page size is 4096 bytes (1 << 12) */
32
33#define TCE_SHIFT 12
34#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
35#define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
36
37
38/* tce_entry
39 * Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
40 * abstracted so layout is irrelevant.
41 */
42union tce_entry {
43 unsigned long te_word;
44 struct {
45 unsigned int tb_cacheBits :6; /* Cache hash bits - not used */
46 unsigned int tb_rsvd :6;
47 unsigned long tb_rpn :40; /* Real page number */
48 unsigned int tb_valid :1; /* Tce is valid (vb only) */
49 unsigned int tb_allio :1; /* Tce is valid for all lps (vb only) */
50 unsigned int tb_lpindex :8; /* LpIndex for user of TCE (vb only) */
51 unsigned int tb_pciwr :1; /* Write allowed (pci only) */
52 unsigned int tb_rdwr :1; /* Read allowed (pci), Write allowed (vb) */
53 } te_bits;
54#define te_cacheBits te_bits.tb_cacheBits
55#define te_rpn te_bits.tb_rpn
56#define te_valid te_bits.tb_valid
57#define te_allio te_bits.tb_allio
58#define te_lpindex te_bits.tb_lpindex
59#define te_pciwr te_bits.tb_pciwr
60#define te_rdwr te_bits.tb_rdwr
61};
62
63
64#endif /* _ASM_POWERPC_TCE_H */
diff --git a/include/asm-powerpc/uaccess.h b/include/asm-powerpc/uaccess.h
index 33af730f0d19..3872e924cdd6 100644
--- a/include/asm-powerpc/uaccess.h
+++ b/include/asm-powerpc/uaccess.h
@@ -120,14 +120,6 @@ struct exception_table_entry {
120 120
121extern long __put_user_bad(void); 121extern long __put_user_bad(void);
122 122
123#ifdef __powerpc64__
124#define __EX_TABLE_ALIGN "3"
125#define __EX_TABLE_TYPE "llong"
126#else
127#define __EX_TABLE_ALIGN "2"
128#define __EX_TABLE_TYPE "long"
129#endif
130
131/* 123/*
132 * We don't tell gcc that we are accessing memory, but this is OK 124 * We don't tell gcc that we are accessing memory, but this is OK
133 * because we do not write to any memory gcc knows about, so there 125 * because we do not write to any memory gcc knows about, so there
@@ -142,11 +134,12 @@ extern long __put_user_bad(void);
142 " b 2b\n" \ 134 " b 2b\n" \
143 ".previous\n" \ 135 ".previous\n" \
144 ".section __ex_table,\"a\"\n" \ 136 ".section __ex_table,\"a\"\n" \
145 " .align " __EX_TABLE_ALIGN "\n" \ 137 " .balign %5\n" \
146 " ."__EX_TABLE_TYPE" 1b,3b\n" \ 138 PPC_LONG "1b,3b\n" \
147 ".previous" \ 139 ".previous" \
148 : "=r" (err) \ 140 : "=r" (err) \
149 : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err)) 141 : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err),\
142 "i"(sizeof(unsigned long)))
150 143
151#ifdef __powerpc64__ 144#ifdef __powerpc64__
152#define __put_user_asm2(x, ptr, retval) \ 145#define __put_user_asm2(x, ptr, retval) \
@@ -162,12 +155,13 @@ extern long __put_user_bad(void);
162 " b 3b\n" \ 155 " b 3b\n" \
163 ".previous\n" \ 156 ".previous\n" \
164 ".section __ex_table,\"a\"\n" \ 157 ".section __ex_table,\"a\"\n" \
165 " .align " __EX_TABLE_ALIGN "\n" \ 158 " .balign %5\n" \
166 " ." __EX_TABLE_TYPE " 1b,4b\n" \ 159 PPC_LONG "1b,4b\n" \
167 " ." __EX_TABLE_TYPE " 2b,4b\n" \ 160 PPC_LONG "2b,4b\n" \
168 ".previous" \ 161 ".previous" \
169 : "=r" (err) \ 162 : "=r" (err) \
170 : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err)) 163 : "r" (x), "b" (addr), "i" (-EFAULT), "0" (err),\
164 "i"(sizeof(unsigned long)))
171#endif /* __powerpc64__ */ 165#endif /* __powerpc64__ */
172 166
173#define __put_user_size(x, ptr, size, retval) \ 167#define __put_user_size(x, ptr, size, retval) \
@@ -213,11 +207,12 @@ extern long __get_user_bad(void);
213 " b 2b\n" \ 207 " b 2b\n" \
214 ".previous\n" \ 208 ".previous\n" \
215 ".section __ex_table,\"a\"\n" \ 209 ".section __ex_table,\"a\"\n" \
216 " .align "__EX_TABLE_ALIGN "\n" \ 210 " .balign %5\n" \
217 " ." __EX_TABLE_TYPE " 1b,3b\n" \ 211 PPC_LONG "1b,3b\n" \
218 ".previous" \ 212 ".previous" \
219 : "=r" (err), "=r" (x) \ 213 : "=r" (err), "=r" (x) \
220 : "b" (addr), "i" (-EFAULT), "0" (err)) 214 : "b" (addr), "i" (-EFAULT), "0" (err), \
215 "i"(sizeof(unsigned long)))
221 216
222#ifdef __powerpc64__ 217#ifdef __powerpc64__
223#define __get_user_asm2(x, addr, err) \ 218#define __get_user_asm2(x, addr, err) \
@@ -235,12 +230,13 @@ extern long __get_user_bad(void);
235 " b 3b\n" \ 230 " b 3b\n" \
236 ".previous\n" \ 231 ".previous\n" \
237 ".section __ex_table,\"a\"\n" \ 232 ".section __ex_table,\"a\"\n" \
238 " .align " __EX_TABLE_ALIGN "\n" \ 233 " .balign %5\n" \
239 " ." __EX_TABLE_TYPE " 1b,4b\n" \ 234 PPC_LONG "1b,4b\n" \
240 " ." __EX_TABLE_TYPE " 2b,4b\n" \ 235 PPC_LONG "2b,4b\n" \
241 ".previous" \ 236 ".previous" \
242 : "=r" (err), "=&r" (x) \ 237 : "=r" (err), "=&r" (x) \
243 : "b" (addr), "i" (-EFAULT), "0" (err)) 238 : "b" (addr), "i" (-EFAULT), "0" (err), \
239 "i"(sizeof(unsigned long)))
244#endif /* __powerpc64__ */ 240#endif /* __powerpc64__ */
245 241
246#define __get_user_size(x, ptr, size, retval) \ 242#define __get_user_size(x, ptr, size, retval) \
diff --git a/include/asm-powerpc/xmon.h b/include/asm-powerpc/xmon.h
index ace2072d4a83..43f7129984c7 100644
--- a/include/asm-powerpc/xmon.h
+++ b/include/asm-powerpc/xmon.h
@@ -7,7 +7,6 @@ struct pt_regs;
7extern int xmon(struct pt_regs *excp); 7extern int xmon(struct pt_regs *excp);
8extern void xmon_printf(const char *fmt, ...); 8extern void xmon_printf(const char *fmt, ...);
9extern void xmon_init(int); 9extern void xmon_init(int);
10extern void xmon_map_scc(void);
11 10
12#endif 11#endif
13#endif 12#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-21 03:16:41 -0500