aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-powerpc/spu_csa.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-powerpc/spu_csa.h')
-rw-r--r--include/asm-powerpc/spu_csa.h255
1 files changed, 255 insertions, 0 deletions
diff --git a/include/asm-powerpc/spu_csa.h b/include/asm-powerpc/spu_csa.h
new file mode 100644
index 000000000000..ba18d7d4dde2
--- /dev/null
+++ b/include/asm-powerpc/spu_csa.h
@@ -0,0 +1,255 @@
1/*
2 * spu_csa.h: Definitions for SPU context save area (CSA).
3 *
4 * (C) Copyright IBM 2005
5 *
6 * Author: Mark Nutter <mnutter@us.ibm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
11 * any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 */
22
23#ifndef _SPU_CSA_H_
24#define _SPU_CSA_H_
25#ifdef __KERNEL__
26
27/*
28 * Total number of 128-bit registers.
29 */
30#define NR_SPU_GPRS 128
31#define NR_SPU_SPRS 9
32#define NR_SPU_REGS_PAD 7
33#define NR_SPU_SPILL_REGS 144 /* GPRS + SPRS + PAD */
34#define SIZEOF_SPU_SPILL_REGS NR_SPU_SPILL_REGS * 16
35
36#define SPU_SAVE_COMPLETE 0x3FFB
37#define SPU_RESTORE_COMPLETE 0x3FFC
38
39/*
40 * Definitions for various 'stopped' status conditions,
41 * to be recreated during context restore.
42 */
43#define SPU_STOPPED_STATUS_P 1
44#define SPU_STOPPED_STATUS_I 2
45#define SPU_STOPPED_STATUS_H 3
46#define SPU_STOPPED_STATUS_S 4
47#define SPU_STOPPED_STATUS_S_I 5
48#define SPU_STOPPED_STATUS_S_P 6
49#define SPU_STOPPED_STATUS_P_H 7
50#define SPU_STOPPED_STATUS_P_I 8
51#define SPU_STOPPED_STATUS_R 9
52
53#ifndef __ASSEMBLY__
54/**
55 * spu_reg128 - generic 128-bit register definition.
56 */
57struct spu_reg128 {
58 u32 slot[4];
59};
60
61/**
62 * struct spu_lscsa - Local Store Context Save Area.
63 * @gprs: Array of saved registers.
64 * @fpcr: Saved floating point status control register.
65 * @decr: Saved decrementer value.
66 * @decr_status: Indicates decrementer run status.
67 * @ppu_mb: Saved PPU mailbox data.
68 * @ppuint_mb: Saved PPU interrupting mailbox data.
69 * @tag_mask: Saved tag group mask.
70 * @event_mask: Saved event mask.
71 * @srr0: Saved SRR0.
72 * @stopped_status: Conditions to be recreated by restore.
73 * @ls: Saved contents of Local Storage Area.
74 *
75 * The LSCSA represents state that is primarily saved and
76 * restored by SPU-side code.
77 */
78struct spu_lscsa {
79 struct spu_reg128 gprs[128];
80 struct spu_reg128 fpcr;
81 struct spu_reg128 decr;
82 struct spu_reg128 decr_status;
83 struct spu_reg128 ppu_mb;
84 struct spu_reg128 ppuint_mb;
85 struct spu_reg128 tag_mask;
86 struct spu_reg128 event_mask;
87 struct spu_reg128 srr0;
88 struct spu_reg128 stopped_status;
89 struct spu_reg128 pad[119]; /* 'ls' must be page-aligned. */
90 unsigned char ls[LS_SIZE];
91};
92
93/*
94 * struct spu_problem_collapsed - condensed problem state area, w/o pads.
95 */
96struct spu_problem_collapsed {
97 u64 spc_mssync_RW;
98 u32 mfc_lsa_W;
99 u32 unused_pad0;
100 u64 mfc_ea_W;
101 union mfc_tag_size_class_cmd mfc_union_W;
102 u32 dma_qstatus_R;
103 u32 dma_querytype_RW;
104 u32 dma_querymask_RW;
105 u32 dma_tagstatus_R;
106 u32 pu_mb_R;
107 u32 spu_mb_W;
108 u32 mb_stat_R;
109 u32 spu_runcntl_RW;
110 u32 spu_status_R;
111 u32 spu_spc_R;
112 u32 spu_npc_RW;
113 u32 signal_notify1;
114 u32 signal_notify2;
115 u32 unused_pad1;
116};
117
118/*
119 * struct spu_priv1_collapsed - condensed privileged 1 area, w/o pads.
120 */
121struct spu_priv1_collapsed {
122 u64 mfc_sr1_RW;
123 u64 mfc_lpid_RW;
124 u64 spu_idr_RW;
125 u64 mfc_vr_RO;
126 u64 spu_vr_RO;
127 u64 int_mask_class0_RW;
128 u64 int_mask_class1_RW;
129 u64 int_mask_class2_RW;
130 u64 int_stat_class0_RW;
131 u64 int_stat_class1_RW;
132 u64 int_stat_class2_RW;
133 u64 int_route_RW;
134 u64 mfc_atomic_flush_RW;
135 u64 resource_allocation_groupID_RW;
136 u64 resource_allocation_enable_RW;
137 u64 mfc_fir_R;
138 u64 mfc_fir_status_or_W;
139 u64 mfc_fir_status_and_W;
140 u64 mfc_fir_mask_R;
141 u64 mfc_fir_mask_or_W;
142 u64 mfc_fir_mask_and_W;
143 u64 mfc_fir_chkstp_enable_RW;
144 u64 smf_sbi_signal_sel;
145 u64 smf_ato_signal_sel;
146 u64 mfc_sdr_RW;
147 u64 tlb_index_hint_RO;
148 u64 tlb_index_W;
149 u64 tlb_vpn_RW;
150 u64 tlb_rpn_RW;
151 u64 tlb_invalidate_entry_W;
152 u64 tlb_invalidate_all_W;
153 u64 smm_hid;
154 u64 mfc_accr_RW;
155 u64 mfc_dsisr_RW;
156 u64 mfc_dar_RW;
157 u64 rmt_index_RW;
158 u64 rmt_data1_RW;
159 u64 mfc_dsir_R;
160 u64 mfc_lsacr_RW;
161 u64 mfc_lscrr_R;
162 u64 mfc_tclass_id_RW;
163 u64 mfc_rm_boundary;
164 u64 smf_dma_signal_sel;
165 u64 smm_signal_sel;
166 u64 mfc_cer_R;
167 u64 pu_ecc_cntl_RW;
168 u64 pu_ecc_stat_RW;
169 u64 spu_ecc_addr_RW;
170 u64 spu_err_mask_RW;
171 u64 spu_trig0_sel;
172 u64 spu_trig1_sel;
173 u64 spu_trig2_sel;
174 u64 spu_trig3_sel;
175 u64 spu_trace_sel;
176 u64 spu_event0_sel;
177 u64 spu_event1_sel;
178 u64 spu_event2_sel;
179 u64 spu_event3_sel;
180 u64 spu_trace_cntl;
181};
182
183/*
184 * struct spu_priv2_collapsed - condensed priviliged 2 area, w/o pads.
185 */
186struct spu_priv2_collapsed {
187 u64 slb_index_W;
188 u64 slb_esid_RW;
189 u64 slb_vsid_RW;
190 u64 slb_invalidate_entry_W;
191 u64 slb_invalidate_all_W;
192 struct mfc_cq_sr spuq[16];
193 struct mfc_cq_sr puq[8];
194 u64 mfc_control_RW;
195 u64 puint_mb_R;
196 u64 spu_privcntl_RW;
197 u64 spu_lslr_RW;
198 u64 spu_chnlcntptr_RW;
199 u64 spu_chnlcnt_RW;
200 u64 spu_chnldata_RW;
201 u64 spu_cfg_RW;
202 u64 spu_tag_status_query_RW;
203 u64 spu_cmd_buf1_RW;
204 u64 spu_cmd_buf2_RW;
205 u64 spu_atomic_status_RW;
206};
207
208/**
209 * struct spu_state
210 * @lscsa: Local Store Context Save Area.
211 * @prob: Collapsed Problem State Area, w/o pads.
212 * @priv1: Collapsed Privileged 1 Area, w/o pads.
213 * @priv2: Collapsed Privileged 2 Area, w/o pads.
214 * @spu_chnlcnt_RW: Array of saved channel counts.
215 * @spu_chnldata_RW: Array of saved channel data.
216 * @suspend_time: Time stamp when decrementer disabled.
217 * @slb_esid_RW: Array of saved SLB esid entries.
218 * @slb_vsid_RW: Array of saved SLB vsid entries.
219 *
220 * Structure representing the whole of the SPU
221 * context save area (CSA). This struct contains
222 * all of the state necessary to suspend and then
223 * later optionally resume execution of an SPU
224 * context.
225 *
226 * The @lscsa region is by far the largest, and is
227 * allocated separately so that it may either be
228 * pinned or mapped to/from application memory, as
229 * appropriate for the OS environment.
230 */
231struct spu_state {
232 struct spu_lscsa *lscsa;
233 struct spu_problem_collapsed prob;
234 struct spu_priv1_collapsed priv1;
235 struct spu_priv2_collapsed priv2;
236 u64 spu_chnlcnt_RW[32];
237 u64 spu_chnldata_RW[32];
238 u32 spu_mailbox_data[4];
239 u32 pu_mailbox_data[1];
240 unsigned long suspend_time;
241 u64 slb_esid_RW[8];
242 u64 slb_vsid_RW[8];
243 spinlock_t register_lock;
244};
245
246extern void spu_init_csa(struct spu_state *csa);
247extern void spu_fini_csa(struct spu_state *csa);
248extern int spu_save(struct spu_state *prev, struct spu *spu);
249extern int spu_restore(struct spu_state *new, struct spu *spu);
250extern int spu_switch(struct spu_state *prev, struct spu_state *new,
251 struct spu *spu);
252
253#endif /* __KERNEL__ */
254#endif /* !__ASSEMBLY__ */
255#endif /* _SPU_CSA_H_ */