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-rw-r--r--include/asm-powerpc/spu.h32
1 files changed, 28 insertions, 4 deletions
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index b1accce77bb5..f07c99ba5d13 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -104,6 +104,7 @@
104 104
105struct spu_context; 105struct spu_context;
106struct spu_runqueue; 106struct spu_runqueue;
107struct spu_lscsa;
107struct device_node; 108struct device_node;
108 109
109enum spu_utilization_state { 110enum spu_utilization_state {
@@ -145,7 +146,6 @@ struct spu {
145 void (* ibox_callback)(struct spu *spu); 146 void (* ibox_callback)(struct spu *spu);
146 void (* stop_callback)(struct spu *spu); 147 void (* stop_callback)(struct spu *spu);
147 void (* mfc_callback)(struct spu *spu); 148 void (* mfc_callback)(struct spu *spu);
148 void (* dma_callback)(struct spu *spu, int type);
149 149
150 char irq_c0[8]; 150 char irq_c0[8];
151 char irq_c1[8]; 151 char irq_c1[8];
@@ -196,10 +196,11 @@ struct cbe_spu_info {
196extern struct cbe_spu_info cbe_spu_info[]; 196extern struct cbe_spu_info cbe_spu_info[];
197 197
198void spu_init_channels(struct spu *spu); 198void spu_init_channels(struct spu *spu);
199int spu_irq_class_0_bottom(struct spu *spu);
200int spu_irq_class_1_bottom(struct spu *spu);
201void spu_irq_setaffinity(struct spu *spu, int cpu); 199void spu_irq_setaffinity(struct spu *spu, int cpu);
202 200
201void spu_setup_kernel_slbs(struct spu *spu, struct spu_lscsa *lscsa,
202 void *code, int code_size);
203
203#ifdef CONFIG_KEXEC 204#ifdef CONFIG_KEXEC
204void crash_register_spus(struct list_head *list); 205void crash_register_spus(struct list_head *list);
205#else 206#else
@@ -210,6 +211,7 @@ static inline void crash_register_spus(struct list_head *list)
210 211
211extern void spu_invalidate_slbs(struct spu *spu); 212extern void spu_invalidate_slbs(struct spu *spu);
212extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm); 213extern void spu_associate_mm(struct spu *spu, struct mm_struct *mm);
214int spu_64k_pages_available(void);
213 215
214/* Calls from the memory management to the SPU */ 216/* Calls from the memory management to the SPU */
215struct mm_struct; 217struct mm_struct;
@@ -246,6 +248,7 @@ struct spufs_calls {
246 __u32 __user *ustatus); 248 __u32 __user *ustatus);
247 int (*coredump_extra_notes_size)(void); 249 int (*coredump_extra_notes_size)(void);
248 int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset); 250 int (*coredump_extra_notes_write)(struct file *file, loff_t *foffset);
251 void (*notify_spus_active)(void);
249 struct module *owner; 252 struct module *owner;
250}; 253};
251 254
@@ -278,6 +281,8 @@ void spu_remove_sysdev_attr(struct sysdev_attribute *attr);
278int spu_add_sysdev_attr_group(struct attribute_group *attrs); 281int spu_add_sysdev_attr_group(struct attribute_group *attrs);
279void spu_remove_sysdev_attr_group(struct attribute_group *attrs); 282void spu_remove_sysdev_attr_group(struct attribute_group *attrs);
280 283
284int spu_handle_mm_fault(struct mm_struct *mm, unsigned long ea,
285 unsigned long dsisr, unsigned *flt);
281 286
282/* 287/*
283 * Notifier blocks: 288 * Notifier blocks:
@@ -298,8 +303,11 @@ struct notifier_block;
298int spu_switch_event_register(struct notifier_block * n); 303int spu_switch_event_register(struct notifier_block * n);
299int spu_switch_event_unregister(struct notifier_block * n); 304int spu_switch_event_unregister(struct notifier_block * n);
300 305
306extern void notify_spus_active(void);
307extern void do_notify_spus_active(void);
308
301/* 309/*
302 * This defines the Local Store, Problem Area and Privlege Area of an SPU. 310 * This defines the Local Store, Problem Area and Privilege Area of an SPU.
303 */ 311 */
304 312
305union mfc_tag_size_class_cmd { 313union mfc_tag_size_class_cmd {
@@ -520,8 +528,24 @@ struct spu_priv1 {
520#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L 528#define CLASS2_ENABLE_SPU_STOP_INTR 0x2L
521#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L 529#define CLASS2_ENABLE_SPU_HALT_INTR 0x4L
522#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L 530#define CLASS2_ENABLE_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
531#define CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR 0x10L
523 u8 pad_0x118_0x140[0x28]; /* 0x118 */ 532 u8 pad_0x118_0x140[0x28]; /* 0x118 */
524 u64 int_stat_RW[3]; /* 0x140 */ 533 u64 int_stat_RW[3]; /* 0x140 */
534#define CLASS0_DMA_ALIGNMENT_INTR 0x1L
535#define CLASS0_INVALID_DMA_COMMAND_INTR 0x2L
536#define CLASS0_SPU_ERROR_INTR 0x4L
537#define CLASS0_INTR_MASK 0x7L
538#define CLASS1_SEGMENT_FAULT_INTR 0x1L
539#define CLASS1_STORAGE_FAULT_INTR 0x2L
540#define CLASS1_LS_COMPARE_SUSPEND_ON_GET_INTR 0x4L
541#define CLASS1_LS_COMPARE_SUSPEND_ON_PUT_INTR 0x8L
542#define CLASS1_INTR_MASK 0xfL
543#define CLASS2_MAILBOX_INTR 0x1L
544#define CLASS2_SPU_STOP_INTR 0x2L
545#define CLASS2_SPU_HALT_INTR 0x4L
546#define CLASS2_SPU_DMA_TAG_GROUP_COMPLETE_INTR 0x8L
547#define CLASS2_MAILBOX_THRESHOLD_INTR 0x10L
548#define CLASS2_INTR_MASK 0x1fL
525 u8 pad_0x158_0x180[0x28]; /* 0x158 */ 549 u8 pad_0x158_0x180[0x28]; /* 0x158 */
526 u64 int_route_RW; /* 0x180 */ 550 u64 int_route_RW; /* 0x180 */
527 551