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Diffstat (limited to 'include/asm-powerpc/spu.h')
-rw-r--r--include/asm-powerpc/spu.h11
1 files changed, 10 insertions, 1 deletions
diff --git a/include/asm-powerpc/spu.h b/include/asm-powerpc/spu.h
index 38bacf2f6e0c..f431d8b0b651 100644
--- a/include/asm-powerpc/spu.h
+++ b/include/asm-powerpc/spu.h
@@ -110,6 +110,7 @@ struct spu {
110 char *name; 110 char *name;
111 unsigned long local_store_phys; 111 unsigned long local_store_phys;
112 u8 *local_store; 112 u8 *local_store;
113 unsigned long problem_phys;
113 struct spu_problem __iomem *problem; 114 struct spu_problem __iomem *problem;
114 struct spu_priv1 __iomem *priv1; 115 struct spu_priv1 __iomem *priv1;
115 struct spu_priv2 __iomem *priv2; 116 struct spu_priv2 __iomem *priv2;
@@ -137,6 +138,7 @@ struct spu {
137 void (* wbox_callback)(struct spu *spu); 138 void (* wbox_callback)(struct spu *spu);
138 void (* ibox_callback)(struct spu *spu); 139 void (* ibox_callback)(struct spu *spu);
139 void (* stop_callback)(struct spu *spu); 140 void (* stop_callback)(struct spu *spu);
141 void (* mfc_callback)(struct spu *spu);
140 142
141 char irq_c0[8]; 143 char irq_c0[8];
142 char irq_c1[8]; 144 char irq_c1[8];
@@ -149,6 +151,14 @@ int spu_irq_class_0_bottom(struct spu *spu);
149int spu_irq_class_1_bottom(struct spu *spu); 151int spu_irq_class_1_bottom(struct spu *spu);
150void spu_irq_setaffinity(struct spu *spu, int cpu); 152void spu_irq_setaffinity(struct spu *spu, int cpu);
151 153
154/* system callbacks from the SPU */
155struct spu_syscall_block {
156 u64 nr_ret;
157 u64 parm[6];
158};
159extern long spu_sys_callback(struct spu_syscall_block *s);
160
161/* syscalls implemented in spufs */
152extern struct spufs_calls { 162extern struct spufs_calls {
153 asmlinkage long (*create_thread)(const char __user *name, 163 asmlinkage long (*create_thread)(const char __user *name,
154 unsigned int flags, mode_t mode); 164 unsigned int flags, mode_t mode);
@@ -399,7 +409,6 @@ struct spu_priv1 {
399#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS) 409#define SPU_GET_REVISION_BITS(vr) (vr & SPU_REVISION_BITS)
400 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */ 410 u8 pad_0x28_0x100[0x100 - 0x28]; /* 0x28 */
401 411
402
403 /* Interrupt Area */ 412 /* Interrupt Area */
404 u64 int_mask_RW[3]; /* 0x100 */ 413 u64 int_mask_RW[3]; /* 0x100 */
405#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L 414#define CLASS0_ENABLE_DMA_ALIGNMENT_INTR 0x1L