diff options
Diffstat (limited to 'include/asm-powerpc/reg.h')
-rw-r--r-- | include/asm-powerpc/reg.h | 52 |
1 files changed, 37 insertions, 15 deletions
diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h index 281011e953ec..e775ff1ca413 100644 --- a/include/asm-powerpc/reg.h +++ b/include/asm-powerpc/reg.h | |||
@@ -102,12 +102,8 @@ | |||
102 | #else /* 32-bit */ | 102 | #else /* 32-bit */ |
103 | /* Default MSR for kernel mode. */ | 103 | /* Default MSR for kernel mode. */ |
104 | #ifndef MSR_KERNEL /* reg_booke.h also defines this */ | 104 | #ifndef MSR_KERNEL /* reg_booke.h also defines this */ |
105 | #ifdef CONFIG_APUS_FAST_EXCEPT | ||
106 | #define MSR_KERNEL (MSR_ME|MSR_IP|MSR_RI|MSR_IR|MSR_DR) | ||
107 | #else | ||
108 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) | 105 | #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR) |
109 | #endif | 106 | #endif |
110 | #endif | ||
111 | 107 | ||
112 | #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) | 108 | #define MSR_USER (MSR_KERNEL|MSR_PR|MSR_EE) |
113 | #endif | 109 | #endif |
@@ -518,21 +514,47 @@ | |||
518 | #define PA6T_MMCR1_ES4 0x0000000000ff0000UL | 514 | #define PA6T_MMCR1_ES4 0x0000000000ff0000UL |
519 | #define PA6T_MMCR1_ES5 0x00000000ff000000UL | 515 | #define PA6T_MMCR1_ES5 0x00000000ff000000UL |
520 | 516 | ||
521 | #define SPRN_PA6T_SIAR 780 | 517 | #define SPRN_PA6T_UPMC0 771 /* User PerfMon Counter 0 */ |
522 | #define SPRN_PA6T_UPMC0 771 | 518 | #define SPRN_PA6T_UPMC1 772 /* ... */ |
523 | #define SPRN_PA6T_UPMC1 772 | ||
524 | #define SPRN_PA6T_UPMC2 773 | 519 | #define SPRN_PA6T_UPMC2 773 |
525 | #define SPRN_PA6T_UPMC3 774 | 520 | #define SPRN_PA6T_UPMC3 774 |
526 | #define SPRN_PA6T_UPMC4 775 | 521 | #define SPRN_PA6T_UPMC4 775 |
527 | #define SPRN_PA6T_UPMC5 776 | 522 | #define SPRN_PA6T_UPMC5 776 |
528 | #define SPRN_PA6T_UMMCR0 779 | 523 | #define SPRN_PA6T_UMMCR0 779 /* User Monitor Mode Control Register 0 */ |
529 | #define SPRN_PA6T_UMMCR1 782 | 524 | #define SPRN_PA6T_SIAR 780 /* Sampled Instruction Address */ |
530 | #define SPRN_PA6T_PMC0 787 | 525 | #define SPRN_PA6T_UMMCR1 782 /* User Monitor Mode Control Register 1 */ |
531 | #define SPRN_PA6T_PMC1 788 | 526 | #define SPRN_PA6T_SIER 785 /* Sampled Instruction Event Register */ |
532 | #define SPRN_PA6T_PMC2 789 | 527 | #define SPRN_PA6T_PMC0 787 |
533 | #define SPRN_PA6T_PMC3 790 | 528 | #define SPRN_PA6T_PMC1 788 |
534 | #define SPRN_PA6T_PMC4 791 | 529 | #define SPRN_PA6T_PMC2 789 |
535 | #define SPRN_PA6T_PMC5 792 | 530 | #define SPRN_PA6T_PMC3 790 |
531 | #define SPRN_PA6T_PMC4 791 | ||
532 | #define SPRN_PA6T_PMC5 792 | ||
533 | #define SPRN_PA6T_TSR0 793 /* Timestamp Register 0 */ | ||
534 | #define SPRN_PA6T_TSR1 794 /* Timestamp Register 1 */ | ||
535 | #define SPRN_PA6T_TSR2 799 /* Timestamp Register 2 */ | ||
536 | #define SPRN_PA6T_TSR3 784 /* Timestamp Register 3 */ | ||
537 | |||
538 | #define SPRN_PA6T_IER 981 /* Icache Error Register */ | ||
539 | #define SPRN_PA6T_DER 982 /* Dcache Error Register */ | ||
540 | #define SPRN_PA6T_BER 862 /* BIU Error Address Register */ | ||
541 | #define SPRN_PA6T_MER 849 /* MMU Error Register */ | ||
542 | |||
543 | #define SPRN_PA6T_IMA0 880 /* Instruction Match Array 0 */ | ||
544 | #define SPRN_PA6T_IMA1 881 /* ... */ | ||
545 | #define SPRN_PA6T_IMA2 882 | ||
546 | #define SPRN_PA6T_IMA3 883 | ||
547 | #define SPRN_PA6T_IMA4 884 | ||
548 | #define SPRN_PA6T_IMA5 885 | ||
549 | #define SPRN_PA6T_IMA6 886 | ||
550 | #define SPRN_PA6T_IMA7 887 | ||
551 | #define SPRN_PA6T_IMA8 888 | ||
552 | #define SPRN_PA6T_IMA9 889 | ||
553 | #define SPRN_PA6T_BTCR 978 /* Breakpoint and Tagging Control Register */ | ||
554 | #define SPRN_PA6T_IMAAT 979 /* Instruction Match Array Action Table */ | ||
555 | #define SPRN_PA6T_PCCR 1019 /* Power Counter Control Register */ | ||
556 | #define SPRN_PA6T_RPCCR 1021 /* Retire PC Trace Control Register */ | ||
557 | |||
536 | 558 | ||
537 | #else /* 32-bit */ | 559 | #else /* 32-bit */ |
538 | #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ | 560 | #define SPRN_MMCR0 952 /* Monitor Mode Control Register 0 */ |