1 files changed, 9 insertions, 1 deletions

diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index edc0cfd7f6e2..c6d1ab650778 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -30,6 +30,7 @@
 #define MSR_ISF_LG      61              /* Interrupt 64b mode valid on 630 */
 #define MSR_HV_LG       60              /* Hypervisor state */
 #define MSR_VEC_LG      25              /* Enable AltiVec */
+#define MSR_VSX_LG      23              /* Enable VSX */
 #define MSR_POW_LG      18              /* Enable Power Management */
 #define MSR_WE_LG       18              /* Wait State Enable */
 #define MSR_TGPR_LG     17              /* TLB Update registers in use */
@@ -71,6 +72,7 @@
 #endif
 
 #define MSR_VEC         __MASK(MSR_VEC_LG)      /* Enable AltiVec */
+#define MSR_VSX         __MASK(MSR_VSX_LG)      /* Enable VSX */
 #define MSR_POW         __MASK(MSR_POW_LG)      /* Enable Power Management */
 #define MSR_WE          __MASK(MSR_WE_LG)       /* Wait State Enable */
 #define MSR_TGPR        __MASK(MSR_TGPR_LG)     /* TLB Update registers in use */
@@ -153,10 +155,12 @@
 #define   CTRL_RUNLATCH 0x1
 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
 #define   DABR_TRANSLATION      (1UL << 2)
+#define SPRN_DABR2      0x13D   /* e300 */
 #define SPRN_DABRX      0x3F7   /* Data Address Breakpoint Register Extension */
 #define   DABRX_USER    (1UL << 0)
 #define   DABRX_KERNEL  (1UL << 1)
 #define SPRN_DAR        0x013   /* Data Address Register */
+#define SPRN_DBCR       0x136   /* e300 Data Breakpoint Control Reg */
 #define SPRN_DSISR      0x012   /* Data Storage Interrupt Status Register */
 #define   DSISR_NOHPTE          0x40000000      /* no translation found */
 #define   DSISR_PROTFAULT       0x08000000      /* protection fault */
@@ -240,7 +244,7 @@
 #define HID0_DAPUEN     (1<<8)          /* Debug APU enable */
 #define HID0_SGE        (1<<7)          /* Store Gathering Enable */
 #define HID0_SIED       (1<<7)          /* Serial Instr. Execution [Disable] */
-#define HID0_DFCA       (1<<6)          /* Data Cache Flush Assist */
+#define HID0_DCFA       (1<<6)          /* Data Cache Flush Assist */
 #define HID0_LRSTK      (1<<4)          /* Link register stack - 745x */
 #define HID0_BTIC       (1<<5)          /* Branch Target Instr Cache Enable */
 #define HID0_ABE        (1<<3)          /* Address Broadcast Enable */
@@ -262,6 +266,8 @@
 #define HID1_PS         (1<<16)         /* 750FX PLL selection */
 #define SPRN_HID2       0x3F8           /* Hardware Implementation Register 2 */
 #define SPRN_IABR       0x3F2   /* Instruction Address Breakpoint Register */
+#define SPRN_IABR2      0x3FA           /* 83xx */
+#define SPRN_IBCR       0x135           /* 83xx Insn Breakpoint Control Reg */
 #define SPRN_HID4       0x3F4           /* 970 HID4 */
 #define SPRN_HID5       0x3F6           /* 970 HID5 */
 #define SPRN_HID6       0x3F9   /* BE HID 6 */
@@ -732,6 +738,8 @@
                                 "       .llong %1\n"                    \
                                 "       .llong 97b-98b\n"               \
                                 "       .llong 99b-98b\n"               \
+                                "       .llong 0\n"                     \
+                                "       .llong 0\n"                     \
                                 ".previous"                             \
                         : "=r" (rval) : "i" (CPU_FTR_CELL_TB_BUG)); rval;})
 #else