1 files changed, 46 insertions, 12 deletions

diff --git a/include/asm-powerpc/reg.h b/include/asm-powerpc/reg.h
index eb392d038ed7..12ecc9b9f285 100644
--- a/include/asm-powerpc/reg.h
+++ b/include/asm-powerpc/reg.h
@@ -145,6 +145,10 @@
 #define SPRN_CTR        0x009   /* Count Register */
 #define SPRN_CTRLF      0x088
 #define SPRN_CTRLT      0x098
+#define   CTRL_CT       0xc0000000      /* current thread */
+#define   CTRL_CT0      0x80000000      /* thread 0 */
+#define   CTRL_CT1      0x40000000      /* thread 1 */
+#define   CTRL_TE       0x00c00000      /* thread enable */
 #define   CTRL_RUNLATCH 0x1
 #define SPRN_DABR       0x3F5   /* Data Address Breakpoint Register */
 #define   DABR_TRANSLATION      (1UL << 2)
@@ -257,11 +261,11 @@
 #define SPRN_HID6       0x3F9   /* BE HID 6 */
 #define   HID6_LB       (0x0F<<12) /* Concurrent Large Page Modes */
 #define   HID6_DLP      (1<<20) /* Disable all large page modes (4K only) */
-#define SPRN_TSCR       0x399   /* Thread switch control on BE */
-#define SPRN_TTR        0x39A   /* Thread switch timeout on BE */
-#define   TSCR_DEC_ENABLE       0x200000 /* Decrementer Interrupt */
-#define   TSCR_EE_ENABLE        0x100000 /* External Interrupt */
-#define   TSCR_EE_BOOST         0x080000 /* External Interrupt Boost */
+#define SPRN_TSC_CELL   0x399   /* Thread switch control on Cell */
+#define   TSC_CELL_DEC_ENABLE_0 0x400000 /* Decrementer Interrupt */
+#define   TSC_CELL_DEC_ENABLE_1 0x200000 /* Decrementer Interrupt */
+#define   TSC_CELL_EE_ENABLE    0x100000 /* External Interrupt */
+#define   TSC_CELL_EE_BOOST     0x080000 /* External Interrupt Boost */
 #define SPRN_TSC        0x3FD   /* Thread switch control on others */
 #define SPRN_TST        0x3FC   /* Thread switch timeout on others */
 #if !defined(SPRN_IAC1) && !defined(SPRN_IAC2)
@@ -375,6 +379,14 @@
 #define SPRN_SPRG7      0x117   /* Special Purpose Register General 7 */
 #define SPRN_SRR0       0x01A   /* Save/Restore Register 0 */
 #define SPRN_SRR1       0x01B   /* Save/Restore Register 1 */
+#define   SRR1_WAKEMASK         0x00380000 /* reason for wakeup */
+#define   SRR1_WAKERESET        0x00380000 /* System reset */
+#define   SRR1_WAKESYSERR       0x00300000 /* System error */
+#define   SRR1_WAKEEE           0x00200000 /* External interrupt */
+#define   SRR1_WAKEMT           0x00280000 /* mtctrl */
+#define   SRR1_WAKEDEC          0x00180000 /* Decrementer interrupt */
+#define   SRR1_WAKETHERM        0x00100000 /* Thermal management interrupt */
+
 #ifndef SPRN_SVR
 #define SPRN_SVR        0x11E   /* System Version Register */
 #endif
@@ -443,12 +455,35 @@
 #define SPRN_SDAR       781
 
 #else /* 32-bit */
-#define SPRN_MMCR0      0x3B8   /* Monitor Mode Control Register 0 */
-#define SPRN_MMCR1      0x3BC   /* Monitor Mode Control Register 1 */
-#define SPRN_PMC1       0x3B9   /* Performance Counter Register 1 */
-#define SPRN_PMC2       0x3BA   /* Performance Counter Register 2 */
-#define SPRN_PMC3       0x3BD   /* Performance Counter Register 3 */
-#define SPRN_PMC4       0x3BE   /* Performance Counter Register 4 */
+#define SPRN_MMCR0      952     /* Monitor Mode Control Register 0 */
+#define   MMCR0_FC      0x80000000UL /* freeze counters */
+#define   MMCR0_FCS     0x40000000UL /* freeze in supervisor state */
+#define   MMCR0_FCP     0x20000000UL /* freeze in problem state */
+#define   MMCR0_FCM1    0x10000000UL /* freeze counters while MSR mark = 1 */
+#define   MMCR0_FCM0    0x08000000UL /* freeze counters while MSR mark = 0 */
+#define   MMCR0_PMXE    0x04000000UL /* performance monitor exception enable */
+#define   MMCR0_FCECE   0x02000000UL /* freeze ctrs on enabled cond or event */
+#define   MMCR0_TBEE    0x00400000UL /* time base exception enable */
+#define   MMCR0_PMC1CE  0x00008000UL /* PMC1 count enable*/
+#define   MMCR0_PMCnCE  0x00004000UL /* count enable for all but PMC 1*/
+#define   MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
+#define   MMCR0_PMC1SEL 0x00001fc0UL /* PMC 1 Event */
+#define   MMCR0_PMC2SEL 0x0000003fUL /* PMC 2 Event */
+
+#define SPRN_MMCR1      956
+#define   MMCR1_PMC3SEL 0xf8000000UL /* PMC 3 Event */
+#define   MMCR1_PMC4SEL 0x07c00000UL /* PMC 4 Event */
+#define   MMCR1_PMC5SEL 0x003e0000UL /* PMC 5 Event */
+#define   MMCR1_PMC6SEL 0x0001f800UL /* PMC 6 Event */
+#define SPRN_MMCR2      944
+#define SPRN_PMC1       953     /* Performance Counter Register 1 */
+#define SPRN_PMC2       954     /* Performance Counter Register 2 */
+#define SPRN_PMC3       957     /* Performance Counter Register 3 */
+#define SPRN_PMC4       958     /* Performance Counter Register 4 */
+#define SPRN_PMC5       945     /* Performance Counter Register 5 */
+#define SPRN_PMC6       946     /* Performance Counter Register 6 */
+
+#define SPRN_SIAR       955     /* Sampled Instruction Address Register */
 
 /* Bit definitions for MMCR0 and PMC1 / PMC2. */
 #define MMCR0_PMC1_CYCLES       (1 << 7)
@@ -458,7 +493,6 @@
 #define MMCR0_PMC2_CYCLES       0x1
 #define MMCR0_PMC2_ITLB         0x7
 #define MMCR0_PMC2_LOADMISSTIME 0x5
-#define MMCR0_PMXE      (1 << 26)
 #endif
 
 /* Processor Version Register (PVR) field extraction */