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-rw-r--r--include/asm-powerpc/qe.h156
1 files changed, 109 insertions, 47 deletions
diff --git a/include/asm-powerpc/qe.h b/include/asm-powerpc/qe.h
index 0dabe46a29d2..430dc77b35fc 100644
--- a/include/asm-powerpc/qe.h
+++ b/include/asm-powerpc/qe.h
@@ -28,6 +28,52 @@
28#define MEM_PART_SECONDARY 1 28#define MEM_PART_SECONDARY 1
29#define MEM_PART_MURAM 2 29#define MEM_PART_MURAM 2
30 30
31/* Clocks and BRGs */
32enum qe_clock {
33 QE_CLK_NONE = 0,
34 QE_BRG1, /* Baud Rate Generator 1 */
35 QE_BRG2, /* Baud Rate Generator 2 */
36 QE_BRG3, /* Baud Rate Generator 3 */
37 QE_BRG4, /* Baud Rate Generator 4 */
38 QE_BRG5, /* Baud Rate Generator 5 */
39 QE_BRG6, /* Baud Rate Generator 6 */
40 QE_BRG7, /* Baud Rate Generator 7 */
41 QE_BRG8, /* Baud Rate Generator 8 */
42 QE_BRG9, /* Baud Rate Generator 9 */
43 QE_BRG10, /* Baud Rate Generator 10 */
44 QE_BRG11, /* Baud Rate Generator 11 */
45 QE_BRG12, /* Baud Rate Generator 12 */
46 QE_BRG13, /* Baud Rate Generator 13 */
47 QE_BRG14, /* Baud Rate Generator 14 */
48 QE_BRG15, /* Baud Rate Generator 15 */
49 QE_BRG16, /* Baud Rate Generator 16 */
50 QE_CLK1, /* Clock 1 */
51 QE_CLK2, /* Clock 2 */
52 QE_CLK3, /* Clock 3 */
53 QE_CLK4, /* Clock 4 */
54 QE_CLK5, /* Clock 5 */
55 QE_CLK6, /* Clock 6 */
56 QE_CLK7, /* Clock 7 */
57 QE_CLK8, /* Clock 8 */
58 QE_CLK9, /* Clock 9 */
59 QE_CLK10, /* Clock 10 */
60 QE_CLK11, /* Clock 11 */
61 QE_CLK12, /* Clock 12 */
62 QE_CLK13, /* Clock 13 */
63 QE_CLK14, /* Clock 14 */
64 QE_CLK15, /* Clock 15 */
65 QE_CLK16, /* Clock 16 */
66 QE_CLK17, /* Clock 17 */
67 QE_CLK18, /* Clock 18 */
68 QE_CLK19, /* Clock 19 */
69 QE_CLK20, /* Clock 20 */
70 QE_CLK21, /* Clock 21 */
71 QE_CLK22, /* Clock 22 */
72 QE_CLK23, /* Clock 23 */
73 QE_CLK24, /* Clock 24 */
74 QE_CLK_DUMMY
75};
76
31/* Export QE common operations */ 77/* Export QE common operations */
32extern void qe_reset(void); 78extern void qe_reset(void);
33extern int par_io_init(struct device_node *np); 79extern int par_io_init(struct device_node *np);
@@ -38,7 +84,8 @@ extern int par_io_data_set(u8 port, u8 pin, u8 val);
38 84
39/* QE internal API */ 85/* QE internal API */
40int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 86int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
41void qe_setbrg(unsigned int brg, unsigned int rate, unsigned int multiplier); 87enum qe_clock qe_clock_source(const char *source);
88int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
42int qe_get_snum(void); 89int qe_get_snum(void);
43void qe_put_snum(u8 snum); 90void qe_put_snum(u8 snum);
44unsigned long qe_muram_alloc(int size, int align); 91unsigned long qe_muram_alloc(int size, int align);
@@ -47,6 +94,58 @@ unsigned long qe_muram_alloc_fixed(unsigned long offset, int size);
47void qe_muram_dump(void); 94void qe_muram_dump(void);
48void *qe_muram_addr(unsigned long offset); 95void *qe_muram_addr(unsigned long offset);
49 96
97/* Structure that defines QE firmware binary files.
98 *
99 * See Documentation/powerpc/qe-firmware.txt for a description of these
100 * fields.
101 */
102struct qe_firmware {
103 struct qe_header {
104 __be32 length; /* Length of the entire structure, in bytes */
105 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
106 u8 version; /* Version of this layout. First ver is '1' */
107 } header;
108 u8 id[62]; /* Null-terminated identifier string */
109 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
110 u8 count; /* Number of microcode[] structures */
111 struct {
112 __be16 model; /* The SOC model */
113 u8 major; /* The SOC revision major */
114 u8 minor; /* The SOC revision minor */
115 } __attribute__ ((packed)) soc;
116 u8 padding[4]; /* Reserved, for alignment */
117 __be64 extended_modes; /* Extended modes */
118 __be32 vtraps[8]; /* Virtual trap addresses */
119 u8 reserved[4]; /* Reserved, for future expansion */
120 struct qe_microcode {
121 u8 id[32]; /* Null-terminated identifier */
122 __be32 traps[16]; /* Trap addresses, 0 == ignore */
123 __be32 eccr; /* The value for the ECCR register */
124 __be32 iram_offset; /* Offset into I-RAM for the code */
125 __be32 count; /* Number of 32-bit words of the code */
126 __be32 code_offset; /* Offset of the actual microcode */
127 u8 major; /* The microcode version major */
128 u8 minor; /* The microcode version minor */
129 u8 revision; /* The microcode version revision */
130 u8 padding; /* Reserved, for alignment */
131 u8 reserved[4]; /* Reserved, for future expansion */
132 } __attribute__ ((packed)) microcode[1];
133 /* All microcode binaries should be located here */
134 /* CRC32 should be located here, after the microcode binaries */
135} __attribute__ ((packed));
136
137struct qe_firmware_info {
138 char id[64]; /* Firmware name */
139 u32 vtraps[8]; /* Virtual trap addresses */
140 u64 extended_modes; /* Extended modes */
141};
142
143/* Upload a firmware to the QE */
144int qe_upload_firmware(const struct qe_firmware *firmware);
145
146/* Obtain information on the uploaded firmware */
147struct qe_firmware_info *qe_get_firmware_info(void);
148
50/* Buffer descriptors */ 149/* Buffer descriptors */
51struct qe_bd { 150struct qe_bd {
52 __be16 status; 151 __be16 status;
@@ -129,52 +228,6 @@ enum comm_dir {
129 COMM_DIR_RX_AND_TX = 3 228 COMM_DIR_RX_AND_TX = 3
130}; 229};
131 230
132/* Clocks and BRGs */
133enum qe_clock {
134 QE_CLK_NONE = 0,
135 QE_BRG1, /* Baud Rate Generator 1 */
136 QE_BRG2, /* Baud Rate Generator 2 */
137 QE_BRG3, /* Baud Rate Generator 3 */
138 QE_BRG4, /* Baud Rate Generator 4 */
139 QE_BRG5, /* Baud Rate Generator 5 */
140 QE_BRG6, /* Baud Rate Generator 6 */
141 QE_BRG7, /* Baud Rate Generator 7 */
142 QE_BRG8, /* Baud Rate Generator 8 */
143 QE_BRG9, /* Baud Rate Generator 9 */
144 QE_BRG10, /* Baud Rate Generator 10 */
145 QE_BRG11, /* Baud Rate Generator 11 */
146 QE_BRG12, /* Baud Rate Generator 12 */
147 QE_BRG13, /* Baud Rate Generator 13 */
148 QE_BRG14, /* Baud Rate Generator 14 */
149 QE_BRG15, /* Baud Rate Generator 15 */
150 QE_BRG16, /* Baud Rate Generator 16 */
151 QE_CLK1, /* Clock 1 */
152 QE_CLK2, /* Clock 2 */
153 QE_CLK3, /* Clock 3 */
154 QE_CLK4, /* Clock 4 */
155 QE_CLK5, /* Clock 5 */
156 QE_CLK6, /* Clock 6 */
157 QE_CLK7, /* Clock 7 */
158 QE_CLK8, /* Clock 8 */
159 QE_CLK9, /* Clock 9 */
160 QE_CLK10, /* Clock 10 */
161 QE_CLK11, /* Clock 11 */
162 QE_CLK12, /* Clock 12 */
163 QE_CLK13, /* Clock 13 */
164 QE_CLK14, /* Clock 14 */
165 QE_CLK15, /* Clock 15 */
166 QE_CLK16, /* Clock 16 */
167 QE_CLK17, /* Clock 17 */
168 QE_CLK18, /* Clock 18 */
169 QE_CLK19, /* Clock 19 */
170 QE_CLK20, /* Clock 20 */
171 QE_CLK21, /* Clock 21 */
172 QE_CLK22, /* Clock 22 */
173 QE_CLK23, /* Clock 23 */
174 QE_CLK24, /* Clock 24 */
175 QE_CLK_DUMMY,
176};
177
178/* QE CMXUCR Registers. 231/* QE CMXUCR Registers.
179 * There are two UCCs represented in each of the four CMXUCR registers. 232 * There are two UCCs represented in each of the four CMXUCR registers.
180 * These values are for the UCC in the LSBs 233 * These values are for the UCC in the LSBs
@@ -328,6 +381,15 @@ enum qe_clock {
328 381
329#define QE_SDEBCR_BA_MASK 0x01FFFFFF 382#define QE_SDEBCR_BA_MASK 0x01FFFFFF
330 383
384/* Communication Processor */
385#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
386#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
387#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
388
389/* I-RAM */
390#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
391#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
392
331/* UPC */ 393/* UPC */
332#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ 394#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
333#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ 395#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-18 15:09:14 -0500