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-rw-r--r--include/asm-powerpc/ppc_asm.h437
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diff --git a/include/asm-powerpc/ppc_asm.h b/include/asm-powerpc/ppc_asm.h
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1/*
2 * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan.
3 */
4
5#ifndef _ASM_POWERPC_PPC_ASM_H
6#define _ASM_POWERPC_PPC_ASM_H
7
8#ifdef __ASSEMBLY__
9
10/*
11 * Macros for storing registers into and loading registers from
12 * exception frames.
13 */
14#ifdef __powerpc64__
15#define SAVE_GPR(n, base) std n,GPR0+8*(n)(base)
16#define REST_GPR(n, base) ld n,GPR0+8*(n)(base)
17#define SAVE_NVGPRS(base) SAVE_8GPRS(14, base); SAVE_10GPRS(22, base)
18#define REST_NVGPRS(base) REST_8GPRS(14, base); REST_10GPRS(22, base)
19#else
20#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base)
21#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base)
22#define SAVE_NVGPRS(base) SAVE_GPR(13, base); SAVE_8GPRS(14, base); \
23 SAVE_10GPRS(22, base)
24#define REST_NVGPRS(base) REST_GPR(13, base); REST_8GPRS(14, base); \
25 REST_10GPRS(22, base)
26#endif
27
28
29#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base)
30#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base)
31#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base)
32#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base)
33#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base)
34#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base)
35#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base)
36#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base)
37
38#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base)
39#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base)
40#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base)
41#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base)
42#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base)
43#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base)
44#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base)
45#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base)
46#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base)
47#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base)
48#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base)
49#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base)
50
51#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base
52#define SAVE_2VRS(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base)
53#define SAVE_4VRS(n,b,base) SAVE_2VRS(n,b,base); SAVE_2VRS(n+2,b,base)
54#define SAVE_8VRS(n,b,base) SAVE_4VRS(n,b,base); SAVE_4VRS(n+4,b,base)
55#define SAVE_16VRS(n,b,base) SAVE_8VRS(n,b,base); SAVE_8VRS(n+8,b,base)
56#define SAVE_32VRS(n,b,base) SAVE_16VRS(n,b,base); SAVE_16VRS(n+16,b,base)
57#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base
58#define REST_2VRS(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base)
59#define REST_4VRS(n,b,base) REST_2VRS(n,b,base); REST_2VRS(n+2,b,base)
60#define REST_8VRS(n,b,base) REST_4VRS(n,b,base); REST_4VRS(n+4,b,base)
61#define REST_16VRS(n,b,base) REST_8VRS(n,b,base); REST_8VRS(n+8,b,base)
62#define REST_32VRS(n,b,base) REST_16VRS(n,b,base); REST_16VRS(n+16,b,base)
63
64#define SAVE_EVR(n,s,base) evmergehi s,s,n; stw s,THREAD_EVR0+4*(n)(base)
65#define SAVE_2EVRS(n,s,base) SAVE_EVR(n,s,base); SAVE_EVR(n+1,s,base)
66#define SAVE_4EVRS(n,s,base) SAVE_2EVRS(n,s,base); SAVE_2EVRS(n+2,s,base)
67#define SAVE_8EVRS(n,s,base) SAVE_4EVRS(n,s,base); SAVE_4EVRS(n+4,s,base)
68#define SAVE_16EVRS(n,s,base) SAVE_8EVRS(n,s,base); SAVE_8EVRS(n+8,s,base)
69#define SAVE_32EVRS(n,s,base) SAVE_16EVRS(n,s,base); SAVE_16EVRS(n+16,s,base)
70#define REST_EVR(n,s,base) lwz s,THREAD_EVR0+4*(n)(base); evmergelo n,s,n
71#define REST_2EVRS(n,s,base) REST_EVR(n,s,base); REST_EVR(n+1,s,base)
72#define REST_4EVRS(n,s,base) REST_2EVRS(n,s,base); REST_2EVRS(n+2,s,base)
73#define REST_8EVRS(n,s,base) REST_4EVRS(n,s,base); REST_4EVRS(n+4,s,base)
74#define REST_16EVRS(n,s,base) REST_8EVRS(n,s,base); REST_8EVRS(n+8,s,base)
75#define REST_32EVRS(n,s,base) REST_16EVRS(n,s,base); REST_16EVRS(n+16,s,base)
76
77/* Macros to adjust thread priority for Iseries hardware multithreading */
78#define HMT_LOW or 1,1,1
79#define HMT_MEDIUM or 2,2,2
80#define HMT_HIGH or 3,3,3
81
82/* handle instructions that older assemblers may not know */
83#define RFCI .long 0x4c000066 /* rfci instruction */
84#define RFDI .long 0x4c00004e /* rfdi instruction */
85#define RFMCI .long 0x4c00004c /* rfmci instruction */
86
87/*
88 * LOADADDR( rn, name )
89 * loads the address of 'name' into 'rn'
90 *
91 * LOADBASE( rn, name )
92 * loads the address (less the low 16 bits) of 'name' into 'rn'
93 * suitable for base+disp addressing
94 */
95#ifdef __powerpc64__
96#define LOADADDR(rn,name) \
97 lis rn,name##@highest; \
98 ori rn,rn,name##@higher; \
99 rldicr rn,rn,32,31; \
100 oris rn,rn,name##@h; \
101 ori rn,rn,name##@l
102
103#define LOADBASE(rn,name) \
104 lis rn,name@highest; \
105 ori rn,rn,name@higher; \
106 rldicr rn,rn,32,31; \
107 oris rn,rn,name@ha
108
109
110#define SET_REG_TO_CONST(reg, value) \
111 lis reg,(((value)>>48)&0xFFFF); \
112 ori reg,reg,(((value)>>32)&0xFFFF); \
113 rldicr reg,reg,32,31; \
114 oris reg,reg,(((value)>>16)&0xFFFF); \
115 ori reg,reg,((value)&0xFFFF);
116
117#define SET_REG_TO_LABEL(reg, label) \
118 lis reg,(label)@highest; \
119 ori reg,reg,(label)@higher; \
120 rldicr reg,reg,32,31; \
121 oris reg,reg,(label)@h; \
122 ori reg,reg,(label)@l;
123#endif
124
125/* various errata or part fixups */
126#ifdef CONFIG_PPC601_SYNC_FIX
127#define SYNC \
128BEGIN_FTR_SECTION \
129 sync; \
130 isync; \
131END_FTR_SECTION_IFSET(CPU_FTR_601)
132#define SYNC_601 \
133BEGIN_FTR_SECTION \
134 sync; \
135END_FTR_SECTION_IFSET(CPU_FTR_601)
136#define ISYNC_601 \
137BEGIN_FTR_SECTION \
138 isync; \
139END_FTR_SECTION_IFSET(CPU_FTR_601)
140#else
141#define SYNC
142#define SYNC_601
143#define ISYNC_601
144#endif
145
146
147#ifndef CONFIG_SMP
148#define TLBSYNC
149#else /* CONFIG_SMP */
150/* tlbsync is not implemented on 601 */
151#define TLBSYNC \
152BEGIN_FTR_SECTION \
153 tlbsync; \
154 sync; \
155END_FTR_SECTION_IFCLR(CPU_FTR_601)
156#endif
157
158
159/*
160 * This instruction is not implemented on the PPC 603 or 601; however, on
161 * the 403GCX and 405GP tlbia IS defined and tlbie is not.
162 * All of these instructions exist in the 8xx, they have magical powers,
163 * and they must be used.
164 */
165
166#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx)
167#define tlbia \
168 li r4,1024; \
169 mtctr r4; \
170 lis r4,KERNELBASE@h; \
1710: tlbie r4; \
172 addi r4,r4,0x1000; \
173 bdnz 0b
174#endif
175
176
177#ifdef CONFIG_IBM405_ERR77
178#define PPC405_ERR77(ra,rb) dcbt ra, rb;
179#define PPC405_ERR77_SYNC sync;
180#else
181#define PPC405_ERR77(ra,rb)
182#define PPC405_ERR77_SYNC
183#endif
184
185
186#ifdef CONFIG_IBM440EP_ERR42
187#define PPC440EP_ERR42 isync
188#else
189#define PPC440EP_ERR42
190#endif
191
192
193#if defined(CONFIG_BOOKE)
194#define tophys(rd,rs) \
195 addis rd,rs,0
196
197#define tovirt(rd,rs) \
198 addis rd,rs,0
199
200#elif defined(CONFIG_PPC64)
201/* PPPBBB - DRENG If KERNELBASE is always 0xC0...,
202 * Then we can easily do this with one asm insn. -Peter
203 */
204#define tophys(rd,rs) \
205 lis rd,((KERNELBASE>>48)&0xFFFF); \
206 rldicr rd,rd,32,31; \
207 sub rd,rs,rd
208
209#define tovirt(rd,rs) \
210 lis rd,((KERNELBASE>>48)&0xFFFF); \
211 rldicr rd,rd,32,31; \
212 add rd,rs,rd
213#else
214/*
215 * On APUS (Amiga PowerPC cpu upgrade board), we don't know the
216 * physical base address of RAM at compile time.
217 */
218#define tophys(rd,rs) \
2190: addis rd,rs,-KERNELBASE@h; \
220 .section ".vtop_fixup","aw"; \
221 .align 1; \
222 .long 0b; \
223 .previous
224
225#define tovirt(rd,rs) \
2260: addis rd,rs,KERNELBASE@h; \
227 .section ".ptov_fixup","aw"; \
228 .align 1; \
229 .long 0b; \
230 .previous
231#endif
232
233/*
234 * On 64-bit cpus, we use the rfid instruction instead of rfi, but
235 * we then have to make sure we preserve the top 32 bits except for
236 * the 64-bit mode bit, which we clear.
237 */
238#if defined(CONFIG_PPC64BRIDGE)
239#define FIX_SRR1(ra, rb) \
240 mr rb,ra; \
241 mfmsr ra; \
242 clrldi ra,ra,1; /* turn off 64-bit mode */ \
243 rldimi ra,rb,0,32
244#define RFI .long 0x4c000024 /* rfid instruction */
245#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */
246#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
247#elif defined(CONFIG_PPC64)
248/* Insert the high 32 bits of the MSR into what will be the new
249 MSR (via SRR1 and rfid) This preserves the MSR.SF and MSR.ISF
250 bits. */
251
252#define FIX_SRR1(ra, rb) \
253 mr rb,ra; \
254 mfmsr ra; \
255 rldimi ra,rb,0,32
256
257#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */
258
259#else
260#define FIX_SRR1(ra, rb)
261#ifndef CONFIG_40x
262#define RFI rfi
263#else
264#define RFI rfi; b . /* Prevent prefetch past rfi */
265#endif
266#define MTMSRD(r) mtmsr r
267#define CLR_TOP32(r)
268#endif
269
270/* The boring bits... */
271
272/* Condition Register Bit Fields */
273
274#define cr0 0
275#define cr1 1
276#define cr2 2
277#define cr3 3
278#define cr4 4
279#define cr5 5
280#define cr6 6
281#define cr7 7
282
283
284/* General Purpose Registers (GPRs) */
285
286#define r0 0
287#define r1 1
288#define r2 2
289#define r3 3
290#define r4 4
291#define r5 5
292#define r6 6
293#define r7 7
294#define r8 8
295#define r9 9
296#define r10 10
297#define r11 11
298#define r12 12
299#define r13 13
300#define r14 14
301#define r15 15
302#define r16 16
303#define r17 17
304#define r18 18
305#define r19 19
306#define r20 20
307#define r21 21
308#define r22 22
309#define r23 23
310#define r24 24
311#define r25 25
312#define r26 26
313#define r27 27
314#define r28 28
315#define r29 29
316#define r30 30
317#define r31 31
318
319
320/* Floating Point Registers (FPRs) */
321
322#define fr0 0
323#define fr1 1
324#define fr2 2
325#define fr3 3
326#define fr4 4
327#define fr5 5
328#define fr6 6
329#define fr7 7
330#define fr8 8
331#define fr9 9
332#define fr10 10
333#define fr11 11
334#define fr12 12
335#define fr13 13
336#define fr14 14
337#define fr15 15
338#define fr16 16
339#define fr17 17
340#define fr18 18
341#define fr19 19
342#define fr20 20
343#define fr21 21
344#define fr22 22
345#define fr23 23
346#define fr24 24
347#define fr25 25
348#define fr26 26
349#define fr27 27
350#define fr28 28
351#define fr29 29
352#define fr30 30
353#define fr31 31
354
355/* AltiVec Registers (VPRs) */
356
357#define vr0 0
358#define vr1 1
359#define vr2 2
360#define vr3 3
361#define vr4 4
362#define vr5 5
363#define vr6 6
364#define vr7 7
365#define vr8 8
366#define vr9 9
367#define vr10 10
368#define vr11 11
369#define vr12 12
370#define vr13 13
371#define vr14 14
372#define vr15 15
373#define vr16 16
374#define vr17 17
375#define vr18 18
376#define vr19 19
377#define vr20 20
378#define vr21 21
379#define vr22 22
380#define vr23 23
381#define vr24 24
382#define vr25 25
383#define vr26 26
384#define vr27 27
385#define vr28 28
386#define vr29 29
387#define vr30 30
388#define vr31 31
389
390/* SPE Registers (EVPRs) */
391
392#define evr0 0
393#define evr1 1
394#define evr2 2
395#define evr3 3
396#define evr4 4
397#define evr5 5
398#define evr6 6
399#define evr7 7
400#define evr8 8
401#define evr9 9
402#define evr10 10
403#define evr11 11
404#define evr12 12
405#define evr13 13
406#define evr14 14
407#define evr15 15
408#define evr16 16
409#define evr17 17
410#define evr18 18
411#define evr19 19
412#define evr20 20
413#define evr21 21
414#define evr22 22
415#define evr23 23
416#define evr24 24
417#define evr25 25
418#define evr26 26
419#define evr27 27
420#define evr28 28
421#define evr29 29
422#define evr30 30
423#define evr31 31
424
425/* some stab codes */
426#define N_FUN 36
427#define N_RSYM 64
428#define N_SLINE 68
429#define N_SO 100
430
431#define ASM_CONST(x) x
432#else
433 #define __ASM_CONST(x) x##UL
434 #define ASM_CONST(x) __ASM_CONST(x)
435#endif /* __ASSEMBLY__ */
436
437#endif /* _ASM_POWERPC_PPC_ASM_H */