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-rw-r--r--include/asm-powerpc/pgtable-64k.h21
1 files changed, 18 insertions, 3 deletions
diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h
index 1cbd6b377eea..07b0d8f09cb6 100644
--- a/include/asm-powerpc/pgtable-64k.h
+++ b/include/asm-powerpc/pgtable-64k.h
@@ -70,11 +70,27 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
70#define PGDIR_MASK (~(PGDIR_SIZE-1)) 70#define PGDIR_MASK (~(PGDIR_SIZE-1))
71 71
72/* Additional PTE bits (don't change without checking asm in hash_low.S) */ 72/* Additional PTE bits (don't change without checking asm in hash_low.S) */
73#define __HAVE_ARCH_PTE_SPECIAL
74#define _PAGE_SPECIAL 0x00000400 /* software: special page */
73#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */ 75#define _PAGE_HPTE_SUB 0x0ffff000 /* combo only: sub pages HPTE bits */
74#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */ 76#define _PAGE_HPTE_SUB0 0x08000000 /* combo only: first sub page */
75#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */ 77#define _PAGE_COMBO 0x10000000 /* this is a combo 4k page */
76#define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */ 78#define _PAGE_4K_PFN 0x20000000 /* PFN is for a single 4k page */
77 79
80/* For 64K page, we don't have a separate _PAGE_HASHPTE bit. Instead,
81 * we set that to be the whole sub-bits mask. The C code will only
82 * test this, so a multi-bit mask will work. For combo pages, this
83 * is equivalent as effectively, the old _PAGE_HASHPTE was an OR of
84 * all the sub bits. For real 64k pages, we now have the assembly set
85 * _PAGE_HPTE_SUB0 in addition to setting the HIDX bits which overlap
86 * that mask. This is fine as long as the HIDX bits are never set on
87 * a PTE that isn't hashed, which is the case today.
88 *
89 * A little nit is for the huge page C code, which does the hashing
90 * in C, we need to provide which bit to use.
91 */
92#define _PAGE_HASHPTE _PAGE_HPTE_SUB
93
78/* Note the full page bits must be in the same location as for normal 94/* Note the full page bits must be in the same location as for normal
79 * 4k pages as the same asssembly will be used to insert 64K pages 95 * 4k pages as the same asssembly will be used to insert 64K pages
80 * wether the kernel has CONFIG_PPC_64K_PAGES or not 96 * wether the kernel has CONFIG_PPC_64K_PAGES or not
@@ -83,8 +99,7 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
83#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */ 99#define _PAGE_F_GIX 0x00007000 /* full page: hidx bits */
84 100
85/* PTE flags to conserve for HPTE identification */ 101/* PTE flags to conserve for HPTE identification */
86#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_HPTE_SUB |\ 102#define _PAGE_HPTEFLAGS (_PAGE_BUSY | _PAGE_HASHPTE | _PAGE_COMBO)
87 _PAGE_COMBO)
88 103
89/* Shift to put page number into pte. 104/* Shift to put page number into pte.
90 * 105 *
@@ -125,7 +140,7 @@ static inline struct subpage_prot_table *pgd_subpage_prot(pgd_t *pgd)
125 unsigned __split = (psize == MMU_PAGE_4K || \ 140 unsigned __split = (psize == MMU_PAGE_4K || \
126 psize == MMU_PAGE_64K_AP); \ 141 psize == MMU_PAGE_64K_AP); \
127 shift = mmu_psize_defs[psize].shift; \ 142 shift = mmu_psize_defs[psize].shift; \
128 for (index = 0; va < __end; index++, va += (1 << shift)) { \ 143 for (index = 0; va < __end; index++, va += (1L << shift)) { \
129 if (!__split || __rpte_sub_valid(rpte, index)) do { \ 144 if (!__split || __rpte_sub_valid(rpte, index)) do { \
130 145
131#define pte_iterate_hashed_end() } while(0); } } while(0) 146#define pte_iterate_hashed_end() } while(0); } } while(0)