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-rw-r--r--include/asm-powerpc/pci.h228
1 files changed, 0 insertions, 228 deletions
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
deleted file mode 100644
index a05a942b1c25..000000000000
--- a/include/asm-powerpc/pci.h
+++ /dev/null
@@ -1,228 +0,0 @@
1#ifndef __ASM_POWERPC_PCI_H
2#define __ASM_POWERPC_PCI_H
3#ifdef __KERNEL__
4
5/*
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12#include <linux/types.h>
13#include <linux/slab.h>
14#include <linux/string.h>
15#include <linux/dma-mapping.h>
16
17#include <asm/machdep.h>
18#include <asm/scatterlist.h>
19#include <asm/io.h>
20#include <asm/prom.h>
21#include <asm/pci-bridge.h>
22
23#include <asm-generic/pci-dma-compat.h>
24
25#define PCIBIOS_MIN_IO 0x1000
26#define PCIBIOS_MIN_MEM 0x10000000
27
28struct pci_dev;
29
30/* Values for the `which' argument to sys_pciconfig_iobase syscall. */
31#define IOBASE_BRIDGE_NUMBER 0
32#define IOBASE_MEMORY 1
33#define IOBASE_IO 2
34#define IOBASE_ISA_IO 3
35#define IOBASE_ISA_MEM 4
36
37/*
38 * Set this to 1 if you want the kernel to re-assign all PCI
39 * bus numbers (don't do that on ppc64 yet !)
40 */
41#define pcibios_assign_all_busses() (ppc_pci_flags & \
42 PPC_PCI_REASSIGN_ALL_BUS)
43#define pcibios_scan_all_fns(a, b) 0
44
45static inline void pcibios_set_master(struct pci_dev *dev)
46{
47 /* No special bus mastering setup handling */
48}
49
50static inline void pcibios_penalize_isa_irq(int irq, int active)
51{
52 /* We don't do dynamic PCI IRQ allocation */
53}
54
55#define HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
56static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
57{
58 if (ppc_md.pci_get_legacy_ide_irq)
59 return ppc_md.pci_get_legacy_ide_irq(dev, channel);
60 return channel ? 15 : 14;
61}
62
63#ifdef CONFIG_PPC64
64
65/*
66 * We want to avoid touching the cacheline size or MWI bit.
67 * pSeries firmware sets the cacheline size (which is not the cpu cacheline
68 * size in all cases) and hardware treats MWI the same as memory write.
69 */
70#define PCI_DISABLE_MWI
71
72#ifdef CONFIG_PCI
73extern void set_pci_dma_ops(struct dma_mapping_ops *dma_ops);
74extern struct dma_mapping_ops *get_pci_dma_ops(void);
75
76static inline void pci_dma_burst_advice(struct pci_dev *pdev,
77 enum pci_dma_burst_strategy *strat,
78 unsigned long *strategy_parameter)
79{
80 unsigned long cacheline_size;
81 u8 byte;
82
83 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &byte);
84 if (byte == 0)
85 cacheline_size = 1024;
86 else
87 cacheline_size = (int) byte * 4;
88
89 *strat = PCI_DMA_BURST_MULTIPLE;
90 *strategy_parameter = cacheline_size;
91}
92#else /* CONFIG_PCI */
93#define set_pci_dma_ops(d)
94#define get_pci_dma_ops() NULL
95#endif
96
97#else /* 32-bit */
98
99#ifdef CONFIG_PCI
100static inline void pci_dma_burst_advice(struct pci_dev *pdev,
101 enum pci_dma_burst_strategy *strat,
102 unsigned long *strategy_parameter)
103{
104 *strat = PCI_DMA_BURST_INFINITY;
105 *strategy_parameter = ~0UL;
106}
107#endif
108#endif /* CONFIG_PPC64 */
109
110extern int pci_domain_nr(struct pci_bus *bus);
111
112/* Decide whether to display the domain number in /proc */
113extern int pci_proc_domain(struct pci_bus *bus);
114
115
116struct vm_area_struct;
117/* Map a range of PCI memory or I/O space for a device into user space */
118int pci_mmap_page_range(struct pci_dev *pdev, struct vm_area_struct *vma,
119 enum pci_mmap_state mmap_state, int write_combine);
120
121/* Tell drivers/pci/proc.c that we have pci_mmap_page_range() */
122#define HAVE_PCI_MMAP 1
123
124#if defined(CONFIG_PPC64) || defined(CONFIG_NOT_COHERENT_CACHE)
125/*
126 * For 64-bit kernels, pci_unmap_{single,page} is not a nop.
127 * For 32-bit non-coherent kernels, pci_dma_sync_single_for_cpu() and
128 * so on are not nops.
129 * and thus...
130 */
131#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME) \
132 dma_addr_t ADDR_NAME;
133#define DECLARE_PCI_UNMAP_LEN(LEN_NAME) \
134 __u32 LEN_NAME;
135#define pci_unmap_addr(PTR, ADDR_NAME) \
136 ((PTR)->ADDR_NAME)
137#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) \
138 (((PTR)->ADDR_NAME) = (VAL))
139#define pci_unmap_len(PTR, LEN_NAME) \
140 ((PTR)->LEN_NAME)
141#define pci_unmap_len_set(PTR, LEN_NAME, VAL) \
142 (((PTR)->LEN_NAME) = (VAL))
143
144#else /* 32-bit && coherent */
145
146/* pci_unmap_{page,single} is a nop so... */
147#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
148#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
149#define pci_unmap_addr(PTR, ADDR_NAME) (0)
150#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
151#define pci_unmap_len(PTR, LEN_NAME) (0)
152#define pci_unmap_len_set(PTR, LEN_NAME, VAL) do { } while (0)
153
154#endif /* CONFIG_PPC64 || CONFIG_NOT_COHERENT_CACHE */
155
156#ifdef CONFIG_PPC64
157
158/* The PCI address space does not equal the physical memory address
159 * space (we have an IOMMU). The IDE and SCSI device layers use
160 * this boolean for bounce buffer decisions.
161 */
162#define PCI_DMA_BUS_IS_PHYS (0)
163
164#else /* 32-bit */
165
166/* The PCI address space does equal the physical memory
167 * address space (no IOMMU). The IDE and SCSI device layers use
168 * this boolean for bounce buffer decisions.
169 */
170#define PCI_DMA_BUS_IS_PHYS (1)
171
172#endif /* CONFIG_PPC64 */
173
174extern void pcibios_resource_to_bus(struct pci_dev *dev,
175 struct pci_bus_region *region,
176 struct resource *res);
177
178extern void pcibios_bus_to_resource(struct pci_dev *dev,
179 struct resource *res,
180 struct pci_bus_region *region);
181
182static inline struct resource *pcibios_select_root(struct pci_dev *pdev,
183 struct resource *res)
184{
185 struct resource *root = NULL;
186
187 if (res->flags & IORESOURCE_IO)
188 root = &ioport_resource;
189 if (res->flags & IORESOURCE_MEM)
190 root = &iomem_resource;
191
192 return root;
193}
194
195extern void pcibios_setup_new_device(struct pci_dev *dev);
196
197extern void pcibios_claim_one_bus(struct pci_bus *b);
198
199extern void pcibios_resource_survey(void);
200
201extern struct pci_controller *init_phb_dynamic(struct device_node *dn);
202
203extern struct pci_dev *of_create_pci_dev(struct device_node *node,
204 struct pci_bus *bus, int devfn);
205
206extern void of_scan_pci_bridge(struct device_node *node,
207 struct pci_dev *dev);
208
209extern void of_scan_bus(struct device_node *node, struct pci_bus *bus);
210
211extern int pci_read_irq_line(struct pci_dev *dev);
212
213struct file;
214extern pgprot_t pci_phys_mem_access_prot(struct file *file,
215 unsigned long pfn,
216 unsigned long size,
217 pgprot_t prot);
218
219#define HAVE_ARCH_PCI_RESOURCE_TO_USER
220extern void pci_resource_to_user(const struct pci_dev *dev, int bar,
221 const struct resource *rsrc,
222 resource_size_t *start, resource_size_t *end);
223
224extern void pcibios_do_bus_setup(struct pci_bus *bus);
225extern void pcibios_fixup_of_probed_bus(struct pci_bus *bus);
226
227#endif /* __KERNEL__ */
228#endif /* __ASM_POWERPC_PCI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-17 07:45:41 -0500