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-rw-r--r--include/asm-powerpc/pci.h20
1 files changed, 7 insertions, 13 deletions
diff --git a/include/asm-powerpc/pci.h b/include/asm-powerpc/pci.h
index 46afd29b904e..721c97f09b20 100644
--- a/include/asm-powerpc/pci.h
+++ b/include/asm-powerpc/pci.h
@@ -62,19 +62,13 @@ static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
62} 62}
63 63
64#ifdef CONFIG_PPC64 64#ifdef CONFIG_PPC64
65#define HAVE_ARCH_PCI_MWI 1 65
66static inline int pcibios_prep_mwi(struct pci_dev *dev) 66/*
67{ 67 * We want to avoid touching the cacheline size or MWI bit.
68 /* 68 * pSeries firmware sets the cacheline size (which is not the cpu cacheline
69 * We would like to avoid touching the cacheline size or MWI bit 69 * size in all cases) and hardware treats MWI the same as memory write.
70 * but we cant do that with the current pcibios_prep_mwi 70 */
71 * interface. pSeries firmware sets the cacheline size (which is not 71#define PCI_DISABLE_MWI
72 * the cpu cacheline size in all cases) and hardware treats MWI
73 * the same as memory write. So we dont touch the cacheline size
74 * here and allow the generic code to set the MWI bit.
75 */
76 return 0;
77}
78 72
79extern struct dma_mapping_ops pci_dma_ops; 73extern struct dma_mapping_ops pci_dma_ops;
80 74