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-rw-r--r--include/asm-powerpc/pci-bridge.h148
1 files changed, 121 insertions, 27 deletions
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index d9bf5aba96cb..e72c2a60853c 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -2,12 +2,91 @@
2#define _ASM_POWERPC_PCI_BRIDGE_H 2#define _ASM_POWERPC_PCI_BRIDGE_H
3#ifdef __KERNEL__ 3#ifdef __KERNEL__
4 4
5#include <linux/pci.h>
6#include <linux/list.h>
7#include <linux/ioport.h>
8
5#ifndef CONFIG_PPC64 9#ifndef CONFIG_PPC64
6#include <asm-ppc/pci-bridge.h> 10
11struct device_node;
12struct pci_controller;
13
14/*
15 * Structure of a PCI controller (host bridge)
16 */
17struct pci_controller {
18 struct pci_bus *bus;
19 char is_dynamic;
20 void *arch_data;
21 struct list_head list_node;
22 struct device *parent;
23
24 int first_busno;
25 int last_busno;
26 int self_busno;
27
28 void __iomem *io_base_virt;
29 resource_size_t io_base_phys;
30
31 /* Some machines (PReP) have a non 1:1 mapping of
32 * the PCI memory space in the CPU bus space
33 */
34 resource_size_t pci_mem_offset;
35
36 struct pci_ops *ops;
37 volatile unsigned int __iomem *cfg_addr;
38 volatile void __iomem *cfg_data;
39
40 /*
41 * Used for variants of PCI indirect handling and possible quirks:
42 * SET_CFG_TYPE - used on 4xx or any PHB that does explicit type0/1
43 * EXT_REG - provides access to PCI-e extended registers
44 * SURPRESS_PRIMARY_BUS - we surpress the setting of PCI_PRIMARY_BUS
45 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
46 * to determine which bus number to match on when generating type0
47 * config cycles
48 */
49#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
50#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
51#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
52 u32 indirect_type;
53
54 /* Currently, we limit ourselves to 1 IO range and 3 mem
55 * ranges since the common pci_bus structure can't handle more
56 */
57 struct resource io_resource;
58 struct resource mem_resources[3];
59 int global_number; /* PCI domain number */
60};
61
62static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
63{
64 return bus->sysdata;
65}
66
67/* These are used for config access before all the PCI probing
68 has been done. */
69int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
70 int where, u8 *val);
71int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
72 int where, u16 *val);
73int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
74 int where, u32 *val);
75int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
76 int where, u8 val);
77int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
78 int where, u16 val);
79int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
80 int where, u32 val);
81
82extern void setup_indirect_pci_nomap(struct pci_controller* hose,
83 void __iomem *cfg_addr, void __iomem *cfg_data);
84extern void setup_indirect_pci(struct pci_controller* hose,
85 u32 cfg_addr, u32 cfg_data);
86extern void setup_grackle(struct pci_controller *hose);
87
7#else 88#else
8 89
9#include <linux/pci.h>
10#include <linux/list.h>
11 90
12/* 91/*
13 * This program is free software; you can redistribute it and/or 92 * This program is free software; you can redistribute it and/or
@@ -31,6 +110,7 @@ struct pci_controller {
31 int last_busno; 110 int last_busno;
32 111
33 void __iomem *io_base_virt; 112 void __iomem *io_base_virt;
113 void *io_base_alloc;
34 resource_size_t io_base_phys; 114 resource_size_t io_base_phys;
35 115
36 /* Some machines have a non 1:1 mapping of 116 /* Some machines have a non 1:1 mapping of
@@ -48,8 +128,7 @@ struct pci_controller {
48 */ 128 */
49 struct resource io_resource; 129 struct resource io_resource;
50 struct resource mem_resources[3]; 130 struct resource mem_resources[3];
51 int global_number; 131 int global_number;
52 int local_number;
53 unsigned long buid; 132 unsigned long buid;
54 unsigned long dma_window_base_cur; 133 unsigned long dma_window_base_cur;
55 unsigned long dma_window_size; 134 unsigned long dma_window_size;
@@ -70,19 +149,22 @@ struct pci_dn {
70 int devfn; /* pci device and function number */ 149 int devfn; /* pci device and function number */
71 int class_code; /* pci device class */ 150 int class_code; /* pci device class */
72 151
73#ifdef CONFIG_PPC_PSERIES 152 struct pci_controller *phb; /* for pci devices */
153 struct iommu_table *iommu_table; /* for phb's or bridges */
154 struct pci_dev *pcidev; /* back-pointer to the pci device */
155 struct device_node *node; /* back-pointer to the device_node */
156
157 int pci_ext_config_space; /* for pci devices */
158
159#ifdef CONFIG_EEH
74 int eeh_mode; /* See eeh.h for possible EEH_MODEs */ 160 int eeh_mode; /* See eeh.h for possible EEH_MODEs */
75 int eeh_config_addr; 161 int eeh_config_addr;
76 int eeh_pe_config_addr; /* new-style partition endpoint address */ 162 int eeh_pe_config_addr; /* new-style partition endpoint address */
77 int eeh_check_count; /* # times driver ignored error */ 163 int eeh_check_count; /* # times driver ignored error */
78 int eeh_freeze_count; /* # times this device froze up. */ 164 int eeh_freeze_count; /* # times this device froze up. */
79#endif 165 int eeh_false_positives; /* # times this device reported #ff's */
80 int pci_ext_config_space; /* for pci devices */
81 struct pci_controller *phb; /* for pci devices */
82 struct iommu_table *iommu_table; /* for phb's or bridges */
83 struct pci_dev *pcidev; /* back-pointer to the pci device */
84 struct device_node *node; /* back-pointer to the device_node */
85 u32 config_space[16]; /* saved PCI config space */ 166 u32 config_space[16]; /* saved PCI config space */
167#endif
86}; 168};
87 169
88/* Get the pointer to a device_node's pci_dn */ 170/* Get the pointer to a device_node's pci_dn */
@@ -128,9 +210,6 @@ static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
128/** Find the bus corresponding to the indicated device node */ 210/** Find the bus corresponding to the indicated device node */
129struct pci_bus * pcibios_find_pci_bus(struct device_node *dn); 211struct pci_bus * pcibios_find_pci_bus(struct device_node *dn);
130 212
131extern void pci_process_bridge_OF_ranges(struct pci_controller *hose,
132 struct device_node *dev, int primary);
133
134/** Remove all of the PCI devices under this bus */ 213/** Remove all of the PCI devices under this bus */
135void pcibios_remove_pci_devices(struct pci_bus *bus); 214void pcibios_remove_pci_devices(struct pci_bus *bus);
136 215
@@ -148,13 +227,38 @@ static inline struct pci_controller *pci_bus_to_host(struct pci_bus *bus)
148 return PCI_DN(busdn)->phb; 227 return PCI_DN(busdn)->phb;
149} 228}
150 229
230extern void pcibios_free_controller(struct pci_controller *phb);
231
232extern void isa_bridge_find_early(struct pci_controller *hose);
233
234extern int pcibios_unmap_io_space(struct pci_bus *bus);
235extern int pcibios_map_io_space(struct pci_bus *bus);
236
237/* Return values for ppc_md.pci_probe_mode function */
238#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
239#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
240#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
241
242#ifdef CONFIG_NUMA
243#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
244#else
245#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
246#endif
247
248#endif /* CONFIG_PPC64 */
249
250/* Get the PCI host controller for an OF device */
151extern struct pci_controller* 251extern struct pci_controller*
152pci_find_hose_for_OF_device(struct device_node* node); 252pci_find_hose_for_OF_device(struct device_node* node);
153 253
254/* Fill up host controller resources from the OF node */
255extern void
256pci_process_bridge_OF_ranges(struct pci_controller *hose,
257 struct device_node *dev, int primary);
258
259/* Allocate a new PCI host bridge structure */
154extern struct pci_controller * 260extern struct pci_controller *
155pcibios_alloc_controller(struct device_node *dev); 261pcibios_alloc_controller(struct device_node *dev);
156extern void pcibios_free_controller(struct pci_controller *phb);
157
158#ifdef CONFIG_PCI 262#ifdef CONFIG_PCI
159extern unsigned long pci_address_to_pio(phys_addr_t address); 263extern unsigned long pci_address_to_pio(phys_addr_t address);
160#else 264#else
@@ -164,17 +268,7 @@ static inline unsigned long pci_address_to_pio(phys_addr_t address)
164} 268}
165#endif 269#endif
166 270
167/* Return values for ppc_md.pci_probe_mode function */
168#define PCI_PROBE_NONE -1 /* Don't look at this bus at all */
169#define PCI_PROBE_NORMAL 0 /* Do normal PCI probing */
170#define PCI_PROBE_DEVTREE 1 /* Instantiate from device tree */
171 271
172#ifdef CONFIG_NUMA
173#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = (NODE))
174#else
175#define PHB_SET_NODE(PHB, NODE) ((PHB)->node = -1)
176#endif
177 272
178#endif /* CONFIG_PPC64 */
179#endif /* __KERNEL__ */ 273#endif /* __KERNEL__ */
180#endif 274#endif