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Diffstat (limited to 'include/asm-powerpc/pci-bridge.h')
-rw-r--r--include/asm-powerpc/pci-bridge.h16
1 files changed, 13 insertions, 3 deletions
diff --git a/include/asm-powerpc/pci-bridge.h b/include/asm-powerpc/pci-bridge.h
index e72c2a60853c..d53e0eb1de16 100644
--- a/include/asm-powerpc/pci-bridge.h
+++ b/include/asm-powerpc/pci-bridge.h
@@ -45,10 +45,17 @@ struct pci_controller {
45 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS 45 * on Freescale PCI-e controllers since they used the PCI_PRIMARY_BUS
46 * to determine which bus number to match on when generating type0 46 * to determine which bus number to match on when generating type0
47 * config cycles 47 * config cycles
48 * NO_PCIE_LINK - the Freescale PCI-e controllers have issues with
49 * hanging if we don't have link and try to do config cycles to
50 * anything but the PHB. Only allow talking to the PHB if this is
51 * set.
52 * BIG_ENDIAN - cfg_addr is a big endian register
48 */ 53 */
49#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001) 54#define PPC_INDIRECT_TYPE_SET_CFG_TYPE (0x00000001)
50#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002) 55#define PPC_INDIRECT_TYPE_EXT_REG (0x00000002)
51#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004) 56#define PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS (0x00000004)
57#define PPC_INDIRECT_TYPE_NO_PCIE_LINK (0x00000008)
58#define PPC_INDIRECT_TYPE_BIG_ENDIAN (0x00000010)
52 u32 indirect_type; 59 u32 indirect_type;
53 60
54 /* Currently, we limit ourselves to 1 IO range and 3 mem 61 /* Currently, we limit ourselves to 1 IO range and 3 mem
@@ -79,11 +86,14 @@ int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
79int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, 86int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
80 int where, u32 val); 87 int where, u32 val);
81 88
82extern void setup_indirect_pci_nomap(struct pci_controller* hose, 89extern int early_find_capability(struct pci_controller *hose, int bus,
83 void __iomem *cfg_addr, void __iomem *cfg_data); 90 int dev_fn, int cap);
91
84extern void setup_indirect_pci(struct pci_controller* hose, 92extern void setup_indirect_pci(struct pci_controller* hose,
85 u32 cfg_addr, u32 cfg_data); 93 u32 cfg_addr, u32 cfg_data, u32 flags);
86extern void setup_grackle(struct pci_controller *hose); 94extern void setup_grackle(struct pci_controller *hose);
95extern void __init update_bridge_resource(struct pci_dev *dev,
96 struct resource *res);
87 97
88#else 98#else
89 99