diff options
Diffstat (limited to 'include/asm-powerpc/mpic.h')
-rw-r--r-- | include/asm-powerpc/mpic.h | 67 |
1 files changed, 32 insertions, 35 deletions
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h index f0d22ac34b96..eb241c99c457 100644 --- a/include/asm-powerpc/mpic.h +++ b/include/asm-powerpc/mpic.h | |||
@@ -114,9 +114,6 @@ | |||
114 | #define MPIC_VEC_TIMER_1 248 | 114 | #define MPIC_VEC_TIMER_1 248 |
115 | #define MPIC_VEC_TIMER_0 247 | 115 | #define MPIC_VEC_TIMER_0 247 |
116 | 116 | ||
117 | /* Type definition of the cascade handler */ | ||
118 | typedef int (*mpic_cascade_t)(struct pt_regs *regs, void *data); | ||
119 | |||
120 | #ifdef CONFIG_MPIC_BROKEN_U3 | 117 | #ifdef CONFIG_MPIC_BROKEN_U3 |
121 | /* Fixup table entry */ | 118 | /* Fixup table entry */ |
122 | struct mpic_irq_fixup | 119 | struct mpic_irq_fixup |
@@ -132,10 +129,19 @@ struct mpic_irq_fixup | |||
132 | /* The instance data of a given MPIC */ | 129 | /* The instance data of a given MPIC */ |
133 | struct mpic | 130 | struct mpic |
134 | { | 131 | { |
132 | /* The device node of the interrupt controller */ | ||
133 | struct device_node *of_node; | ||
134 | |||
135 | /* The remapper for this MPIC */ | ||
136 | struct irq_host *irqhost; | ||
137 | |||
135 | /* The "linux" controller struct */ | 138 | /* The "linux" controller struct */ |
136 | hw_irq_controller hc_irq; | 139 | struct irq_chip hc_irq; |
140 | #ifdef CONFIG_MPIC_BROKEN_U3 | ||
141 | struct irq_chip hc_ht_irq; | ||
142 | #endif | ||
137 | #ifdef CONFIG_SMP | 143 | #ifdef CONFIG_SMP |
138 | hw_irq_controller hc_ipi; | 144 | struct irq_chip hc_ipi; |
139 | #endif | 145 | #endif |
140 | const char *name; | 146 | const char *name; |
141 | /* Flags */ | 147 | /* Flags */ |
@@ -144,20 +150,12 @@ struct mpic | |||
144 | unsigned int isu_size; | 150 | unsigned int isu_size; |
145 | unsigned int isu_shift; | 151 | unsigned int isu_shift; |
146 | unsigned int isu_mask; | 152 | unsigned int isu_mask; |
147 | /* Offset of irq vector numbers */ | ||
148 | unsigned int irq_offset; | ||
149 | unsigned int irq_count; | 153 | unsigned int irq_count; |
150 | /* Offset of ipi vector numbers */ | ||
151 | unsigned int ipi_offset; | ||
152 | /* Number of sources */ | 154 | /* Number of sources */ |
153 | unsigned int num_sources; | 155 | unsigned int num_sources; |
154 | /* Number of CPUs */ | 156 | /* Number of CPUs */ |
155 | unsigned int num_cpus; | 157 | unsigned int num_cpus; |
156 | /* cascade handler */ | 158 | /* default senses array */ |
157 | mpic_cascade_t cascade; | ||
158 | void *cascade_data; | ||
159 | unsigned int cascade_vec; | ||
160 | /* senses array */ | ||
161 | unsigned char *senses; | 159 | unsigned char *senses; |
162 | unsigned int senses_count; | 160 | unsigned int senses_count; |
163 | 161 | ||
@@ -213,14 +211,11 @@ struct mpic | |||
213 | * The values in the array start at the first source of the MPIC, | 211 | * The values in the array start at the first source of the MPIC, |
214 | * that is senses[0] correspond to linux irq "irq_offset". | 212 | * that is senses[0] correspond to linux irq "irq_offset". |
215 | */ | 213 | */ |
216 | extern struct mpic *mpic_alloc(unsigned long phys_addr, | 214 | extern struct mpic *mpic_alloc(struct device_node *node, |
215 | unsigned long phys_addr, | ||
217 | unsigned int flags, | 216 | unsigned int flags, |
218 | unsigned int isu_size, | 217 | unsigned int isu_size, |
219 | unsigned int irq_offset, | ||
220 | unsigned int irq_count, | 218 | unsigned int irq_count, |
221 | unsigned int ipi_offset, | ||
222 | unsigned char *senses, | ||
223 | unsigned int senses_num, | ||
224 | const char *name); | 219 | const char *name); |
225 | 220 | ||
226 | /* Assign ISUs, to call before mpic_init() | 221 | /* Assign ISUs, to call before mpic_init() |
@@ -232,22 +227,27 @@ extern struct mpic *mpic_alloc(unsigned long phys_addr, | |||
232 | extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, | 227 | extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num, |
233 | unsigned long phys_addr); | 228 | unsigned long phys_addr); |
234 | 229 | ||
230 | /* Set default sense codes | ||
231 | * | ||
232 | * @mpic: controller | ||
233 | * @senses: array of sense codes | ||
234 | * @count: size of above array | ||
235 | * | ||
236 | * Optionally provide an array (indexed on hardware interrupt numbers | ||
237 | * for this MPIC) of default sense codes for the chip. Those are linux | ||
238 | * sense codes IRQ_TYPE_* | ||
239 | * | ||
240 | * The driver gets ownership of the pointer, don't dispose of it or | ||
241 | * anything like that. __init only. | ||
242 | */ | ||
243 | extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count); | ||
244 | |||
245 | |||
235 | /* Initialize the controller. After this has been called, none of the above | 246 | /* Initialize the controller. After this has been called, none of the above |
236 | * should be called again for this mpic | 247 | * should be called again for this mpic |
237 | */ | 248 | */ |
238 | extern void mpic_init(struct mpic *mpic); | 249 | extern void mpic_init(struct mpic *mpic); |
239 | 250 | ||
240 | /* Setup a cascade. Currently, only one cascade is supported this | ||
241 | * way, though you can always do a normal request_irq() and add | ||
242 | * other cascades this way. You should call this _after_ having | ||
243 | * added all the ISUs | ||
244 | * | ||
245 | * @irq_no: "linux" irq number of the cascade (that is offset'ed vector) | ||
246 | * @handler: cascade handler function | ||
247 | */ | ||
248 | extern void mpic_setup_cascade(unsigned int irq_no, mpic_cascade_t hanlder, | ||
249 | void *data); | ||
250 | |||
251 | /* | 251 | /* |
252 | * All of the following functions must only be used after the | 252 | * All of the following functions must only be used after the |
253 | * ISUs have been assigned and the controller fully initialized | 253 | * ISUs have been assigned and the controller fully initialized |
@@ -284,9 +284,9 @@ extern void mpic_send_ipi(unsigned int ipi_no, unsigned int cpu_mask); | |||
284 | void smp_mpic_message_pass(int target, int msg); | 284 | void smp_mpic_message_pass(int target, int msg); |
285 | 285 | ||
286 | /* Fetch interrupt from a given mpic */ | 286 | /* Fetch interrupt from a given mpic */ |
287 | extern int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs); | 287 | extern unsigned int mpic_get_one_irq(struct mpic *mpic, struct pt_regs *regs); |
288 | /* This one gets to the primary mpic */ | 288 | /* This one gets to the primary mpic */ |
289 | extern int mpic_get_irq(struct pt_regs *regs); | 289 | extern unsigned int mpic_get_irq(struct pt_regs *regs); |
290 | 290 | ||
291 | /* Set the EPIC clock ratio */ | 291 | /* Set the EPIC clock ratio */ |
292 | void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); | 292 | void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); |
@@ -294,8 +294,5 @@ void mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio); | |||
294 | /* Enable/Disable EPIC serial interrupt mode */ | 294 | /* Enable/Disable EPIC serial interrupt mode */ |
295 | void mpic_set_serial_int(struct mpic *mpic, int enable); | 295 | void mpic_set_serial_int(struct mpic *mpic, int enable); |
296 | 296 | ||
297 | /* global mpic for pSeries */ | ||
298 | extern struct mpic *pSeries_mpic; | ||
299 | |||
300 | #endif /* __KERNEL__ */ | 297 | #endif /* __KERNEL__ */ |
301 | #endif /* _ASM_POWERPC_MPIC_H */ | 298 | #endif /* _ASM_POWERPC_MPIC_H */ |