1 files changed, 16 insertions, 0 deletions

diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index 31f721994bd8..3a5ebe229af5 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -96,6 +96,8 @@ extern char initial_stab[];
 #define HPTE_R_FLAGS            ASM_CONST(0x00000000000003ff)
 #define HPTE_R_PP               ASM_CONST(0x0000000000000003)
 #define HPTE_R_N                ASM_CONST(0x0000000000000004)
+#define HPTE_R_C                ASM_CONST(0x0000000000000080)
+#define HPTE_R_R                ASM_CONST(0x0000000000000100)
 
 /* Values for PP (assumes Ks=0, Kp=1) */
 /* pp0 will always be 0 for linux     */
@@ -163,6 +165,16 @@ struct mmu_psize_def
 extern struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT];
 extern int mmu_linear_psize;
 extern int mmu_virtual_psize;
+extern int mmu_vmalloc_psize;
+extern int mmu_io_psize;
+
+/*
+ * If the processor supports 64k normal pages but not 64k cache
+ * inhibited pages, we have to be prepared to switch processes
+ * to use 4k pages when they create cache-inhibited mappings.
+ * If this is the case, mmu_ci_restrictions will be set to 1.
+ */
+extern int mmu_ci_restrictions;
 
 #ifdef CONFIG_HUGETLB_PAGE
 /*
@@ -254,6 +266,7 @@ extern long iSeries_hpte_insert(unsigned long hpte_group,
 
 extern void stabs_alloc(void);
 extern void slb_initialize(void);
+extern void slb_flush_and_rebolt(void);
 extern void stab_initialize(unsigned long stab);
 
 #endif /* __ASSEMBLY__ */
@@ -357,9 +370,12 @@ typedef unsigned long mm_context_id_t;
 
 typedef struct {
         mm_context_id_t id;
+        u16 user_psize;                 /* page size index */
+        u16 sllp;                       /* SLB entry page size encoding */
 #ifdef CONFIG_HUGETLB_PAGE
         u16 low_htlb_areas, high_htlb_areas;
 #endif
+        unsigned long vdso_base;
 } mm_context_t;