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-rw-r--r--include/asm-powerpc/mmu-hash32.h28
1 files changed, 11 insertions, 17 deletions
diff --git a/include/asm-powerpc/mmu-hash32.h b/include/asm-powerpc/mmu-hash32.h
index 6e21ca618ec3..16b1a1e77e64 100644
--- a/include/asm-powerpc/mmu-hash32.h
+++ b/include/asm-powerpc/mmu-hash32.h
@@ -28,24 +28,18 @@
28#define BPP_RW 0x02 /* Read/write */ 28#define BPP_RW 0x02 /* Read/write */
29 29
30#ifndef __ASSEMBLY__ 30#ifndef __ASSEMBLY__
31/* Contort a phys_addr_t into the right format/bits for a BAT */
32#ifdef CONFIG_PHYS_64BIT
33#define BAT_PHYS_ADDR(x) ((u32)((x & 0x00000000fffe0000ULL) | \
34 ((x & 0x0000000e00000000ULL) >> 24) | \
35 ((x & 0x0000000100000000ULL) >> 30)))
36#else
37#define BAT_PHYS_ADDR(x) (x)
38#endif
39
31struct ppc_bat { 40struct ppc_bat {
32 struct { 41 u32 batu;
33 unsigned long bepi:15; /* Effective page index (virtual address) */ 42 u32 batl;
34 unsigned long :4; /* Unused */
35 unsigned long bl:11; /* Block size mask */
36 unsigned long vs:1; /* Supervisor valid */
37 unsigned long vp:1; /* User valid */
38 } batu; /* Upper register */
39 struct {
40 unsigned long brpn:15; /* Real page index (physical address) */
41 unsigned long :10; /* Unused */
42 unsigned long w:1; /* Write-thru cache */
43 unsigned long i:1; /* Cache inhibit */
44 unsigned long m:1; /* Memory coherence */
45 unsigned long g:1; /* Guarded (MBZ in IBAT) */
46 unsigned long :1; /* Unused */
47 unsigned long pp:2; /* Page access protections */
48 } batl; /* Lower register */
49}; 43};
50#endif /* !__ASSEMBLY__ */ 44#endif /* !__ASSEMBLY__ */
51 45