diff options
Diffstat (limited to 'include/asm-powerpc/irq.h')
| -rw-r--r-- | include/asm-powerpc/irq.h | 121 |
1 files changed, 0 insertions, 121 deletions
diff --git a/include/asm-powerpc/irq.h b/include/asm-powerpc/irq.h index 4a015da9fb1e..0efe7b24b633 100644 --- a/include/asm-powerpc/irq.h +++ b/include/asm-powerpc/irq.h | |||
| @@ -483,127 +483,6 @@ static __inline__ int irq_canonicalize(int irq) | |||
| 483 | */ | 483 | */ |
| 484 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) | 484 | #define mk_int_int_mask(IL) (1 << (7 - (IL/2))) |
| 485 | 485 | ||
| 486 | #elif defined(CONFIG_85xx) | ||
| 487 | /* Now include the board configuration specific associations. | ||
| 488 | */ | ||
| 489 | #include <asm/mpc85xx.h> | ||
| 490 | |||
| 491 | /* The MPC8548 openpic has 48 internal interrupts and 12 external | ||
| 492 | * interrupts. | ||
| 493 | * | ||
| 494 | * We are "flattening" the interrupt vectors of the cascaded CPM | ||
| 495 | * so that we can uniquely identify any interrupt source with a | ||
| 496 | * single integer. | ||
| 497 | */ | ||
| 498 | #define NR_CPM_INTS 64 | ||
| 499 | #define NR_EPIC_INTS 60 | ||
| 500 | #ifndef NR_8259_INTS | ||
| 501 | #define NR_8259_INTS 0 | ||
| 502 | #endif | ||
| 503 | #define NUM_8259_INTERRUPTS NR_8259_INTS | ||
| 504 | |||
| 505 | #ifndef CPM_IRQ_OFFSET | ||
| 506 | #define CPM_IRQ_OFFSET 0 | ||
| 507 | #endif | ||
| 508 | |||
| 509 | #define NR_IRQS (NR_EPIC_INTS + NR_CPM_INTS + NR_8259_INTS) | ||
| 510 | |||
| 511 | /* Internal IRQs on MPC85xx OpenPIC */ | ||
| 512 | |||
| 513 | #ifndef MPC85xx_OPENPIC_IRQ_OFFSET | ||
| 514 | #ifdef CONFIG_CPM2 | ||
| 515 | #define MPC85xx_OPENPIC_IRQ_OFFSET (CPM_IRQ_OFFSET + NR_CPM_INTS) | ||
| 516 | #else | ||
| 517 | #define MPC85xx_OPENPIC_IRQ_OFFSET 0 | ||
| 518 | #endif | ||
| 519 | #endif | ||
| 520 | |||
| 521 | /* Not all of these exist on all MPC85xx implementations */ | ||
| 522 | #define MPC85xx_IRQ_L2CACHE ( 0 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 523 | #define MPC85xx_IRQ_ECM ( 1 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 524 | #define MPC85xx_IRQ_DDR ( 2 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 525 | #define MPC85xx_IRQ_LBIU ( 3 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 526 | #define MPC85xx_IRQ_DMA0 ( 4 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 527 | #define MPC85xx_IRQ_DMA1 ( 5 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 528 | #define MPC85xx_IRQ_DMA2 ( 6 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 529 | #define MPC85xx_IRQ_DMA3 ( 7 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 530 | #define MPC85xx_IRQ_PCI1 ( 8 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 531 | #define MPC85xx_IRQ_PCI2 ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 532 | #define MPC85xx_IRQ_RIO_ERROR ( 9 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 533 | #define MPC85xx_IRQ_RIO_BELL (10 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 534 | #define MPC85xx_IRQ_RIO_TX (11 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 535 | #define MPC85xx_IRQ_RIO_RX (12 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 536 | #define MPC85xx_IRQ_TSEC1_TX (13 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 537 | #define MPC85xx_IRQ_TSEC1_RX (14 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 538 | #define MPC85xx_IRQ_TSEC3_TX (15 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 539 | #define MPC85xx_IRQ_TSEC3_RX (16 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 540 | #define MPC85xx_IRQ_TSEC3_ERROR (17 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 541 | #define MPC85xx_IRQ_TSEC1_ERROR (18 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 542 | #define MPC85xx_IRQ_TSEC2_TX (19 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 543 | #define MPC85xx_IRQ_TSEC2_RX (20 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 544 | #define MPC85xx_IRQ_TSEC4_TX (21 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 545 | #define MPC85xx_IRQ_TSEC4_RX (22 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 546 | #define MPC85xx_IRQ_TSEC4_ERROR (23 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 547 | #define MPC85xx_IRQ_TSEC2_ERROR (24 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 548 | #define MPC85xx_IRQ_FEC (25 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 549 | #define MPC85xx_IRQ_DUART (26 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 550 | #define MPC85xx_IRQ_IIC1 (27 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 551 | #define MPC85xx_IRQ_PERFMON (28 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 552 | #define MPC85xx_IRQ_SEC2 (29 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 553 | #define MPC85xx_IRQ_CPM (30 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 554 | |||
| 555 | /* The 12 external interrupt lines */ | ||
| 556 | #define MPC85xx_IRQ_EXT0 (48 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 557 | #define MPC85xx_IRQ_EXT1 (49 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 558 | #define MPC85xx_IRQ_EXT2 (50 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 559 | #define MPC85xx_IRQ_EXT3 (51 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 560 | #define MPC85xx_IRQ_EXT4 (52 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 561 | #define MPC85xx_IRQ_EXT5 (53 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 562 | #define MPC85xx_IRQ_EXT6 (54 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 563 | #define MPC85xx_IRQ_EXT7 (55 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 564 | #define MPC85xx_IRQ_EXT8 (56 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 565 | #define MPC85xx_IRQ_EXT9 (57 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 566 | #define MPC85xx_IRQ_EXT10 (58 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 567 | #define MPC85xx_IRQ_EXT11 (59 + MPC85xx_OPENPIC_IRQ_OFFSET) | ||
| 568 | |||
| 569 | /* CPM related interrupts */ | ||
| 570 | #define SIU_INT_ERROR ((uint)0x00+CPM_IRQ_OFFSET) | ||
| 571 | #define SIU_INT_I2C ((uint)0x01+CPM_IRQ_OFFSET) | ||
| 572 | #define SIU_INT_SPI ((uint)0x02+CPM_IRQ_OFFSET) | ||
| 573 | #define SIU_INT_RISC ((uint)0x03+CPM_IRQ_OFFSET) | ||
| 574 | #define SIU_INT_SMC1 ((uint)0x04+CPM_IRQ_OFFSET) | ||
| 575 | #define SIU_INT_SMC2 ((uint)0x05+CPM_IRQ_OFFSET) | ||
| 576 | #define SIU_INT_USB ((uint)0x0b+CPM_IRQ_OFFSET) | ||
| 577 | #define SIU_INT_TIMER1 ((uint)0x0c+CPM_IRQ_OFFSET) | ||
| 578 | #define SIU_INT_TIMER2 ((uint)0x0d+CPM_IRQ_OFFSET) | ||
| 579 | #define SIU_INT_TIMER3 ((uint)0x0e+CPM_IRQ_OFFSET) | ||
| 580 | #define SIU_INT_TIMER4 ((uint)0x0f+CPM_IRQ_OFFSET) | ||
| 581 | #define SIU_INT_FCC1 ((uint)0x20+CPM_IRQ_OFFSET) | ||
| 582 | #define SIU_INT_FCC2 ((uint)0x21+CPM_IRQ_OFFSET) | ||
| 583 | #define SIU_INT_FCC3 ((uint)0x22+CPM_IRQ_OFFSET) | ||
| 584 | #define SIU_INT_MCC1 ((uint)0x24+CPM_IRQ_OFFSET) | ||
| 585 | #define SIU_INT_MCC2 ((uint)0x25+CPM_IRQ_OFFSET) | ||
| 586 | #define SIU_INT_SCC1 ((uint)0x28+CPM_IRQ_OFFSET) | ||
| 587 | #define SIU_INT_SCC2 ((uint)0x29+CPM_IRQ_OFFSET) | ||
| 588 | #define SIU_INT_SCC3 ((uint)0x2a+CPM_IRQ_OFFSET) | ||
| 589 | #define SIU_INT_SCC4 ((uint)0x2b+CPM_IRQ_OFFSET) | ||
| 590 | #define SIU_INT_PC15 ((uint)0x30+CPM_IRQ_OFFSET) | ||
| 591 | #define SIU_INT_PC14 ((uint)0x31+CPM_IRQ_OFFSET) | ||
| 592 | #define SIU_INT_PC13 ((uint)0x32+CPM_IRQ_OFFSET) | ||
| 593 | #define SIU_INT_PC12 ((uint)0x33+CPM_IRQ_OFFSET) | ||
| 594 | #define SIU_INT_PC11 ((uint)0x34+CPM_IRQ_OFFSET) | ||
| 595 | #define SIU_INT_PC10 ((uint)0x35+CPM_IRQ_OFFSET) | ||
| 596 | #define SIU_INT_PC9 ((uint)0x36+CPM_IRQ_OFFSET) | ||
| 597 | #define SIU_INT_PC8 ((uint)0x37+CPM_IRQ_OFFSET) | ||
| 598 | #define SIU_INT_PC7 ((uint)0x38+CPM_IRQ_OFFSET) | ||
| 599 | #define SIU_INT_PC6 ((uint)0x39+CPM_IRQ_OFFSET) | ||
| 600 | #define SIU_INT_PC5 ((uint)0x3a+CPM_IRQ_OFFSET) | ||
| 601 | #define SIU_INT_PC4 ((uint)0x3b+CPM_IRQ_OFFSET) | ||
| 602 | #define SIU_INT_PC3 ((uint)0x3c+CPM_IRQ_OFFSET) | ||
| 603 | #define SIU_INT_PC2 ((uint)0x3d+CPM_IRQ_OFFSET) | ||
| 604 | #define SIU_INT_PC1 ((uint)0x3e+CPM_IRQ_OFFSET) | ||
| 605 | #define SIU_INT_PC0 ((uint)0x3f+CPM_IRQ_OFFSET) | ||
| 606 | |||
| 607 | #elif defined(CONFIG_PPC_86xx) | 486 | #elif defined(CONFIG_PPC_86xx) |
| 608 | #include <asm/mpc86xx.h> | 487 | #include <asm/mpc86xx.h> |
| 609 | 488 | ||