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-rw-r--r--include/asm-powerpc/io.h845
1 files changed, 576 insertions, 269 deletions
diff --git a/include/asm-powerpc/io.h b/include/asm-powerpc/io.h
index c2c5f14b5f5f..1cd532379c30 100644
--- a/include/asm-powerpc/io.h
+++ b/include/asm-powerpc/io.h
@@ -13,154 +13,530 @@
13extern int check_legacy_ioport(unsigned long base_port); 13extern int check_legacy_ioport(unsigned long base_port);
14#define PNPBIOS_BASE 0xf000 /* only relevant for PReP */ 14#define PNPBIOS_BASE 0xf000 /* only relevant for PReP */
15 15
16#ifndef CONFIG_PPC64
17#include <asm-ppc/io.h>
18#else
19
20#include <linux/compiler.h> 16#include <linux/compiler.h>
21#include <asm/page.h> 17#include <asm/page.h>
22#include <asm/byteorder.h> 18#include <asm/byteorder.h>
23#include <asm/paca.h>
24#include <asm/synch.h> 19#include <asm/synch.h>
25#include <asm/delay.h> 20#include <asm/delay.h>
21#include <asm/mmu.h>
26 22
27#include <asm-generic/iomap.h> 23#include <asm-generic/iomap.h>
28 24
25#ifdef CONFIG_PPC64
26#include <asm/paca.h>
27#endif
28
29#define SIO_CONFIG_RA 0x398 29#define SIO_CONFIG_RA 0x398
30#define SIO_CONFIG_RD 0x399 30#define SIO_CONFIG_RD 0x399
31 31
32#define SLOW_DOWN_IO 32#define SLOW_DOWN_IO
33 33
34/* 32 bits uses slightly different variables for the various IO
35 * bases. Most of this file only uses _IO_BASE though which we
36 * define properly based on the platform
37 */
38#ifndef CONFIG_PCI
39#define _IO_BASE 0
40#define _ISA_MEM_BASE 0
41#define PCI_DRAM_OFFSET 0
42#elif defined(CONFIG_PPC32)
43#define _IO_BASE isa_io_base
44#define _ISA_MEM_BASE isa_mem_base
45#define PCI_DRAM_OFFSET pci_dram_offset
46#else
47#define _IO_BASE pci_io_base
48#define _ISA_MEM_BASE 0
49#define PCI_DRAM_OFFSET 0
50#endif
51
34extern unsigned long isa_io_base; 52extern unsigned long isa_io_base;
53extern unsigned long isa_mem_base;
35extern unsigned long pci_io_base; 54extern unsigned long pci_io_base;
55extern unsigned long pci_dram_offset;
56
57#if defined(CONFIG_PPC32) && defined(CONFIG_PPC_INDIRECT_IO)
58#error CONFIG_PPC_INDIRECT_IO is not yet supported on 32 bits
59#endif
60
61/*
62 *
63 * Low level MMIO accessors
64 *
65 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
66 * specific and thus shouldn't be used in generic code. The accessors
67 * provided here are:
68 *
69 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
70 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
71 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
72 *
73 * Those operate directly on a kernel virtual address. Note that the prototype
74 * for the out_* accessors has the arguments in opposite order from the usual
75 * linux PCI accessors. Unlike those, they take the address first and the value
76 * next.
77 *
78 * Note: I might drop the _ns suffix on the stream operations soon as it is
79 * simply normal for stream operations to not swap in the first place.
80 *
81 */
82
83#ifdef CONFIG_PPC64
84#define IO_SET_SYNC_FLAG() do { get_paca()->io_sync = 1; } while(0)
85#else
86#define IO_SET_SYNC_FLAG()
87#endif
88
89#define DEF_MMIO_IN(name, type, insn) \
90static inline type name(const volatile type __iomem *addr) \
91{ \
92 type ret; \
93 __asm__ __volatile__("sync;" insn ";twi 0,%0,0;isync" \
94 : "=r" (ret) : "r" (addr), "m" (*addr)); \
95 return ret; \
96}
97
98#define DEF_MMIO_OUT(name, type, insn) \
99static inline void name(volatile type __iomem *addr, type val) \
100{ \
101 __asm__ __volatile__("sync;" insn \
102 : "=m" (*addr) : "r" (val), "r" (addr)); \
103 IO_SET_SYNC_FLAG(); \
104}
105
106
107#define DEF_MMIO_IN_BE(name, size, insn) \
108 DEF_MMIO_IN(name, u##size, __stringify(insn)"%U2%X2 %0,%2")
109#define DEF_MMIO_IN_LE(name, size, insn) \
110 DEF_MMIO_IN(name, u##size, __stringify(insn)" %0,0,%1")
111
112#define DEF_MMIO_OUT_BE(name, size, insn) \
113 DEF_MMIO_OUT(name, u##size, __stringify(insn)"%U0%X0 %1,%0")
114#define DEF_MMIO_OUT_LE(name, size, insn) \
115 DEF_MMIO_OUT(name, u##size, __stringify(insn)" %1,0,%2")
116
117DEF_MMIO_IN_BE(in_8, 8, lbz);
118DEF_MMIO_IN_BE(in_be16, 16, lhz);
119DEF_MMIO_IN_BE(in_be32, 32, lwz);
120DEF_MMIO_IN_LE(in_le16, 16, lhbrx);
121DEF_MMIO_IN_LE(in_le32, 32, lwbrx);
122
123DEF_MMIO_OUT_BE(out_8, 8, stb);
124DEF_MMIO_OUT_BE(out_be16, 16, sth);
125DEF_MMIO_OUT_BE(out_be32, 32, stw);
126DEF_MMIO_OUT_LE(out_le16, 16, sthbrx);
127DEF_MMIO_OUT_LE(out_le32, 32, stwbrx);
128
129#ifdef __powerpc64__
130DEF_MMIO_OUT_BE(out_be64, 64, std);
131DEF_MMIO_IN_BE(in_be64, 64, ld);
132
133/* There is no asm instructions for 64 bits reverse loads and stores */
134static inline u64 in_le64(const volatile u64 __iomem *addr)
135{
136 return le64_to_cpu(in_be64(addr));
137}
138
139static inline void out_le64(volatile u64 __iomem *addr, u64 val)
140{
141 out_be64(addr, cpu_to_le64(val));
142}
143#endif /* __powerpc64__ */
144
145/*
146 * Low level IO stream instructions are defined out of line for now
147 */
148extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
149extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
150extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
151extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
152extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
153extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
154
155/* The _ns naming is historical and will be removed. For now, just #define
156 * the non _ns equivalent names
157 */
158#define _insw _insw_ns
159#define _insl _insl_ns
160#define _outsw _outsw_ns
161#define _outsl _outsl_ns
162
163
164/*
165 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
166 */
167
168extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
169extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
170 unsigned long n);
171extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
172 unsigned long n);
173
174/*
175 *
176 * PCI and standard ISA accessors
177 *
178 * Those are globally defined linux accessors for devices on PCI or ISA
179 * busses. They follow the Linux defined semantics. The current implementation
180 * for PowerPC is as close as possible to the x86 version of these, and thus
181 * provides fairly heavy weight barriers for the non-raw versions
182 *
183 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_IO
184 * allowing the platform to provide its own implementation of some or all
185 * of the accessors.
186 */
187
188/*
189 * Include the EEH definitions when EEH is enabled only so they don't get
190 * in the way when building for 32 bits
191 */
192#ifdef CONFIG_EEH
193#include <asm/eeh.h>
194#endif
195
196/* Shortcut to the MMIO argument pointer */
197#define PCI_IO_ADDR volatile void __iomem *
198
199/* Indirect IO address tokens:
200 *
201 * When CONFIG_PPC_INDIRECT_IO is set, the platform can provide hooks
202 * on all IOs. (Note that this is all 64 bits only for now)
203 *
204 * To help platforms who may need to differenciate MMIO addresses in
205 * their hooks, a bitfield is reserved for use by the platform near the
206 * top of MMIO addresses (not PIO, those have to cope the hard way).
207 *
208 * This bit field is 12 bits and is at the top of the IO virtual
209 * addresses PCI_IO_INDIRECT_TOKEN_MASK.
210 *
211 * The kernel virtual space is thus:
212 *
213 * 0xD000000000000000 : vmalloc
214 * 0xD000080000000000 : PCI PHB IO space
215 * 0xD000080080000000 : ioremap
216 * 0xD0000fffffffffff : end of ioremap region
217 *
218 * Since the top 4 bits are reserved as the region ID, we use thus
219 * the next 12 bits and keep 4 bits available for the future if the
220 * virtual address space is ever to be extended.
221 *
222 * The direct IO mapping operations will then mask off those bits
223 * before doing the actual access, though that only happen when
224 * CONFIG_PPC_INDIRECT_IO is set, thus be careful when you use that
225 * mechanism
226 */
227
228#ifdef CONFIG_PPC_INDIRECT_IO
229#define PCI_IO_IND_TOKEN_MASK 0x0fff000000000000ul
230#define PCI_IO_IND_TOKEN_SHIFT 48
231#define PCI_FIX_ADDR(addr) \
232 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
233#define PCI_GET_ADDR_TOKEN(addr) \
234 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
235 PCI_IO_IND_TOKEN_SHIFT)
236#define PCI_SET_ADDR_TOKEN(addr, token) \
237do { \
238 unsigned long __a = (unsigned long)(addr); \
239 __a &= ~PCI_IO_IND_TOKEN_MASK; \
240 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
241 (addr) = (void __iomem *)__a; \
242} while(0)
243#else
244#define PCI_FIX_ADDR(addr) (addr)
245#endif
36 246
37#ifdef CONFIG_PPC_ISERIES 247
38 248/*
39extern int in_8(const volatile unsigned char __iomem *addr); 249 * Non ordered and non-swapping "raw" accessors
40extern void out_8(volatile unsigned char __iomem *addr, int val); 250 */
41extern int in_le16(const volatile unsigned short __iomem *addr);
42extern int in_be16(const volatile unsigned short __iomem *addr);
43extern void out_le16(volatile unsigned short __iomem *addr, int val);
44extern void out_be16(volatile unsigned short __iomem *addr, int val);
45extern unsigned in_le32(const volatile unsigned __iomem *addr);
46extern unsigned in_be32(const volatile unsigned __iomem *addr);
47extern void out_le32(volatile unsigned __iomem *addr, int val);
48extern void out_be32(volatile unsigned __iomem *addr, int val);
49extern unsigned long in_le64(const volatile unsigned long __iomem *addr);
50extern unsigned long in_be64(const volatile unsigned long __iomem *addr);
51extern void out_le64(volatile unsigned long __iomem *addr, unsigned long val);
52extern void out_be64(volatile unsigned long __iomem *addr, unsigned long val);
53
54extern unsigned char __raw_readb(const volatile void __iomem *addr);
55extern unsigned short __raw_readw(const volatile void __iomem *addr);
56extern unsigned int __raw_readl(const volatile void __iomem *addr);
57extern unsigned long __raw_readq(const volatile void __iomem *addr);
58extern void __raw_writeb(unsigned char v, volatile void __iomem *addr);
59extern void __raw_writew(unsigned short v, volatile void __iomem *addr);
60extern void __raw_writel(unsigned int v, volatile void __iomem *addr);
61extern void __raw_writeq(unsigned long v, volatile void __iomem *addr);
62
63extern void memset_io(volatile void __iomem *addr, int c, unsigned long n);
64extern void memcpy_fromio(void *dest, const volatile void __iomem *src,
65 unsigned long n);
66extern void memcpy_toio(volatile void __iomem *dest, const void *src,
67 unsigned long n);
68
69#else /* CONFIG_PPC_ISERIES */
70
71#define in_8(addr) __in_8((addr))
72#define out_8(addr, val) __out_8((addr), (val))
73#define in_le16(addr) __in_le16((addr))
74#define in_be16(addr) __in_be16((addr))
75#define out_le16(addr, val) __out_le16((addr), (val))
76#define out_be16(addr, val) __out_be16((addr), (val))
77#define in_le32(addr) __in_le32((addr))
78#define in_be32(addr) __in_be32((addr))
79#define out_le32(addr, val) __out_le32((addr), (val))
80#define out_be32(addr, val) __out_be32((addr), (val))
81#define in_le64(addr) __in_le64((addr))
82#define in_be64(addr) __in_be64((addr))
83#define out_le64(addr, val) __out_le64((addr), (val))
84#define out_be64(addr, val) __out_be64((addr), (val))
85 251
86static inline unsigned char __raw_readb(const volatile void __iomem *addr) 252static inline unsigned char __raw_readb(const volatile void __iomem *addr)
87{ 253{
88 return *(volatile unsigned char __force *)addr; 254 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
89} 255}
90static inline unsigned short __raw_readw(const volatile void __iomem *addr) 256static inline unsigned short __raw_readw(const volatile void __iomem *addr)
91{ 257{
92 return *(volatile unsigned short __force *)addr; 258 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
93} 259}
94static inline unsigned int __raw_readl(const volatile void __iomem *addr) 260static inline unsigned int __raw_readl(const volatile void __iomem *addr)
95{ 261{
96 return *(volatile unsigned int __force *)addr; 262 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
97}
98static inline unsigned long __raw_readq(const volatile void __iomem *addr)
99{
100 return *(volatile unsigned long __force *)addr;
101} 263}
102static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr) 264static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
103{ 265{
104 *(volatile unsigned char __force *)addr = v; 266 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
105} 267}
106static inline void __raw_writew(unsigned short v, volatile void __iomem *addr) 268static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
107{ 269{
108 *(volatile unsigned short __force *)addr = v; 270 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
109} 271}
110static inline void __raw_writel(unsigned int v, volatile void __iomem *addr) 272static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
111{ 273{
112 *(volatile unsigned int __force *)addr = v; 274 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
275}
276
277#ifdef __powerpc64__
278static inline unsigned long __raw_readq(const volatile void __iomem *addr)
279{
280 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
113} 281}
114static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr) 282static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
115{ 283{
116 *(volatile unsigned long __force *)addr = v; 284 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
285}
286#endif /* __powerpc64__ */
287
288/*
289 *
290 * PCI PIO and MMIO accessors.
291 *
292 *
293 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
294 * machine checks (which they occasionally do when probing non existing
295 * IO ports on some platforms, like PowerMac and 8xx).
296 * I always found it to be of dubious reliability and I am tempted to get
297 * rid of it one of these days. So if you think it's important to keep it,
298 * please voice up asap. We never had it for 64 bits and I do not intend
299 * to port it over
300 */
301
302#ifdef CONFIG_PPC32
303
304#define __do_in_asm(name, op) \
305static inline unsigned int name(unsigned int port) \
306{ \
307 unsigned int x; \
308 __asm__ __volatile__( \
309 "sync\n" \
310 "0:" op " %0,0,%1\n" \
311 "1: twi 0,%0,0\n" \
312 "2: isync\n" \
313 "3: nop\n" \
314 "4:\n" \
315 ".section .fixup,\"ax\"\n" \
316 "5: li %0,-1\n" \
317 " b 4b\n" \
318 ".previous\n" \
319 ".section __ex_table,\"a\"\n" \
320 " .align 2\n" \
321 " .long 0b,5b\n" \
322 " .long 1b,5b\n" \
323 " .long 2b,5b\n" \
324 " .long 3b,5b\n" \
325 ".previous" \
326 : "=&r" (x) \
327 : "r" (port + _IO_BASE)); \
328 return x; \
329}
330
331#define __do_out_asm(name, op) \
332static inline void name(unsigned int val, unsigned int port) \
333{ \
334 __asm__ __volatile__( \
335 "sync\n" \
336 "0:" op " %0,0,%1\n" \
337 "1: sync\n" \
338 "2:\n" \
339 ".section __ex_table,\"a\"\n" \
340 " .align 2\n" \
341 " .long 0b,2b\n" \
342 " .long 1b,2b\n" \
343 ".previous" \
344 : : "r" (val), "r" (port + _IO_BASE)); \
345}
346
347__do_in_asm(_rec_inb, "lbzx")
348__do_in_asm(_rec_inw, "lhbrx")
349__do_in_asm(_rec_inl, "lwbrx")
350__do_out_asm(_rec_outb, "stbx")
351__do_out_asm(_rec_outw, "sthbrx")
352__do_out_asm(_rec_outl, "stwbrx")
353
354#endif /* CONFIG_PPC32 */
355
356/* The "__do_*" operations below provide the actual "base" implementation
357 * for each of the defined acccessor. Some of them use the out_* functions
358 * directly, some of them still use EEH, though we might change that in the
359 * future. Those macros below provide the necessary argument swapping and
360 * handling of the IO base for PIO.
361 *
362 * They are themselves used by the macros that define the actual accessors
363 * and can be used by the hooks if any.
364 *
365 * Note that PIO operations are always defined in terms of their corresonding
366 * MMIO operations. That allows platforms like iSeries who want to modify the
367 * behaviour of both to only hook on the MMIO version and get both. It's also
368 * possible to hook directly at the toplevel PIO operation if they have to
369 * be handled differently
370 */
371#define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
372#define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
373#define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
374#define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
375#define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
376#define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
377#define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
378
379#ifdef CONFIG_EEH
380#define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
381#define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
382#define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
383#define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
384#define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
385#define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
386#define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
387#else /* CONFIG_EEH */
388#define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
389#define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
390#define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
391#define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
392#define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
393#define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
394#define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
395#endif /* !defined(CONFIG_EEH) */
396
397#ifdef CONFIG_PPC32
398#define __do_outb(val, port) _rec_outb(val, port)
399#define __do_outw(val, port) _rec_outw(val, port)
400#define __do_outl(val, port) _rec_outl(val, port)
401#define __do_inb(port) _rec_inb(port)
402#define __do_inw(port) _rec_inw(port)
403#define __do_inl(port) _rec_inl(port)
404#else /* CONFIG_PPC32 */
405#define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)_IO_BASE+port);
406#define __do_outw(val, port) writew(val,(PCI_IO_ADDR)_IO_BASE+port);
407#define __do_outl(val, port) writel(val,(PCI_IO_ADDR)_IO_BASE+port);
408#define __do_inb(port) readb((PCI_IO_ADDR)_IO_BASE + port);
409#define __do_inw(port) readw((PCI_IO_ADDR)_IO_BASE + port);
410#define __do_inl(port) readl((PCI_IO_ADDR)_IO_BASE + port);
411#endif /* !CONFIG_PPC32 */
412
413#ifdef CONFIG_EEH
414#define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
415#define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
416#define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
417#else /* CONFIG_EEH */
418#define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
419#define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
420#define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
421#endif /* !CONFIG_EEH */
422#define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
423#define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
424#define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
425
426#define __do_insb(p, b, n) readsb((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
427#define __do_insw(p, b, n) readsw((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
428#define __do_insl(p, b, n) readsl((PCI_IO_ADDR)_IO_BASE+(p), (b), (n))
429#define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
430#define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
431#define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)_IO_BASE+(p),(b),(n))
432
433#define __do_memset_io(addr, c, n) \
434 _memset_io(PCI_FIX_ADDR(addr), c, n)
435#define __do_memcpy_toio(dst, src, n) \
436 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
437
438#ifdef CONFIG_EEH
439#define __do_memcpy_fromio(dst, src, n) \
440 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
441#else /* CONFIG_EEH */
442#define __do_memcpy_fromio(dst, src, n) \
443 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
444#endif /* !CONFIG_EEH */
445
446#ifdef CONFIG_PPC_INDIRECT_IO
447#define DEF_PCI_HOOK(x) x
448#else
449#define DEF_PCI_HOOK(x) NULL
450#endif
451
452/* Structure containing all the hooks */
453extern struct ppc_pci_io {
454
455#define DEF_PCI_AC_RET(name, ret, at, al) ret (*name) at;
456#define DEF_PCI_AC_NORET(name, at, al) void (*name) at;
457
458#include <asm/io-defs.h>
459
460#undef DEF_PCI_AC_RET
461#undef DEF_PCI_AC_NORET
462
463} ppc_pci_io;
464
465/* The inline wrappers */
466#define DEF_PCI_AC_RET(name, ret, at, al) \
467static inline ret name at \
468{ \
469 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
470 return ppc_pci_io.name al; \
471 return __do_##name al; \
472}
473
474#define DEF_PCI_AC_NORET(name, at, al) \
475static inline void name at \
476{ \
477 if (DEF_PCI_HOOK(ppc_pci_io.name) != NULL) \
478 ppc_pci_io.name al; \
479 else \
480 __do_##name al; \
117} 481}
118#define memset_io(a,b,c) eeh_memset_io((a),(b),(c))
119#define memcpy_fromio(a,b,c) eeh_memcpy_fromio((a),(b),(c))
120#define memcpy_toio(a,b,c) eeh_memcpy_toio((a),(b),(c))
121 482
122#endif /* CONFIG_PPC_ISERIES */ 483#include <asm/io-defs.h>
484
485#undef DEF_PCI_AC_RET
486#undef DEF_PCI_AC_NORET
487
488/* Some drivers check for the presence of readq & writeq with
489 * a #ifdef, so we make them happy here.
490 */
491#ifdef __powerpc64__
492#define readq readq
493#define writeq writeq
494#endif
495
496#ifdef CONFIG_NOT_COHERENT_CACHE
497
498#define dma_cache_inv(_start,_size) \
499 invalidate_dcache_range(_start, (_start + _size))
500#define dma_cache_wback(_start,_size) \
501 clean_dcache_range(_start, (_start + _size))
502#define dma_cache_wback_inv(_start,_size) \
503 flush_dcache_range(_start, (_start + _size))
504
505#else /* CONFIG_NOT_COHERENT_CACHE */
506
507#define dma_cache_inv(_start,_size) do { } while (0)
508#define dma_cache_wback(_start,_size) do { } while (0)
509#define dma_cache_wback_inv(_start,_size) do { } while (0)
510
511#endif /* !CONFIG_NOT_COHERENT_CACHE */
123 512
124/* 513/*
125 * The insw/outsw/insl/outsl macros don't do byte-swapping. 514 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
126 * They are only used in practice for transferring buffers which 515 * access
127 * are arrays of bytes, and byte-swapping is not appropriate in 516 */
128 * that case. - paulus */ 517#define xlate_dev_mem_ptr(p) __va(p)
129#define insb(port, buf, ns) eeh_insb((port), (buf), (ns)) 518
130#define insw(port, buf, ns) eeh_insw_ns((port), (buf), (ns)) 519/*
131#define insl(port, buf, nl) eeh_insl_ns((port), (buf), (nl)) 520 * Convert a virtual cached pointer to an uncached pointer
132 521 */
133#define outsb(port, buf, ns) _outsb((u8 __iomem *)((port)+pci_io_base), (buf), (ns)) 522#define xlate_dev_kmem_ptr(p) p
134#define outsw(port, buf, ns) _outsw_ns((u16 __iomem *)((port)+pci_io_base), (buf), (ns))
135#define outsl(port, buf, nl) _outsl_ns((u32 __iomem *)((port)+pci_io_base), (buf), (nl))
136
137#define readb(addr) eeh_readb(addr)
138#define readw(addr) eeh_readw(addr)
139#define readl(addr) eeh_readl(addr)
140#define readq(addr) eeh_readq(addr)
141#define writeb(data, addr) eeh_writeb((data), (addr))
142#define writew(data, addr) eeh_writew((data), (addr))
143#define writel(data, addr) eeh_writel((data), (addr))
144#define writeq(data, addr) eeh_writeq((data), (addr))
145#define inb(port) eeh_inb((unsigned long)port)
146#define outb(val, port) eeh_outb(val, (unsigned long)port)
147#define inw(port) eeh_inw((unsigned long)port)
148#define outw(val, port) eeh_outw(val, (unsigned long)port)
149#define inl(port) eeh_inl((unsigned long)port)
150#define outl(val, port) eeh_outl(val, (unsigned long)port)
151 523
524/*
525 * We don't do relaxed operations yet, at least not with this semantic
526 */
152#define readb_relaxed(addr) readb(addr) 527#define readb_relaxed(addr) readb(addr)
153#define readw_relaxed(addr) readw(addr) 528#define readw_relaxed(addr) readw(addr)
154#define readl_relaxed(addr) readl(addr) 529#define readl_relaxed(addr) readl(addr)
155#define readq_relaxed(addr) readq(addr) 530#define readq_relaxed(addr) readq(addr)
156 531
157extern void _insb(volatile u8 __iomem *port, void *buf, long count); 532#ifdef CONFIG_PPC32
158extern void _outsb(volatile u8 __iomem *port, const void *buf, long count); 533#define mmiowb()
159extern void _insw_ns(volatile u16 __iomem *port, void *buf, long count); 534#else
160extern void _outsw_ns(volatile u16 __iomem *port, const void *buf, long count); 535/*
161extern void _insl_ns(volatile u32 __iomem *port, void *buf, long count); 536 * Enforce synchronisation of stores vs. spin_unlock
162extern void _outsl_ns(volatile u32 __iomem *port, const void *buf, long count); 537 * (this does it explicitely, though our implementation of spin_unlock
163 538 * does it implicitely too)
539 */
164static inline void mmiowb(void) 540static inline void mmiowb(void)
165{ 541{
166 unsigned long tmp; 542 unsigned long tmp;
@@ -169,6 +545,24 @@ static inline void mmiowb(void)
169 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync)) 545 : "=&r" (tmp) : "i" (offsetof(struct paca_struct, io_sync))
170 : "memory"); 546 : "memory");
171} 547}
548#endif /* !CONFIG_PPC32 */
549
550static inline void iosync(void)
551{
552 __asm__ __volatile__ ("sync" : : : "memory");
553}
554
555/* Enforce in-order execution of data I/O.
556 * No distinction between read/write on PPC; use eieio for all three.
557 * Those are fairly week though. They don't provide a barrier between
558 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
559 * they only provide barriers between 2 __raw MMIO operations and
560 * possibly break write combining.
561 */
562#define iobarrier_rw() eieio()
563#define iobarrier_r() eieio()
564#define iobarrier_w() eieio()
565
172 566
173/* 567/*
174 * output pause versions need a delay at least for the 568 * output pause versions need a delay at least for the
@@ -185,11 +579,6 @@ static inline void mmiowb(void)
185#define IO_SPACE_LIMIT ~(0UL) 579#define IO_SPACE_LIMIT ~(0UL)
186 580
187 581
188extern int __ioremap_explicit(unsigned long p_addr, unsigned long v_addr,
189 unsigned long size, unsigned long flags);
190extern void __iomem *__ioremap(unsigned long address, unsigned long size,
191 unsigned long flags);
192
193/** 582/**
194 * ioremap - map bus memory into CPU space 583 * ioremap - map bus memory into CPU space
195 * @address: bus address of the memory 584 * @address: bus address of the memory
@@ -200,14 +589,77 @@ extern void __iomem *__ioremap(unsigned long address, unsigned long size,
200 * writew/writel functions and the other mmio helpers. The returned 589 * writew/writel functions and the other mmio helpers. The returned
201 * address is not guaranteed to be usable directly as a virtual 590 * address is not guaranteed to be usable directly as a virtual
202 * address. 591 * address.
592 *
593 * We provide a few variations of it:
594 *
595 * * ioremap is the standard one and provides non-cacheable guarded mappings
596 * and can be hooked by the platform via ppc_md
597 *
598 * * ioremap_flags allows to specify the page flags as an argument and can
599 * also be hooked by the platform via ppc_md
600 *
601 * * ioremap_nocache is identical to ioremap
602 *
603 * * iounmap undoes such a mapping and can be hooked
604 *
605 * * __ioremap_explicit (and the pending __iounmap_explicit) are low level
606 * functions to create hand-made mappings for use only by the PCI code
607 * and cannot currently be hooked.
608 *
609 * * __ioremap is the low level implementation used by ioremap and
610 * ioremap_flags and cannot be hooked (but can be used by a hook on one
611 * of the previous ones)
612 *
613 * * __iounmap, is the low level implementation used by iounmap and cannot
614 * be hooked (but can be used by a hook on iounmap)
615 *
203 */ 616 */
204extern void __iomem *ioremap(unsigned long address, unsigned long size); 617extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
205 618extern void __iomem *ioremap_flags(phys_addr_t address, unsigned long size,
619 unsigned long flags);
206#define ioremap_nocache(addr, size) ioremap((addr), (size)) 620#define ioremap_nocache(addr, size) ioremap((addr), (size))
207extern int iounmap_explicit(volatile void __iomem *addr, unsigned long size);
208extern void iounmap(volatile void __iomem *addr); 621extern void iounmap(volatile void __iomem *addr);
622
623extern void __iomem *__ioremap(phys_addr_t, unsigned long size,
624 unsigned long flags);
625extern void __iounmap(volatile void __iomem *addr);
626
627extern int __ioremap_explicit(phys_addr_t p_addr, unsigned long v_addr,
628 unsigned long size, unsigned long flags);
629extern int __iounmap_explicit(volatile void __iomem *start,
630 unsigned long size);
631
209extern void __iomem * reserve_phb_iospace(unsigned long size); 632extern void __iomem * reserve_phb_iospace(unsigned long size);
210 633
634/* Those are more 32 bits only functions */
635extern unsigned long iopa(unsigned long addr);
636extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
637extern void io_block_mapping(unsigned long virt, phys_addr_t phys,
638 unsigned int size, int flags);
639
640
641/*
642 * When CONFIG_PPC_INDIRECT_IO is set, we use the generic iomap implementation
643 * which needs some additional definitions here. They basically allow PIO
644 * space overall to be 1GB. This will work as long as we never try to use
645 * iomap to map MMIO below 1GB which should be fine on ppc64
646 */
647#define HAVE_ARCH_PIO_SIZE 1
648#define PIO_OFFSET 0x00000000UL
649#define PIO_MASK 0x3fffffffUL
650#define PIO_RESERVED 0x40000000UL
651
652#define mmio_read16be(addr) readw_be(addr)
653#define mmio_read32be(addr) readl_be(addr)
654#define mmio_write16be(val, addr) writew_be(val, addr)
655#define mmio_write32be(val, addr) writel_be(val, addr)
656#define mmio_insb(addr, dst, count) readsb(addr, dst, count)
657#define mmio_insw(addr, dst, count) readsw(addr, dst, count)
658#define mmio_insl(addr, dst, count) readsl(addr, dst, count)
659#define mmio_outsb(addr, src, count) writesb(addr, src, count)
660#define mmio_outsw(addr, src, count) writesw(addr, src, count)
661#define mmio_outsl(addr, src, count) writesl(addr, src, count)
662
211/** 663/**
212 * virt_to_phys - map virtual addresses to physical 664 * virt_to_phys - map virtual addresses to physical
213 * @address: address to remap 665 * @address: address to remap
@@ -254,178 +706,33 @@ static inline void * phys_to_virt(unsigned long address)
254 */ 706 */
255#define BIO_VMERGE_BOUNDARY 0 707#define BIO_VMERGE_BOUNDARY 0
256 708
257static inline void iosync(void)
258{
259 __asm__ __volatile__ ("sync" : : : "memory");
260}
261
262/* Enforce in-order execution of data I/O.
263 * No distinction between read/write on PPC; use eieio for all three.
264 */
265#define iobarrier_rw() eieio()
266#define iobarrier_r() eieio()
267#define iobarrier_w() eieio()
268
269/* 709/*
270 * 8, 16 and 32 bit, big and little endian I/O operations, with barrier. 710 * 32 bits still uses virt_to_bus() for it's implementation of DMA
271 * These routines do not perform EEH-related I/O address translation, 711 * mappings se we have to keep it defined here. We also have some old
272 * and should not be used directly by device drivers. Use inb/readb 712 * drivers (shame shame shame) that use bus_to_virt() and haven't been
273 * instead. 713 * fixed yet so I need to define it here.
274 */ 714 */
275static inline int __in_8(const volatile unsigned char __iomem *addr) 715#ifdef CONFIG_PPC32
276{
277 int ret;
278 716
279 __asm__ __volatile__("sync; lbz%U1%X1 %0,%1; twi 0,%0,0; isync" 717static inline unsigned long virt_to_bus(volatile void * address)
280 : "=r" (ret) : "m" (*addr));
281 return ret;
282}
283
284static inline void __out_8(volatile unsigned char __iomem *addr, int val)
285{
286 __asm__ __volatile__("sync; stb%U0%X0 %1,%0"
287 : "=m" (*addr) : "r" (val));
288 get_paca()->io_sync = 1;
289}
290
291static inline int __in_le16(const volatile unsigned short __iomem *addr)
292{ 718{
293 int ret; 719 if (address == NULL)
294 720 return 0;
295 __asm__ __volatile__("sync; lhbrx %0,0,%1; twi 0,%0,0; isync" 721 return __pa(address) + PCI_DRAM_OFFSET;
296 : "=r" (ret) : "r" (addr), "m" (*addr));
297 return ret;
298} 722}
299 723
300static inline int __in_be16(const volatile unsigned short __iomem *addr) 724static inline void * bus_to_virt(unsigned long address)
301{ 725{
302 int ret; 726 if (address == 0)
303 727 return NULL;
304 __asm__ __volatile__("sync; lhz%U1%X1 %0,%1; twi 0,%0,0; isync" 728 return __va(address - PCI_DRAM_OFFSET);
305 : "=r" (ret) : "m" (*addr));
306 return ret;
307} 729}
308 730
309static inline void __out_le16(volatile unsigned short __iomem *addr, int val) 731#define page_to_bus(page) (page_to_phys(page) + PCI_DRAM_OFFSET)
310{
311 __asm__ __volatile__("sync; sthbrx %1,0,%2"
312 : "=m" (*addr) : "r" (val), "r" (addr));
313 get_paca()->io_sync = 1;
314}
315
316static inline void __out_be16(volatile unsigned short __iomem *addr, int val)
317{
318 __asm__ __volatile__("sync; sth%U0%X0 %1,%0"
319 : "=m" (*addr) : "r" (val));
320 get_paca()->io_sync = 1;
321}
322
323static inline unsigned __in_le32(const volatile unsigned __iomem *addr)
324{
325 unsigned ret;
326
327 __asm__ __volatile__("sync; lwbrx %0,0,%1; twi 0,%0,0; isync"
328 : "=r" (ret) : "r" (addr), "m" (*addr));
329 return ret;
330}
331 732
332static inline unsigned __in_be32(const volatile unsigned __iomem *addr) 733#endif /* CONFIG_PPC32 */
333{
334 unsigned ret;
335
336 __asm__ __volatile__("sync; lwz%U1%X1 %0,%1; twi 0,%0,0; isync"
337 : "=r" (ret) : "m" (*addr));
338 return ret;
339}
340
341static inline void __out_le32(volatile unsigned __iomem *addr, int val)
342{
343 __asm__ __volatile__("sync; stwbrx %1,0,%2" : "=m" (*addr)
344 : "r" (val), "r" (addr));
345 get_paca()->io_sync = 1;
346}
347
348static inline void __out_be32(volatile unsigned __iomem *addr, int val)
349{
350 __asm__ __volatile__("sync; stw%U0%X0 %1,%0"
351 : "=m" (*addr) : "r" (val));
352 get_paca()->io_sync = 1;
353}
354
355static inline unsigned long __in_le64(const volatile unsigned long __iomem *addr)
356{
357 unsigned long tmp, ret;
358
359 __asm__ __volatile__(
360 "sync\n"
361 "ld %1,0(%2)\n"
362 "twi 0,%1,0\n"
363 "isync\n"
364 "rldimi %0,%1,5*8,1*8\n"
365 "rldimi %0,%1,3*8,2*8\n"
366 "rldimi %0,%1,1*8,3*8\n"
367 "rldimi %0,%1,7*8,4*8\n"
368 "rldicl %1,%1,32,0\n"
369 "rlwimi %0,%1,8,8,31\n"
370 "rlwimi %0,%1,24,16,23\n"
371 : "=r" (ret) , "=r" (tmp) : "b" (addr) , "m" (*addr));
372 return ret;
373}
374
375static inline unsigned long __in_be64(const volatile unsigned long __iomem *addr)
376{
377 unsigned long ret;
378 734
379 __asm__ __volatile__("sync; ld%U1%X1 %0,%1; twi 0,%0,0; isync"
380 : "=r" (ret) : "m" (*addr));
381 return ret;
382}
383
384static inline void __out_le64(volatile unsigned long __iomem *addr, unsigned long val)
385{
386 unsigned long tmp;
387
388 __asm__ __volatile__(
389 "rldimi %0,%1,5*8,1*8\n"
390 "rldimi %0,%1,3*8,2*8\n"
391 "rldimi %0,%1,1*8,3*8\n"
392 "rldimi %0,%1,7*8,4*8\n"
393 "rldicl %1,%1,32,0\n"
394 "rlwimi %0,%1,8,8,31\n"
395 "rlwimi %0,%1,24,16,23\n"
396 "sync\n"
397 "std %0,0(%3)"
398 : "=&r" (tmp) , "=&r" (val) : "1" (val) , "b" (addr) , "m" (*addr));
399 get_paca()->io_sync = 1;
400}
401
402static inline void __out_be64(volatile unsigned long __iomem *addr, unsigned long val)
403{
404 __asm__ __volatile__("sync; std%U0%X0 %1,%0" : "=m" (*addr) : "r" (val));
405 get_paca()->io_sync = 1;
406}
407
408#include <asm/eeh.h>
409
410/* Nothing to do */
411
412#define dma_cache_inv(_start,_size) do { } while (0)
413#define dma_cache_wback(_start,_size) do { } while (0)
414#define dma_cache_wback_inv(_start,_size) do { } while (0)
415
416
417/*
418 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
419 * access
420 */
421#define xlate_dev_mem_ptr(p) __va(p)
422
423/*
424 * Convert a virtual cached pointer to an uncached pointer
425 */
426#define xlate_dev_kmem_ptr(p) p
427 735
428#endif /* __KERNEL__ */ 736#endif /* __KERNEL__ */
429 737
430#endif /* CONFIG_PPC64 */
431#endif /* _ASM_POWERPC_IO_H */ 738#endif /* _ASM_POWERPC_IO_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 00:14:48 -0500