diff options
Diffstat (limited to 'include/asm-powerpc/immap_86xx.h')
-rw-r--r-- | include/asm-powerpc/immap_86xx.h | 219 |
1 files changed, 115 insertions, 104 deletions
diff --git a/include/asm-powerpc/immap_86xx.h b/include/asm-powerpc/immap_86xx.h index 59b9e07b8e99..0ad4e653d464 100644 --- a/include/asm-powerpc/immap_86xx.h +++ b/include/asm-powerpc/immap_86xx.h | |||
@@ -1,124 +1,135 @@ | |||
1 | /* | 1 | /** |
2 | * MPC86xx Internal Memory Map | 2 | * MPC86xx Internal Memory Map |
3 | * | 3 | * |
4 | * Author: Jeff Brown | 4 | * Authors: Jeff Brown |
5 | * Timur Tabi <timur@freescale.com> | ||
5 | * | 6 | * |
6 | * Copyright 2004 Freescale Semiconductor, Inc | 7 | * Copyright 2004,2007 Freescale Semiconductor, Inc |
7 | * | 8 | * |
8 | * This program is free software; you can redistribute it and/or modify it | 9 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | 10 | * under the terms of the GNU General Public License as published by the |
10 | * Free Software Foundation; either version 2 of the License, or (at your | 11 | * Free Software Foundation; either version 2 of the License, or (at your |
11 | * option) any later version. | 12 | * option) any later version. |
12 | * | 13 | * |
14 | * This header file defines structures for various 86xx SOC devices that are | ||
15 | * used by multiple source files. | ||
13 | */ | 16 | */ |
14 | 17 | ||
15 | #ifndef __ASM_POWERPC_IMMAP_86XX_H__ | 18 | #ifndef __ASM_POWERPC_IMMAP_86XX_H__ |
16 | #define __ASM_POWERPC_IMMAP_86XX_H__ | 19 | #define __ASM_POWERPC_IMMAP_86XX_H__ |
17 | #ifdef __KERNEL__ | 20 | #ifdef __KERNEL__ |
18 | 21 | ||
19 | /* Eventually this should define all the IO block registers in 86xx */ | 22 | /* Global Utility Registers */ |
23 | struct ccsr_guts { | ||
24 | __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ | ||
25 | __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ | ||
26 | __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ | ||
27 | __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */ | ||
28 | __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ | ||
29 | u8 res1[0x20 - 0x14]; | ||
30 | __be32 porcir; /* 0x.0020 - POR Configuration Information Register */ | ||
31 | u8 res2[0x30 - 0x24]; | ||
32 | __be32 gpiocr; /* 0x.0030 - GPIO Control Register */ | ||
33 | u8 res3[0x40 - 0x34]; | ||
34 | __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ | ||
35 | u8 res4[0x50 - 0x44]; | ||
36 | __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */ | ||
37 | u8 res5[0x60 - 0x54]; | ||
38 | __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ | ||
39 | u8 res6[0x70 - 0x64]; | ||
40 | __be32 devdisr; /* 0x.0070 - Device Disable Control */ | ||
41 | __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */ | ||
42 | u8 res7[0x80 - 0x78]; | ||
43 | __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ | ||
44 | u8 res8[0x90 - 0x84]; | ||
45 | __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */ | ||
46 | __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */ | ||
47 | u8 res9[0xA0 - 0x98]; | ||
48 | __be32 pvr; /* 0x.00a0 - Processor Version Register */ | ||
49 | __be32 svr; /* 0x.00a4 - System Version Register */ | ||
50 | u8 res10[0xB0 - 0xA8]; | ||
51 | __be32 rstcr; /* 0x.00b0 - Reset Control Register */ | ||
52 | u8 res11[0xC0 - 0xB4]; | ||
53 | __be32 elbcvselcr; /* 0x.00c0 - eLBC Voltage Select Ctrl Reg */ | ||
54 | u8 res12[0x800 - 0xC4]; | ||
55 | __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ | ||
56 | u8 res13[0x900 - 0x804]; | ||
57 | __be32 ircr; /* 0x.0900 - Infrared Control Register */ | ||
58 | u8 res14[0x908 - 0x904]; | ||
59 | __be32 dmacr; /* 0x.0908 - DMA Control Register */ | ||
60 | u8 res15[0x914 - 0x90C]; | ||
61 | __be32 elbccr; /* 0x.0914 - eLBC Control Register */ | ||
62 | u8 res16[0xB20 - 0x918]; | ||
63 | __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */ | ||
64 | __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */ | ||
65 | __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */ | ||
66 | u8 res17[0xE00 - 0xB2C]; | ||
67 | __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */ | ||
68 | u8 res18[0xE10 - 0xE04]; | ||
69 | __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ | ||
70 | u8 res19[0xE20 - 0xE14]; | ||
71 | __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ | ||
72 | u8 res20[0xF04 - 0xE24]; | ||
73 | __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */ | ||
74 | __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */ | ||
75 | u8 res21[0xF40 - 0xF0C]; | ||
76 | __be32 srds2cr0; /* 0x.0f40 - SerDes1 Control Register 0 */ | ||
77 | __be32 srds2cr1; /* 0x.0f44 - SerDes1 Control Register 0 */ | ||
78 | } __attribute__ ((packed)); | ||
20 | 79 | ||
21 | /* PCI Registers */ | 80 | #define CCSR_GUTS_DMACR_DEV_SSI 0 /* DMA controller/channel set to SSI */ |
22 | typedef struct ccsr_pci { | 81 | #define CCSR_GUTS_DMACR_DEV_IR 1 /* DMA controller/channel set to IR */ |
23 | uint cfg_addr; /* 0x.000 - PCI Configuration Address Register */ | ||
24 | uint cfg_data; /* 0x.004 - PCI Configuration Data Register */ | ||
25 | uint int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ | ||
26 | char res1[3060]; | ||
27 | uint potar0; /* 0x.c00 - PCI Outbound Transaction Address Register 0 */ | ||
28 | uint potear0; /* 0x.c04 - PCI Outbound Translation Extended Address Register 0 */ | ||
29 | uint powbar0; /* 0x.c08 - PCI Outbound Window Base Address Register 0 */ | ||
30 | char res2[4]; | ||
31 | uint powar0; /* 0x.c10 - PCI Outbound Window Attributes Register 0 */ | ||
32 | char res3[12]; | ||
33 | uint potar1; /* 0x.c20 - PCI Outbound Transaction Address Register 1 */ | ||
34 | uint potear1; /* 0x.c24 - PCI Outbound Translation Extended Address Register 1 */ | ||
35 | uint powbar1; /* 0x.c28 - PCI Outbound Window Base Address Register 1 */ | ||
36 | char res4[4]; | ||
37 | uint powar1; /* 0x.c30 - PCI Outbound Window Attributes Register 1 */ | ||
38 | char res5[12]; | ||
39 | uint potar2; /* 0x.c40 - PCI Outbound Transaction Address Register 2 */ | ||
40 | uint potear2; /* 0x.c44 - PCI Outbound Translation Extended Address Register 2 */ | ||
41 | uint powbar2; /* 0x.c48 - PCI Outbound Window Base Address Register 2 */ | ||
42 | char res6[4]; | ||
43 | uint powar2; /* 0x.c50 - PCI Outbound Window Attributes Register 2 */ | ||
44 | char res7[12]; | ||
45 | uint potar3; /* 0x.c60 - PCI Outbound Transaction Address Register 3 */ | ||
46 | uint potear3; /* 0x.c64 - PCI Outbound Translation Extended Address Register 3 */ | ||
47 | uint powbar3; /* 0x.c68 - PCI Outbound Window Base Address Register 3 */ | ||
48 | char res8[4]; | ||
49 | uint powar3; /* 0x.c70 - PCI Outbound Window Attributes Register 3 */ | ||
50 | char res9[12]; | ||
51 | uint potar4; /* 0x.c80 - PCI Outbound Transaction Address Register 4 */ | ||
52 | uint potear4; /* 0x.c84 - PCI Outbound Translation Extended Address Register 4 */ | ||
53 | uint powbar4; /* 0x.c88 - PCI Outbound Window Base Address Register 4 */ | ||
54 | char res10[4]; | ||
55 | uint powar4; /* 0x.c90 - PCI Outbound Window Attributes Register 4 */ | ||
56 | char res11[268]; | ||
57 | uint pitar3; /* 0x.da0 - PCI Inbound Translation Address Register 3 */ | ||
58 | char res12[4]; | ||
59 | uint piwbar3; /* 0x.da8 - PCI Inbound Window Base Address Register 3 */ | ||
60 | uint piwbear3; /* 0x.dac - PCI Inbound Window Base Extended Address Register 3 */ | ||
61 | uint piwar3; /* 0x.db0 - PCI Inbound Window Attributes Register 3 */ | ||
62 | char res13[12]; | ||
63 | uint pitar2; /* 0x.dc0 - PCI Inbound Translation Address Register 2 */ | ||
64 | char res14[4]; | ||
65 | uint piwbar2; /* 0x.dc8 - PCI Inbound Window Base Address Register 2 */ | ||
66 | uint piwbear2; /* 0x.dcc - PCI Inbound Window Base Extended Address Register 2 */ | ||
67 | uint piwar2; /* 0x.dd0 - PCI Inbound Window Attributes Register 2 */ | ||
68 | char res15[12]; | ||
69 | uint pitar1; /* 0x.de0 - PCI Inbound Translation Address Register 1 */ | ||
70 | char res16[4]; | ||
71 | uint piwbar1; /* 0x.de8 - PCI Inbound Window Base Address Register 1 */ | ||
72 | char res17[4]; | ||
73 | uint piwar1; /* 0x.df0 - PCI Inbound Window Attributes Register 1 */ | ||
74 | char res18[12]; | ||
75 | uint err_dr; /* 0x.e00 - PCI Error Detect Register */ | ||
76 | uint err_cap_dr; /* 0x.e04 - PCI Error Capture Disable Register */ | ||
77 | uint err_en; /* 0x.e08 - PCI Error Enable Register */ | ||
78 | uint err_attrib; /* 0x.e0c - PCI Error Attributes Capture Register */ | ||
79 | uint err_addr; /* 0x.e10 - PCI Error Address Capture Register */ | ||
80 | uint err_ext_addr; /* 0x.e14 - PCI Error Extended Address Capture Register */ | ||
81 | uint err_dl; /* 0x.e18 - PCI Error Data Low Capture Register */ | ||
82 | uint err_dh; /* 0x.e1c - PCI Error Data High Capture Register */ | ||
83 | uint gas_timr; /* 0x.e20 - PCI Gasket Timer Register */ | ||
84 | uint pci_timr; /* 0x.e24 - PCI Timer Register */ | ||
85 | char res19[472]; | ||
86 | } ccsr_pci_t; | ||
87 | 82 | ||
88 | /* Global Utility Registers */ | 83 | /* |
89 | typedef struct ccsr_guts { | 84 | * Set the DMACR register in the GUTS |
90 | uint porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */ | 85 | * |
91 | uint porbmsr; /* 0x.0004 - POR Boot Mode Status Register */ | 86 | * The DMACR register determines the source of initiated transfers for each |
92 | uint porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */ | 87 | * channel on each DMA controller. Rather than have a bunch of repetitive |
93 | uint pordevsr; /* 0x.000c - POR I/O Device Status Register */ | 88 | * macros for the bit patterns, we just have a function that calculates |
94 | uint pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */ | 89 | * them. |
95 | char res1[12]; | 90 | * |
96 | uint gpporcr; /* 0x.0020 - General-Purpose POR Configuration Register */ | 91 | * guts: Pointer to GUTS structure |
97 | char res2[12]; | 92 | * co: The DMA controller (1 or 2) |
98 | uint gpiocr; /* 0x.0030 - GPIO Control Register */ | 93 | * ch: The channel on the DMA controller (0, 1, 2, or 3) |
99 | char res3[12]; | 94 | * device: The device to set as the source (CCSR_GUTS_DMACR_DEV_xx) |
100 | uint gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */ | 95 | */ |
101 | char res4[12]; | 96 | static inline void guts_set_dmacr(struct ccsr_guts __iomem *guts, |
102 | uint gpindr; /* 0x.0050 - General-Purpose Input Data Register */ | 97 | unsigned int co, unsigned int ch, unsigned int device) |
103 | char res5[12]; | 98 | { |
104 | uint pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */ | 99 | unsigned int shift = 16 + (8 * (2 - co) + 2 * (3 - ch)); |
105 | char res6[12]; | 100 | |
106 | uint devdisr; /* 0x.0070 - Device Disable Control */ | 101 | clrsetbits_be32(&guts->dmacr, 3 << shift, device << shift); |
107 | char res7[12]; | 102 | } |
108 | uint powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */ | 103 | |
109 | char res8[12]; | 104 | #define CCSR_GUTS_PMUXCR_LDPSEL 0x00010000 |
110 | uint mcpsumr; /* 0x.0090 - Machine Check Summary Register */ | 105 | #define CCSR_GUTS_PMUXCR_SSI1_MASK 0x0000C000 /* Bitmask for SSI1 */ |
111 | char res9[12]; | 106 | #define CCSR_GUTS_PMUXCR_SSI1_LA 0x00000000 /* Latched address */ |
112 | uint pvr; /* 0x.00a0 - Processor Version Register */ | 107 | #define CCSR_GUTS_PMUXCR_SSI1_HI 0x00004000 /* High impedance */ |
113 | uint svr; /* 0x.00a4 - System Version Register */ | 108 | #define CCSR_GUTS_PMUXCR_SSI1_SSI 0x00008000 /* Used for SSI1 */ |
114 | char res10[3416]; | 109 | #define CCSR_GUTS_PMUXCR_SSI2_MASK 0x00003000 /* Bitmask for SSI2 */ |
115 | uint clkocr; /* 0x.0e00 - Clock Out Select Register */ | 110 | #define CCSR_GUTS_PMUXCR_SSI2_LA 0x00000000 /* Latched address */ |
116 | char res11[12]; | 111 | #define CCSR_GUTS_PMUXCR_SSI2_HI 0x00001000 /* High impedance */ |
117 | uint ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */ | 112 | #define CCSR_GUTS_PMUXCR_SSI2_SSI 0x00002000 /* Used for SSI2 */ |
118 | char res12[12]; | 113 | #define CCSR_GUTS_PMUXCR_LA_22_25_LA 0x00000000 /* Latched Address */ |
119 | uint lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */ | 114 | #define CCSR_GUTS_PMUXCR_LA_22_25_HI 0x00000400 /* High impedance */ |
120 | char res13[61916]; | 115 | #define CCSR_GUTS_PMUXCR_DBGDRV 0x00000200 /* Signals not driven */ |
121 | } ccsr_guts_t; | 116 | #define CCSR_GUTS_PMUXCR_DMA2_0 0x00000008 |
117 | #define CCSR_GUTS_PMUXCR_DMA2_3 0x00000004 | ||
118 | #define CCSR_GUTS_PMUXCR_DMA1_0 0x00000002 | ||
119 | #define CCSR_GUTS_PMUXCR_DMA1_3 0x00000001 | ||
120 | |||
121 | #define CCSR_GUTS_CLKDVDR_PXCKEN 0x80000000 | ||
122 | #define CCSR_GUTS_CLKDVDR_SSICKEN 0x20000000 | ||
123 | #define CCSR_GUTS_CLKDVDR_PXCKINV 0x10000000 | ||
124 | #define CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT 25 | ||
125 | #define CCSR_GUTS_CLKDVDR_PXCKDLY_MASK 0x06000000 | ||
126 | #define CCSR_GUTS_CLKDVDR_PXCKDLY(x) \ | ||
127 | (((x) & 3) << CCSR_GUTS_CLKDVDR_PXCKDLY_SHIFT) | ||
128 | #define CCSR_GUTS_CLKDVDR_PXCLK_SHIFT 16 | ||
129 | #define CCSR_GUTS_CLKDVDR_PXCLK_MASK 0x001F0000 | ||
130 | #define CCSR_GUTS_CLKDVDR_PXCLK(x) (((x) & 31) << CCSR_GUTS_CLKDVDR_PXCLK_SHIFT) | ||
131 | #define CCSR_GUTS_CLKDVDR_SSICLK_MASK 0x000000FF | ||
132 | #define CCSR_GUTS_CLKDVDR_SSICLK(x) ((x) & CCSR_GUTS_CLKDVDR_SSICLK_MASK) | ||
122 | 133 | ||
123 | #endif /* __ASM_POWERPC_IMMAP_86XX_H__ */ | 134 | #endif /* __ASM_POWERPC_IMMAP_86XX_H__ */ |
124 | #endif /* __KERNEL__ */ | 135 | #endif /* __KERNEL__ */ |