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1/* Freescale Local Bus Controller
2 *
3 * Copyright (c) 2006-2007 Freescale Semiconductor
4 *
5 * Authors: Nick Spence <nick.spence@freescale.com>,
6 * Scott Wood <scottwood@freescale.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __ASM_FSL_LBC_H
24#define __ASM_FSL_LBC_H
25
26#include <linux/types.h>
27
28struct fsl_lbc_bank {
29 __be32 br; /**< Base Register */
30#define BR_BA 0xFFFF8000
31#define BR_BA_SHIFT 15
32#define BR_PS 0x00001800
33#define BR_PS_SHIFT 11
34#define BR_PS_8 0x00000800 /* Port Size 8 bit */
35#define BR_PS_16 0x00001000 /* Port Size 16 bit */
36#define BR_PS_32 0x00001800 /* Port Size 32 bit */
37#define BR_DECC 0x00000600
38#define BR_DECC_SHIFT 9
39#define BR_DECC_OFF 0x00000000 /* HW ECC checking and generation off */
40#define BR_DECC_CHK 0x00000200 /* HW ECC checking on, generation off */
41#define BR_DECC_CHK_GEN 0x00000400 /* HW ECC checking and generation on */
42#define BR_WP 0x00000100
43#define BR_WP_SHIFT 8
44#define BR_MSEL 0x000000E0
45#define BR_MSEL_SHIFT 5
46#define BR_MS_GPCM 0x00000000 /* GPCM */
47#define BR_MS_FCM 0x00000020 /* FCM */
48#define BR_MS_SDRAM 0x00000060 /* SDRAM */
49#define BR_MS_UPMA 0x00000080 /* UPMA */
50#define BR_MS_UPMB 0x000000A0 /* UPMB */
51#define BR_MS_UPMC 0x000000C0 /* UPMC */
52#define BR_V 0x00000001
53#define BR_V_SHIFT 0
54#define BR_RES ~(BR_BA|BR_PS|BR_DECC|BR_WP|BR_MSEL|BR_V)
55
56 __be32 or; /**< Base Register */
57#define OR0 0x5004
58#define OR1 0x500C
59#define OR2 0x5014
60#define OR3 0x501C
61#define OR4 0x5024
62#define OR5 0x502C
63#define OR6 0x5034
64#define OR7 0x503C
65
66#define OR_FCM_AM 0xFFFF8000
67#define OR_FCM_AM_SHIFT 15
68#define OR_FCM_BCTLD 0x00001000
69#define OR_FCM_BCTLD_SHIFT 12
70#define OR_FCM_PGS 0x00000400
71#define OR_FCM_PGS_SHIFT 10
72#define OR_FCM_CSCT 0x00000200
73#define OR_FCM_CSCT_SHIFT 9
74#define OR_FCM_CST 0x00000100
75#define OR_FCM_CST_SHIFT 8
76#define OR_FCM_CHT 0x00000080
77#define OR_FCM_CHT_SHIFT 7
78#define OR_FCM_SCY 0x00000070
79#define OR_FCM_SCY_SHIFT 4
80#define OR_FCM_SCY_1 0x00000010
81#define OR_FCM_SCY_2 0x00000020
82#define OR_FCM_SCY_3 0x00000030
83#define OR_FCM_SCY_4 0x00000040
84#define OR_FCM_SCY_5 0x00000050
85#define OR_FCM_SCY_6 0x00000060
86#define OR_FCM_SCY_7 0x00000070
87#define OR_FCM_RST 0x00000008
88#define OR_FCM_RST_SHIFT 3
89#define OR_FCM_TRLX 0x00000004
90#define OR_FCM_TRLX_SHIFT 2
91#define OR_FCM_EHTR 0x00000002
92#define OR_FCM_EHTR_SHIFT 1
93};
94
95struct fsl_lbc_regs {
96 struct fsl_lbc_bank bank[8];
97 u8 res0[0x28];
98 __be32 mar; /**< UPM Address Register */
99 u8 res1[0x4];
100 __be32 mamr; /**< UPMA Mode Register */
101 __be32 mbmr; /**< UPMB Mode Register */
102 __be32 mcmr; /**< UPMC Mode Register */
103 u8 res2[0x8];
104 __be32 mrtpr; /**< Memory Refresh Timer Prescaler Register */
105 __be32 mdr; /**< UPM Data Register */
106 u8 res3[0x4];
107 __be32 lsor; /**< Special Operation Initiation Register */
108 __be32 lsdmr; /**< SDRAM Mode Register */
109 u8 res4[0x8];
110 __be32 lurt; /**< UPM Refresh Timer */
111 __be32 lsrt; /**< SDRAM Refresh Timer */
112 u8 res5[0x8];
113 __be32 ltesr; /**< Transfer Error Status Register */
114#define LTESR_BM 0x80000000
115#define LTESR_FCT 0x40000000
116#define LTESR_PAR 0x20000000
117#define LTESR_WP 0x04000000
118#define LTESR_ATMW 0x00800000
119#define LTESR_ATMR 0x00400000
120#define LTESR_CS 0x00080000
121#define LTESR_CC 0x00000001
122#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC)
123 __be32 ltedr; /**< Transfer Error Disable Register */
124 __be32 lteir; /**< Transfer Error Interrupt Register */
125 __be32 lteatr; /**< Transfer Error Attributes Register */
126 __be32 ltear; /**< Transfer Error Address Register */
127 u8 res6[0xC];
128 __be32 lbcr; /**< Configuration Register */
129#define LBCR_LDIS 0x80000000
130#define LBCR_LDIS_SHIFT 31
131#define LBCR_BCTLC 0x00C00000
132#define LBCR_BCTLC_SHIFT 22
133#define LBCR_AHD 0x00200000
134#define LBCR_LPBSE 0x00020000
135#define LBCR_LPBSE_SHIFT 17
136#define LBCR_EPAR 0x00010000
137#define LBCR_EPAR_SHIFT 16
138#define LBCR_BMT 0x0000FF00
139#define LBCR_BMT_SHIFT 8
140#define LBCR_INIT 0x00040000
141 __be32 lcrr; /**< Clock Ratio Register */
142#define LCRR_DBYP 0x80000000
143#define LCRR_DBYP_SHIFT 31
144#define LCRR_BUFCMDC 0x30000000
145#define LCRR_BUFCMDC_SHIFT 28
146#define LCRR_ECL 0x03000000
147#define LCRR_ECL_SHIFT 24
148#define LCRR_EADC 0x00030000
149#define LCRR_EADC_SHIFT 16
150#define LCRR_CLKDIV 0x0000000F
151#define LCRR_CLKDIV_SHIFT 0
152 u8 res7[0x8];
153 __be32 fmr; /**< Flash Mode Register */
154#define FMR_CWTO 0x0000F000
155#define FMR_CWTO_SHIFT 12
156#define FMR_BOOT 0x00000800
157#define FMR_ECCM 0x00000100
158#define FMR_AL 0x00000030
159#define FMR_AL_SHIFT 4
160#define FMR_OP 0x00000003
161#define FMR_OP_SHIFT 0
162 __be32 fir; /**< Flash Instruction Register */
163#define FIR_OP0 0xF0000000
164#define FIR_OP0_SHIFT 28
165#define FIR_OP1 0x0F000000
166#define FIR_OP1_SHIFT 24
167#define FIR_OP2 0x00F00000
168#define FIR_OP2_SHIFT 20
169#define FIR_OP3 0x000F0000
170#define FIR_OP3_SHIFT 16
171#define FIR_OP4 0x0000F000
172#define FIR_OP4_SHIFT 12
173#define FIR_OP5 0x00000F00
174#define FIR_OP5_SHIFT 8
175#define FIR_OP6 0x000000F0
176#define FIR_OP6_SHIFT 4
177#define FIR_OP7 0x0000000F
178#define FIR_OP7_SHIFT 0
179#define FIR_OP_NOP 0x0 /* No operation and end of sequence */
180#define FIR_OP_CA 0x1 /* Issue current column address */
181#define FIR_OP_PA 0x2 /* Issue current block+page address */
182#define FIR_OP_UA 0x3 /* Issue user defined address */
183#define FIR_OP_CM0 0x4 /* Issue command from FCR[CMD0] */
184#define FIR_OP_CM1 0x5 /* Issue command from FCR[CMD1] */
185#define FIR_OP_CM2 0x6 /* Issue command from FCR[CMD2] */
186#define FIR_OP_CM3 0x7 /* Issue command from FCR[CMD3] */
187#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */
188#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */
189#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */
190#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */
191#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */
192#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */
193#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */
194#define FIR_OP_RSW 0xE /* Wait then read 1 or 2 bytes */
195 __be32 fcr; /**< Flash Command Register */
196#define FCR_CMD0 0xFF000000
197#define FCR_CMD0_SHIFT 24
198#define FCR_CMD1 0x00FF0000
199#define FCR_CMD1_SHIFT 16
200#define FCR_CMD2 0x0000FF00
201#define FCR_CMD2_SHIFT 8
202#define FCR_CMD3 0x000000FF
203#define FCR_CMD3_SHIFT 0
204 __be32 fbar; /**< Flash Block Address Register */
205#define FBAR_BLK 0x00FFFFFF
206 __be32 fpar; /**< Flash Page Address Register */
207#define FPAR_SP_PI 0x00007C00
208#define FPAR_SP_PI_SHIFT 10
209#define FPAR_SP_MS 0x00000200
210#define FPAR_SP_CI 0x000001FF
211#define FPAR_SP_CI_SHIFT 0
212#define FPAR_LP_PI 0x0003F000
213#define FPAR_LP_PI_SHIFT 12
214#define FPAR_LP_MS 0x00000800
215#define FPAR_LP_CI 0x000007FF
216#define FPAR_LP_CI_SHIFT 0
217 __be32 fbcr; /**< Flash Byte Count Register */
218#define FBCR_BC 0x00000FFF
219 u8 res11[0x8];
220 u8 res8[0xF00];
221};
222
223#endif /* __ASM_FSL_LBC_H */
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-06 23:19:37 -0500