diff options
Diffstat (limited to 'include/asm-powerpc/dcr-regs.h')
| -rw-r--r-- | include/asm-powerpc/dcr-regs.h | 149 |
1 files changed, 0 insertions, 149 deletions
diff --git a/include/asm-powerpc/dcr-regs.h b/include/asm-powerpc/dcr-regs.h deleted file mode 100644 index 29b0ecef980a..000000000000 --- a/include/asm-powerpc/dcr-regs.h +++ /dev/null | |||
| @@ -1,149 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * Common DCR / SDR / CPR register definitions used on various IBM/AMCC | ||
| 3 | * 4xx processors | ||
| 4 | * | ||
| 5 | * Copyright 2007 Benjamin Herrenschmidt, IBM Corp | ||
| 6 | * <benh@kernel.crashing.org> | ||
| 7 | * | ||
| 8 | * Mostly lifted from asm-ppc/ibm4xx.h by | ||
| 9 | * | ||
| 10 | * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #ifndef __DCR_REGS_H__ | ||
| 15 | #define __DCR_REGS_H__ | ||
| 16 | |||
| 17 | /* | ||
| 18 | * Most DCRs used for controlling devices such as the MAL, DMA engine, | ||
| 19 | * etc... are obtained for the device tree. | ||
| 20 | * | ||
| 21 | * The definitions in this files are fixed DCRs and indirect DCRs that | ||
| 22 | * are commonly used outside of specific drivers or refer to core | ||
| 23 | * common registers that may occasionally have to be tweaked outside | ||
| 24 | * of the driver main register set | ||
| 25 | */ | ||
| 26 | |||
| 27 | /* CPRs (440GX and 440SP/440SPe) */ | ||
| 28 | #define DCRN_CPR0_CONFIG_ADDR 0xc | ||
| 29 | #define DCRN_CPR0_CONFIG_DATA 0xd | ||
| 30 | |||
| 31 | /* SDRs (440GX and 440SP/440SPe) */ | ||
| 32 | #define DCRN_SDR0_CONFIG_ADDR 0xe | ||
| 33 | #define DCRN_SDR0_CONFIG_DATA 0xf | ||
| 34 | |||
| 35 | #define SDR0_PFC0 0x4100 | ||
| 36 | #define SDR0_PFC1 0x4101 | ||
| 37 | #define SDR0_PFC1_EPS 0x1c00000 | ||
| 38 | #define SDR0_PFC1_EPS_SHIFT 22 | ||
| 39 | #define SDR0_PFC1_RMII 0x02000000 | ||
| 40 | #define SDR0_MFR 0x4300 | ||
| 41 | #define SDR0_MFR_TAH0 0x80000000 /* TAHOE0 Enable */ | ||
| 42 | #define SDR0_MFR_TAH1 0x40000000 /* TAHOE1 Enable */ | ||
| 43 | #define SDR0_MFR_PCM 0x10000000 /* PPC440GP irq compat mode */ | ||
| 44 | #define SDR0_MFR_ECS 0x08000000 /* EMAC int clk */ | ||
| 45 | #define SDR0_MFR_T0TXFL 0x00080000 | ||
| 46 | #define SDR0_MFR_T0TXFH 0x00040000 | ||
| 47 | #define SDR0_MFR_T1TXFL 0x00020000 | ||
| 48 | #define SDR0_MFR_T1TXFH 0x00010000 | ||
| 49 | #define SDR0_MFR_E0TXFL 0x00008000 | ||
| 50 | #define SDR0_MFR_E0TXFH 0x00004000 | ||
| 51 | #define SDR0_MFR_E0RXFL 0x00002000 | ||
| 52 | #define SDR0_MFR_E0RXFH 0x00001000 | ||
| 53 | #define SDR0_MFR_E1TXFL 0x00000800 | ||
| 54 | #define SDR0_MFR_E1TXFH 0x00000400 | ||
| 55 | #define SDR0_MFR_E1RXFL 0x00000200 | ||
| 56 | #define SDR0_MFR_E1RXFH 0x00000100 | ||
| 57 | #define SDR0_MFR_E2TXFL 0x00000080 | ||
| 58 | #define SDR0_MFR_E2TXFH 0x00000040 | ||
| 59 | #define SDR0_MFR_E2RXFL 0x00000020 | ||
| 60 | #define SDR0_MFR_E2RXFH 0x00000010 | ||
| 61 | #define SDR0_MFR_E3TXFL 0x00000008 | ||
| 62 | #define SDR0_MFR_E3TXFH 0x00000004 | ||
| 63 | #define SDR0_MFR_E3RXFL 0x00000002 | ||
| 64 | #define SDR0_MFR_E3RXFH 0x00000001 | ||
| 65 | #define SDR0_UART0 0x0120 | ||
| 66 | #define SDR0_UART1 0x0121 | ||
| 67 | #define SDR0_UART2 0x0122 | ||
| 68 | #define SDR0_UART3 0x0123 | ||
| 69 | #define SDR0_CUST0 0x4000 | ||
| 70 | |||
| 71 | /* | ||
| 72 | * All those DCR register addresses are offsets from the base address | ||
| 73 | * for the SRAM0 controller (e.g. 0x20 on 440GX). The base address is | ||
| 74 | * excluded here and configured in the device tree. | ||
| 75 | */ | ||
| 76 | #define DCRN_SRAM0_SB0CR 0x00 | ||
| 77 | #define DCRN_SRAM0_SB1CR 0x01 | ||
| 78 | #define DCRN_SRAM0_SB2CR 0x02 | ||
| 79 | #define DCRN_SRAM0_SB3CR 0x03 | ||
| 80 | #define SRAM_SBCR_BU_MASK 0x00000180 | ||
| 81 | #define SRAM_SBCR_BS_64KB 0x00000800 | ||
| 82 | #define SRAM_SBCR_BU_RO 0x00000080 | ||
| 83 | #define SRAM_SBCR_BU_RW 0x00000180 | ||
| 84 | #define DCRN_SRAM0_BEAR 0x04 | ||
| 85 | #define DCRN_SRAM0_BESR0 0x05 | ||
| 86 | #define DCRN_SRAM0_BESR1 0x06 | ||
| 87 | #define DCRN_SRAM0_PMEG 0x07 | ||
| 88 | #define DCRN_SRAM0_CID 0x08 | ||
| 89 | #define DCRN_SRAM0_REVID 0x09 | ||
| 90 | #define DCRN_SRAM0_DPC 0x0a | ||
| 91 | #define SRAM_DPC_ENABLE 0x80000000 | ||
| 92 | |||
| 93 | /* | ||
| 94 | * All those DCR register addresses are offsets from the base address | ||
| 95 | * for the SRAM0 controller (e.g. 0x30 on 440GX). The base address is | ||
| 96 | * excluded here and configured in the device tree. | ||
| 97 | */ | ||
| 98 | #define DCRN_L2C0_CFG 0x00 | ||
| 99 | #define L2C_CFG_L2M 0x80000000 | ||
| 100 | #define L2C_CFG_ICU 0x40000000 | ||
| 101 | #define L2C_CFG_DCU 0x20000000 | ||
| 102 | #define L2C_CFG_DCW_MASK 0x1e000000 | ||
| 103 | #define L2C_CFG_TPC 0x01000000 | ||
| 104 | #define L2C_CFG_CPC 0x00800000 | ||
| 105 | #define L2C_CFG_FRAN 0x00200000 | ||
| 106 | #define L2C_CFG_SS_MASK 0x00180000 | ||
| 107 | #define L2C_CFG_SS_256 0x00000000 | ||
| 108 | #define L2C_CFG_CPIM 0x00040000 | ||
| 109 | #define L2C_CFG_TPIM 0x00020000 | ||
| 110 | #define L2C_CFG_LIM 0x00010000 | ||
| 111 | #define L2C_CFG_PMUX_MASK 0x00007000 | ||
| 112 | #define L2C_CFG_PMUX_SNP 0x00000000 | ||
| 113 | #define L2C_CFG_PMUX_IF 0x00001000 | ||
| 114 | #define L2C_CFG_PMUX_DF 0x00002000 | ||
| 115 | #define L2C_CFG_PMUX_DS 0x00003000 | ||
| 116 | #define L2C_CFG_PMIM 0x00000800 | ||
| 117 | #define L2C_CFG_TPEI 0x00000400 | ||
| 118 | #define L2C_CFG_CPEI 0x00000200 | ||
| 119 | #define L2C_CFG_NAM 0x00000100 | ||
| 120 | #define L2C_CFG_SMCM 0x00000080 | ||
| 121 | #define L2C_CFG_NBRM 0x00000040 | ||
| 122 | #define L2C_CFG_RDBW 0x00000008 /* only 460EX/GT */ | ||
| 123 | #define DCRN_L2C0_CMD 0x01 | ||
| 124 | #define L2C_CMD_CLR 0x80000000 | ||
| 125 | #define L2C_CMD_DIAG 0x40000000 | ||
| 126 | #define L2C_CMD_INV 0x20000000 | ||
| 127 | #define L2C_CMD_CCP 0x10000000 | ||
| 128 | #define L2C_CMD_CTE 0x08000000 | ||
| 129 | #define L2C_CMD_STRC 0x04000000 | ||
| 130 | #define L2C_CMD_STPC 0x02000000 | ||
| 131 | #define L2C_CMD_RPMC 0x01000000 | ||
| 132 | #define L2C_CMD_HCC 0x00800000 | ||
| 133 | #define DCRN_L2C0_ADDR 0x02 | ||
| 134 | #define DCRN_L2C0_DATA 0x03 | ||
| 135 | #define DCRN_L2C0_SR 0x04 | ||
| 136 | #define L2C_SR_CC 0x80000000 | ||
| 137 | #define L2C_SR_CPE 0x40000000 | ||
| 138 | #define L2C_SR_TPE 0x20000000 | ||
| 139 | #define L2C_SR_LRU 0x10000000 | ||
| 140 | #define L2C_SR_PCS 0x08000000 | ||
| 141 | #define DCRN_L2C0_REVID 0x05 | ||
| 142 | #define DCRN_L2C0_SNP0 0x06 | ||
| 143 | #define DCRN_L2C0_SNP1 0x07 | ||
| 144 | #define L2C_SNP_BA_MASK 0xffff0000 | ||
| 145 | #define L2C_SNP_SSR_MASK 0x0000f000 | ||
| 146 | #define L2C_SNP_SSR_32G 0x0000f000 | ||
| 147 | #define L2C_SNP_ESR 0x00000800 | ||
| 148 | |||
| 149 | #endif /* __DCR_REGS_H__ */ | ||